Commit | Line | Data |
---|---|---|
afaf5a2d DS |
1 | /* |
2 | * QLogic iSCSI HBA Driver | |
4a4f51e9 | 3 | * Copyright (c) 2003-2013 QLogic Corporation |
afaf5a2d DS |
4 | * |
5 | * See LICENSE.qla4xxx for copyright and licensing details. | |
6 | */ | |
7 | ||
eee06a0f | 8 | #include <linux/ctype.h> |
afaf5a2d | 9 | #include "ql4_def.h" |
c0e344c9 DS |
10 | #include "ql4_glbl.h" |
11 | #include "ql4_dbg.h" | |
12 | #include "ql4_inline.h" | |
cfb27874 | 13 | #include "ql4_version.h" |
afaf5a2d | 14 | |
33693c7a VC |
15 | void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, |
16 | int in_count) | |
17 | { | |
18 | int i; | |
19 | ||
20 | /* Load all mailbox registers, except mailbox 0. */ | |
21 | for (i = 1; i < in_count; i++) | |
22 | writel(mbx_cmd[i], &ha->reg->mailbox[i]); | |
23 | ||
24 | /* Wakeup firmware */ | |
25 | writel(mbx_cmd[0], &ha->reg->mailbox[0]); | |
26 | readl(&ha->reg->mailbox[0]); | |
27 | writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status); | |
28 | readl(&ha->reg->ctrl_status); | |
29 | } | |
30 | ||
31 | void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count) | |
32 | { | |
33 | int intr_status; | |
34 | ||
35 | intr_status = readl(&ha->reg->ctrl_status); | |
36 | if (intr_status & INTR_PENDING) { | |
37 | /* | |
38 | * Service the interrupt. | |
39 | * The ISR will save the mailbox status registers | |
40 | * to a temporary storage location in the adapter structure. | |
41 | */ | |
42 | ha->mbox_status_count = out_count; | |
43 | ha->isp_ops->interrupt_service_routine(ha, intr_status); | |
44 | } | |
45 | } | |
afaf5a2d | 46 | |
5c19b92a VC |
47 | /** |
48 | * qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts? | |
49 | * @ha: Pointer to host adapter structure. | |
50 | * @ret: 1=polling mode, 0=non-polling mode | |
51 | **/ | |
52 | static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha) | |
53 | { | |
54 | int rval = 1; | |
55 | ||
b37ca418 | 56 | if (is_qla8032(ha) || is_qla8042(ha)) { |
5c19b92a VC |
57 | if (test_bit(AF_IRQ_ATTACHED, &ha->flags) && |
58 | test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) | |
59 | rval = 0; | |
60 | } else { | |
61 | if (test_bit(AF_IRQ_ATTACHED, &ha->flags) && | |
62 | test_bit(AF_INTERRUPTS_ON, &ha->flags) && | |
63 | test_bit(AF_ONLINE, &ha->flags) && | |
64 | !test_bit(AF_HA_REMOVAL, &ha->flags)) | |
65 | rval = 0; | |
66 | } | |
67 | ||
68 | return rval; | |
69 | } | |
70 | ||
afaf5a2d DS |
71 | /** |
72 | * qla4xxx_mailbox_command - issues mailbox commands | |
73 | * @ha: Pointer to host adapter structure. | |
74 | * @inCount: number of mailbox registers to load. | |
75 | * @outCount: number of mailbox registers to return. | |
76 | * @mbx_cmd: data pointer for mailbox in registers. | |
77 | * @mbx_sts: data pointer for mailbox out registers. | |
78 | * | |
70f23fd6 | 79 | * This routine issue mailbox commands and waits for completion. |
afaf5a2d DS |
80 | * If outCount is 0, this routine completes successfully WITHOUT waiting |
81 | * for the mailbox command to complete. | |
82 | **/ | |
f4f5df23 VC |
83 | int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount, |
84 | uint8_t outCount, uint32_t *mbx_cmd, | |
85 | uint32_t *mbx_sts) | |
afaf5a2d DS |
86 | { |
87 | int status = QLA_ERROR; | |
88 | uint8_t i; | |
89 | u_long wait_count; | |
afaf5a2d | 90 | unsigned long flags = 0; |
99b53bf5 | 91 | uint32_t dev_state; |
afaf5a2d DS |
92 | |
93 | /* Make sure that pointers are valid */ | |
94 | if (!mbx_cmd || !mbx_sts) { | |
95 | DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts " | |
96 | "pointer\n", ha->host_no, __func__)); | |
477ffb9d DS |
97 | return status; |
98 | } | |
21033639 | 99 | |
13483730 MC |
100 | if (is_qla40XX(ha)) { |
101 | if (test_bit(AF_HA_REMOVAL, &ha->flags)) { | |
102 | DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: " | |
103 | "prematurely completing mbx cmd as " | |
104 | "adapter removal detected\n", | |
105 | ha->host_no, __func__)); | |
106 | return status; | |
107 | } | |
108 | } | |
109 | ||
2232be0d LC |
110 | if ((is_aer_supported(ha)) && |
111 | (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) { | |
112 | DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, " | |
113 | "timeout MBX Exiting.\n", ha->host_no, __func__)); | |
114 | return status; | |
115 | } | |
116 | ||
477ffb9d DS |
117 | /* Mailbox code active */ |
118 | wait_count = MBOX_TOV * 100; | |
119 | ||
120 | while (wait_count--) { | |
121 | mutex_lock(&ha->mbox_sem); | |
122 | if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) { | |
123 | set_bit(AF_MBOX_COMMAND, &ha->flags); | |
124 | mutex_unlock(&ha->mbox_sem); | |
125 | break; | |
126 | } | |
127 | mutex_unlock(&ha->mbox_sem); | |
128 | if (!wait_count) { | |
129 | DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n", | |
130 | ha->host_no, __func__)); | |
131 | return status; | |
132 | } | |
133 | msleep(10); | |
afaf5a2d DS |
134 | } |
135 | ||
6e7b4292 | 136 | if (is_qla80XX(ha)) { |
5f50aa3a LC |
137 | if (test_bit(AF_FW_RECOVERY, &ha->flags)) { |
138 | DEBUG2(ql4_printk(KERN_WARNING, ha, | |
139 | "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n", | |
140 | ha->host_no, __func__)); | |
141 | goto mbox_exit; | |
142 | } | |
143 | /* Do not send any mbx cmd if h/w is in failed state*/ | |
33693c7a VC |
144 | ha->isp_ops->idc_lock(ha); |
145 | dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); | |
146 | ha->isp_ops->idc_unlock(ha); | |
de8c72da | 147 | if (dev_state == QLA8XXX_DEV_FAILED) { |
5f50aa3a LC |
148 | ql4_printk(KERN_WARNING, ha, |
149 | "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n", | |
150 | ha->host_no, __func__); | |
151 | goto mbox_exit; | |
152 | } | |
153 | } | |
154 | ||
afaf5a2d | 155 | spin_lock_irqsave(&ha->hardware_lock, flags); |
f4f5df23 | 156 | |
afaf5a2d DS |
157 | ha->mbox_status_count = outCount; |
158 | for (i = 0; i < outCount; i++) | |
159 | ha->mbox_status[i] = 0; | |
160 | ||
33693c7a VC |
161 | /* Queue the mailbox command to the firmware */ |
162 | ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount); | |
afaf5a2d | 163 | |
afaf5a2d DS |
164 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
165 | ||
166 | /* Wait for completion */ | |
afaf5a2d DS |
167 | |
168 | /* | |
169 | * If we don't want status, don't wait for the mailbox command to | |
170 | * complete. For example, MBOX_CMD_RESET_FW doesn't return status, | |
171 | * you must poll the inbound Interrupt Mask for completion. | |
172 | */ | |
173 | if (outCount == 0) { | |
174 | status = QLA_SUCCESS; | |
afaf5a2d DS |
175 | goto mbox_exit; |
176 | } | |
afaf5a2d | 177 | |
f4f5df23 VC |
178 | /* |
179 | * Wait for completion: Poll or completion queue | |
180 | */ | |
5c19b92a | 181 | if (qla4xxx_is_intr_poll_mode(ha)) { |
f4f5df23 VC |
182 | /* Poll for command to complete */ |
183 | wait_count = jiffies + MBOX_TOV * HZ; | |
184 | while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) { | |
185 | if (time_after_eq(jiffies, wait_count)) | |
186 | break; | |
afaf5a2d DS |
187 | /* |
188 | * Service the interrupt. | |
189 | * The ISR will save the mailbox status registers | |
190 | * to a temporary storage location in the adapter | |
191 | * structure. | |
192 | */ | |
f4f5df23 | 193 | spin_lock_irqsave(&ha->hardware_lock, flags); |
33693c7a | 194 | ha->isp_ops->process_mailbox_interrupt(ha, outCount); |
f4f5df23 VC |
195 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
196 | msleep(10); | |
afaf5a2d | 197 | } |
5c19b92a VC |
198 | } else { |
199 | /* Do not poll for completion. Use completion queue */ | |
200 | set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags); | |
201 | wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ); | |
202 | clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags); | |
afaf5a2d | 203 | } |
afaf5a2d DS |
204 | |
205 | /* Check for mailbox timeout. */ | |
206 | if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) { | |
6e7b4292 | 207 | if (is_qla80XX(ha) && |
21033639 NJ |
208 | test_bit(AF_FW_RECOVERY, &ha->flags)) { |
209 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
210 | "scsi%ld: %s: prematurely completing mbx cmd as " | |
211 | "firmware recovery detected\n", | |
212 | ha->host_no, __func__)); | |
213 | goto mbox_exit; | |
214 | } | |
b1f5df3b VC |
215 | ql4_printk(KERN_WARNING, ha, "scsi%ld: Mailbox Cmd 0x%08X timed out, Scheduling Adapter Reset\n", |
216 | ha->host_no, mbx_cmd[0]); | |
afaf5a2d DS |
217 | ha->mailbox_timeout_count++; |
218 | mbx_sts[0] = (-1); | |
219 | set_bit(DPC_RESET_HA, &ha->dpc_flags); | |
e6bd0ebd GM |
220 | if (is_qla8022(ha)) { |
221 | ql4_printk(KERN_INFO, ha, | |
222 | "disabling pause transmit on port 0 & 1.\n"); | |
f8086f4f | 223 | qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, |
e6bd0ebd GM |
224 | CRB_NIU_XG_PAUSE_CTL_P0 | |
225 | CRB_NIU_XG_PAUSE_CTL_P1); | |
b37ca418 | 226 | } else if (is_qla8032(ha) || is_qla8042(ha)) { |
546fef27 TP |
227 | ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n", |
228 | __func__); | |
229 | qla4_83xx_disable_pause(ha); | |
e6bd0ebd | 230 | } |
afaf5a2d DS |
231 | goto mbox_exit; |
232 | } | |
233 | ||
234 | /* | |
235 | * Copy the mailbox out registers to the caller's mailbox in/out | |
236 | * structure. | |
237 | */ | |
238 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
239 | for (i = 0; i < outCount; i++) | |
240 | mbx_sts[i] = ha->mbox_status[i]; | |
241 | ||
242 | /* Set return status and error flags (if applicable). */ | |
243 | switch (ha->mbox_status[0]) { | |
244 | case MBOX_STS_COMMAND_COMPLETE: | |
245 | status = QLA_SUCCESS; | |
246 | break; | |
247 | ||
248 | case MBOX_STS_INTERMEDIATE_COMPLETION: | |
249 | status = QLA_SUCCESS; | |
250 | break; | |
251 | ||
252 | case MBOX_STS_BUSY: | |
b1f5df3b VC |
253 | ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: Cmd = %08X, ISP BUSY\n", |
254 | ha->host_no, __func__, mbx_cmd[0]); | |
afaf5a2d DS |
255 | ha->mailbox_timeout_count++; |
256 | break; | |
257 | ||
258 | default: | |
b1f5df3b VC |
259 | ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: FAILED, MBOX CMD = %08X, MBOX STS = %08X %08X %08X %08X %08X %08X %08X %08X\n", |
260 | ha->host_no, __func__, mbx_cmd[0], mbx_sts[0], | |
261 | mbx_sts[1], mbx_sts[2], mbx_sts[3], mbx_sts[4], | |
262 | mbx_sts[5], mbx_sts[6], mbx_sts[7]); | |
afaf5a2d DS |
263 | break; |
264 | } | |
265 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
266 | ||
267 | mbox_exit: | |
477ffb9d | 268 | mutex_lock(&ha->mbox_sem); |
afaf5a2d | 269 | clear_bit(AF_MBOX_COMMAND, &ha->flags); |
afaf5a2d | 270 | mutex_unlock(&ha->mbox_sem); |
477ffb9d | 271 | clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags); |
afaf5a2d DS |
272 | |
273 | return status; | |
274 | } | |
21033639 | 275 | |
068237c8 TP |
276 | /** |
277 | * qla4xxx_get_minidump_template - Get the firmware template | |
278 | * @ha: Pointer to host adapter structure. | |
279 | * @phys_addr: dma address for template | |
280 | * | |
281 | * Obtain the minidump template from firmware during initialization | |
282 | * as it may not be available when minidump is desired. | |
283 | **/ | |
284 | int qla4xxx_get_minidump_template(struct scsi_qla_host *ha, | |
285 | dma_addr_t phys_addr) | |
286 | { | |
287 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
288 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
289 | int status; | |
290 | ||
291 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
292 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
293 | ||
294 | mbox_cmd[0] = MBOX_CMD_MINIDUMP; | |
295 | mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND; | |
296 | mbox_cmd[2] = LSDW(phys_addr); | |
297 | mbox_cmd[3] = MSDW(phys_addr); | |
298 | mbox_cmd[4] = ha->fw_dump_tmplt_size; | |
299 | mbox_cmd[5] = 0; | |
300 | ||
301 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], | |
302 | &mbox_sts[0]); | |
303 | if (status != QLA_SUCCESS) { | |
304 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
305 | "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n", | |
306 | ha->host_no, __func__, mbox_cmd[0], | |
307 | mbox_sts[0], mbox_sts[1])); | |
308 | } | |
309 | return status; | |
310 | } | |
311 | ||
312 | /** | |
313 | * qla4xxx_req_template_size - Get minidump template size from firmware. | |
314 | * @ha: Pointer to host adapter structure. | |
315 | **/ | |
316 | int qla4xxx_req_template_size(struct scsi_qla_host *ha) | |
317 | { | |
318 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
319 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
320 | int status; | |
321 | ||
322 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
323 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
324 | ||
325 | mbox_cmd[0] = MBOX_CMD_MINIDUMP; | |
326 | mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND; | |
327 | ||
328 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0], | |
329 | &mbox_sts[0]); | |
330 | if (status == QLA_SUCCESS) { | |
331 | ha->fw_dump_tmplt_size = mbox_sts[1]; | |
332 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
333 | "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n", | |
334 | __func__, mbox_sts[0], mbox_sts[1], | |
335 | mbox_sts[2], mbox_sts[3], mbox_sts[4], | |
336 | mbox_sts[5], mbox_sts[6], mbox_sts[7])); | |
337 | if (ha->fw_dump_tmplt_size == 0) | |
338 | status = QLA_ERROR; | |
339 | } else { | |
340 | ql4_printk(KERN_WARNING, ha, | |
341 | "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n", | |
342 | __func__, mbox_sts[0], mbox_sts[1]); | |
343 | status = QLA_ERROR; | |
344 | } | |
345 | ||
346 | return status; | |
347 | } | |
348 | ||
21033639 NJ |
349 | void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha) |
350 | { | |
351 | set_bit(AF_FW_RECOVERY, &ha->flags); | |
352 | ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n", | |
353 | ha->host_no, __func__); | |
354 | ||
355 | if (test_bit(AF_MBOX_COMMAND, &ha->flags)) { | |
356 | if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) { | |
357 | complete(&ha->mbx_intr_comp); | |
358 | ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw " | |
359 | "recovery, doing premature completion of " | |
360 | "mbx cmd\n", ha->host_no, __func__); | |
361 | ||
362 | } else { | |
363 | set_bit(AF_MBOX_COMMAND_DONE, &ha->flags); | |
364 | ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw " | |
365 | "recovery, doing premature completion of " | |
366 | "polling mbx cmd\n", ha->host_no, __func__); | |
367 | } | |
368 | } | |
369 | } | |
afaf5a2d | 370 | |
f4f5df23 | 371 | static uint8_t |
2a49a78e VC |
372 | qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, |
373 | uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma) | |
374 | { | |
375 | memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT); | |
376 | memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT); | |
2657c800 SS |
377 | |
378 | if (is_qla8022(ha)) | |
f8086f4f | 379 | qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0); |
2657c800 | 380 | |
2a49a78e VC |
381 | mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE; |
382 | mbox_cmd[1] = 0; | |
383 | mbox_cmd[2] = LSDW(init_fw_cb_dma); | |
384 | mbox_cmd[3] = MSDW(init_fw_cb_dma); | |
385 | mbox_cmd[4] = sizeof(struct addr_ctrl_blk); | |
2a49a78e VC |
386 | |
387 | if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) != | |
388 | QLA_SUCCESS) { | |
389 | DEBUG2(printk(KERN_WARNING "scsi%ld: %s: " | |
390 | "MBOX_CMD_INITIALIZE_FIRMWARE" | |
391 | " failed w/ status %04X\n", | |
392 | ha->host_no, __func__, mbox_sts[0])); | |
393 | return QLA_ERROR; | |
394 | } | |
395 | return QLA_SUCCESS; | |
396 | } | |
397 | ||
d00efe3f | 398 | uint8_t |
2a49a78e VC |
399 | qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, |
400 | uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma) | |
401 | { | |
402 | memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT); | |
403 | memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT); | |
404 | mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK; | |
405 | mbox_cmd[2] = LSDW(init_fw_cb_dma); | |
406 | mbox_cmd[3] = MSDW(init_fw_cb_dma); | |
407 | mbox_cmd[4] = sizeof(struct addr_ctrl_blk); | |
408 | ||
409 | if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) != | |
410 | QLA_SUCCESS) { | |
411 | DEBUG2(printk(KERN_WARNING "scsi%ld: %s: " | |
412 | "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK" | |
413 | " failed w/ status %04X\n", | |
414 | ha->host_no, __func__, mbox_sts[0])); | |
415 | return QLA_ERROR; | |
416 | } | |
417 | return QLA_SUCCESS; | |
418 | } | |
419 | ||
f8e93412 HZ |
420 | uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state) |
421 | { | |
422 | uint8_t ipaddr_state; | |
423 | ||
424 | switch (fw_ipaddr_state) { | |
425 | case IP_ADDRSTATE_UNCONFIGURED: | |
426 | ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED; | |
427 | break; | |
428 | case IP_ADDRSTATE_INVALID: | |
429 | ipaddr_state = ISCSI_IPDDRESS_STATE_INVALID; | |
430 | break; | |
431 | case IP_ADDRSTATE_ACQUIRING: | |
432 | ipaddr_state = ISCSI_IPDDRESS_STATE_ACQUIRING; | |
433 | break; | |
434 | case IP_ADDRSTATE_TENTATIVE: | |
435 | ipaddr_state = ISCSI_IPDDRESS_STATE_TENTATIVE; | |
436 | break; | |
437 | case IP_ADDRSTATE_DEPRICATED: | |
438 | ipaddr_state = ISCSI_IPDDRESS_STATE_DEPRECATED; | |
439 | break; | |
440 | case IP_ADDRSTATE_PREFERRED: | |
441 | ipaddr_state = ISCSI_IPDDRESS_STATE_VALID; | |
442 | break; | |
443 | case IP_ADDRSTATE_DISABLING: | |
444 | ipaddr_state = ISCSI_IPDDRESS_STATE_DISABLING; | |
445 | break; | |
446 | default: | |
447 | ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED; | |
448 | } | |
449 | return ipaddr_state; | |
450 | } | |
451 | ||
f4f5df23 | 452 | static void |
2a49a78e | 453 | qla4xxx_update_local_ip(struct scsi_qla_host *ha, |
2bab08fc | 454 | struct addr_ctrl_blk *init_fw_cb) |
2a49a78e | 455 | { |
2bab08fc VC |
456 | ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts); |
457 | ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts); | |
458 | ha->ip_config.ipv4_addr_state = | |
f8e93412 | 459 | qla4xxx_set_ipaddr_state(init_fw_cb->ipv4_addr_state); |
943c157b VC |
460 | ha->ip_config.eth_mtu_size = |
461 | le16_to_cpu(init_fw_cb->eth_mtu_size); | |
2ada7fc5 | 462 | ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port); |
2bab08fc VC |
463 | |
464 | if (ha->acb_version == ACB_SUPPORTED) { | |
465 | ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts); | |
466 | ha->ip_config.ipv6_addl_options = | |
467 | le16_to_cpu(init_fw_cb->ipv6_addtl_opts); | |
f8e93412 HZ |
468 | ha->ip_config.ipv6_tcp_options = |
469 | le16_to_cpu(init_fw_cb->ipv6_tcp_opts); | |
2bab08fc VC |
470 | } |
471 | ||
2a49a78e | 472 | /* Save IPv4 Address Info */ |
2bab08fc VC |
473 | memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr, |
474 | min(sizeof(ha->ip_config.ip_address), | |
475 | sizeof(init_fw_cb->ipv4_addr))); | |
476 | memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet, | |
477 | min(sizeof(ha->ip_config.subnet_mask), | |
478 | sizeof(init_fw_cb->ipv4_subnet))); | |
479 | memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr, | |
480 | min(sizeof(ha->ip_config.gateway), | |
481 | sizeof(init_fw_cb->ipv4_gw_addr))); | |
2a49a78e | 482 | |
6ac73e8c | 483 | ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag); |
f8e93412 HZ |
484 | ha->ip_config.control = init_fw_cb->control; |
485 | ha->ip_config.tcp_wsf = init_fw_cb->ipv4_tcp_wsf; | |
486 | ha->ip_config.ipv4_tos = init_fw_cb->ipv4_tos; | |
487 | ha->ip_config.ipv4_cache_id = init_fw_cb->ipv4_cacheid; | |
488 | ha->ip_config.ipv4_alt_cid_len = init_fw_cb->ipv4_dhcp_alt_cid_len; | |
489 | memcpy(ha->ip_config.ipv4_alt_cid, init_fw_cb->ipv4_dhcp_alt_cid, | |
490 | min(sizeof(ha->ip_config.ipv4_alt_cid), | |
491 | sizeof(init_fw_cb->ipv4_dhcp_alt_cid))); | |
492 | ha->ip_config.ipv4_vid_len = init_fw_cb->ipv4_dhcp_vid_len; | |
493 | memcpy(ha->ip_config.ipv4_vid, init_fw_cb->ipv4_dhcp_vid, | |
494 | min(sizeof(ha->ip_config.ipv4_vid), | |
495 | sizeof(init_fw_cb->ipv4_dhcp_vid))); | |
496 | ha->ip_config.ipv4_ttl = init_fw_cb->ipv4_ttl; | |
497 | ha->ip_config.def_timeout = le16_to_cpu(init_fw_cb->def_timeout); | |
498 | ha->ip_config.abort_timer = init_fw_cb->abort_timer; | |
499 | ha->ip_config.iscsi_options = le16_to_cpu(init_fw_cb->iscsi_opts); | |
500 | ha->ip_config.iscsi_max_pdu_size = | |
501 | le16_to_cpu(init_fw_cb->iscsi_max_pdu_size); | |
502 | ha->ip_config.iscsi_first_burst_len = | |
503 | le16_to_cpu(init_fw_cb->iscsi_fburst_len); | |
504 | ha->ip_config.iscsi_max_outstnd_r2t = | |
505 | le16_to_cpu(init_fw_cb->iscsi_max_outstnd_r2t); | |
506 | ha->ip_config.iscsi_max_burst_len = | |
507 | le16_to_cpu(init_fw_cb->iscsi_max_burst_len); | |
508 | memcpy(ha->ip_config.iscsi_name, init_fw_cb->iscsi_name, | |
509 | min(sizeof(ha->ip_config.iscsi_name), | |
510 | sizeof(init_fw_cb->iscsi_name))); | |
6ac73e8c | 511 | |
2a49a78e VC |
512 | if (is_ipv6_enabled(ha)) { |
513 | /* Save IPv6 Address */ | |
2bab08fc | 514 | ha->ip_config.ipv6_link_local_state = |
f8e93412 | 515 | qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_lnk_lcl_addr_state); |
2bab08fc | 516 | ha->ip_config.ipv6_addr0_state = |
f8e93412 | 517 | qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_addr0_state); |
2bab08fc | 518 | ha->ip_config.ipv6_addr1_state = |
f8e93412 HZ |
519 | qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_addr1_state); |
520 | ||
521 | switch (le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state)) { | |
522 | case IPV6_RTRSTATE_UNKNOWN: | |
523 | ha->ip_config.ipv6_default_router_state = | |
524 | ISCSI_ROUTER_STATE_UNKNOWN; | |
525 | break; | |
526 | case IPV6_RTRSTATE_MANUAL: | |
527 | ha->ip_config.ipv6_default_router_state = | |
528 | ISCSI_ROUTER_STATE_MANUAL; | |
529 | break; | |
530 | case IPV6_RTRSTATE_ADVERTISED: | |
531 | ha->ip_config.ipv6_default_router_state = | |
532 | ISCSI_ROUTER_STATE_ADVERTISED; | |
533 | break; | |
534 | case IPV6_RTRSTATE_STALE: | |
535 | ha->ip_config.ipv6_default_router_state = | |
536 | ISCSI_ROUTER_STATE_STALE; | |
537 | break; | |
538 | default: | |
539 | ha->ip_config.ipv6_default_router_state = | |
540 | ISCSI_ROUTER_STATE_UNKNOWN; | |
541 | } | |
542 | ||
2bab08fc VC |
543 | ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE; |
544 | ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80; | |
545 | ||
546 | memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8], | |
547 | init_fw_cb->ipv6_if_id, | |
548 | min(sizeof(ha->ip_config.ipv6_link_local_addr)/2, | |
549 | sizeof(init_fw_cb->ipv6_if_id))); | |
550 | memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0, | |
551 | min(sizeof(ha->ip_config.ipv6_addr0), | |
552 | sizeof(init_fw_cb->ipv6_addr0))); | |
553 | memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1, | |
554 | min(sizeof(ha->ip_config.ipv6_addr1), | |
555 | sizeof(init_fw_cb->ipv6_addr1))); | |
556 | memcpy(&ha->ip_config.ipv6_default_router_addr, | |
557 | init_fw_cb->ipv6_dflt_rtr_addr, | |
558 | min(sizeof(ha->ip_config.ipv6_default_router_addr), | |
559 | sizeof(init_fw_cb->ipv6_dflt_rtr_addr))); | |
6ac73e8c VC |
560 | ha->ip_config.ipv6_vlan_tag = |
561 | be16_to_cpu(init_fw_cb->ipv6_vlan_tag); | |
2ada7fc5 | 562 | ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port); |
f8e93412 HZ |
563 | ha->ip_config.ipv6_cache_id = init_fw_cb->ipv6_cache_id; |
564 | ha->ip_config.ipv6_flow_lbl = | |
565 | le16_to_cpu(init_fw_cb->ipv6_flow_lbl); | |
566 | ha->ip_config.ipv6_traffic_class = | |
567 | init_fw_cb->ipv6_traffic_class; | |
568 | ha->ip_config.ipv6_hop_limit = init_fw_cb->ipv6_hop_limit; | |
569 | ha->ip_config.ipv6_nd_reach_time = | |
570 | le32_to_cpu(init_fw_cb->ipv6_nd_reach_time); | |
571 | ha->ip_config.ipv6_nd_rexmit_timer = | |
572 | le32_to_cpu(init_fw_cb->ipv6_nd_rexmit_timer); | |
573 | ha->ip_config.ipv6_nd_stale_timeout = | |
574 | le32_to_cpu(init_fw_cb->ipv6_nd_stale_timeout); | |
575 | ha->ip_config.ipv6_dup_addr_detect_count = | |
576 | init_fw_cb->ipv6_dup_addr_detect_count; | |
577 | ha->ip_config.ipv6_gw_advrt_mtu = | |
578 | le32_to_cpu(init_fw_cb->ipv6_gw_advrt_mtu); | |
579 | ha->ip_config.ipv6_tcp_wsf = init_fw_cb->ipv6_tcp_wsf; | |
2a49a78e VC |
580 | } |
581 | } | |
582 | ||
d00efe3f | 583 | uint8_t |
2a49a78e VC |
584 | qla4xxx_update_local_ifcb(struct scsi_qla_host *ha, |
585 | uint32_t *mbox_cmd, | |
586 | uint32_t *mbox_sts, | |
587 | struct addr_ctrl_blk *init_fw_cb, | |
588 | dma_addr_t init_fw_cb_dma) | |
589 | { | |
590 | if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma) | |
591 | != QLA_SUCCESS) { | |
592 | DEBUG2(printk(KERN_WARNING | |
593 | "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n", | |
594 | ha->host_no, __func__)); | |
595 | return QLA_ERROR; | |
596 | } | |
597 | ||
598 | DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk))); | |
599 | ||
600 | /* Save some info in adapter structure. */ | |
601 | ha->acb_version = init_fw_cb->acb_version; | |
602 | ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options); | |
2a49a78e VC |
603 | ha->heartbeat_interval = init_fw_cb->hb_interval; |
604 | memcpy(ha->name_string, init_fw_cb->iscsi_name, | |
605 | min(sizeof(ha->name_string), | |
606 | sizeof(init_fw_cb->iscsi_name))); | |
13483730 | 607 | ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout); |
2a49a78e VC |
608 | /*memcpy(ha->alias, init_fw_cb->Alias, |
609 | min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/ | |
610 | ||
2a49a78e VC |
611 | qla4xxx_update_local_ip(ha, init_fw_cb); |
612 | ||
613 | return QLA_SUCCESS; | |
614 | } | |
615 | ||
afaf5a2d DS |
616 | /** |
617 | * qla4xxx_initialize_fw_cb - initializes firmware control block. | |
618 | * @ha: Pointer to host adapter structure. | |
619 | **/ | |
620 | int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha) | |
621 | { | |
2a49a78e | 622 | struct addr_ctrl_blk *init_fw_cb; |
afaf5a2d DS |
623 | dma_addr_t init_fw_cb_dma; |
624 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
625 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
626 | int status = QLA_ERROR; | |
627 | ||
628 | init_fw_cb = dma_alloc_coherent(&ha->pdev->dev, | |
2a49a78e | 629 | sizeof(struct addr_ctrl_blk), |
afaf5a2d DS |
630 | &init_fw_cb_dma, GFP_KERNEL); |
631 | if (init_fw_cb == NULL) { | |
632 | DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n", | |
633 | ha->host_no, __func__)); | |
beabe7c1 | 634 | goto exit_init_fw_cb_no_free; |
afaf5a2d | 635 | } |
2a49a78e | 636 | memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk)); |
afaf5a2d DS |
637 | |
638 | /* Get Initialize Firmware Control Block. */ | |
639 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
640 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
c0e344c9 | 641 | |
2a49a78e | 642 | if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) != |
afaf5a2d DS |
643 | QLA_SUCCESS) { |
644 | dma_free_coherent(&ha->pdev->dev, | |
2a49a78e | 645 | sizeof(struct addr_ctrl_blk), |
afaf5a2d | 646 | init_fw_cb, init_fw_cb_dma); |
2a49a78e | 647 | goto exit_init_fw_cb; |
afaf5a2d DS |
648 | } |
649 | ||
afaf5a2d | 650 | /* Fill in the request and response queue information. */ |
2a49a78e VC |
651 | init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out); |
652 | init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in); | |
653 | init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH); | |
654 | init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH); | |
655 | init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma)); | |
656 | init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma)); | |
657 | init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma)); | |
658 | init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma)); | |
659 | init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma)); | |
660 | init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma)); | |
afaf5a2d DS |
661 | |
662 | /* Set up required options. */ | |
2a49a78e | 663 | init_fw_cb->fw_options |= |
afaf5a2d DS |
664 | __constant_cpu_to_le16(FWOPT_SESSION_MODE | |
665 | FWOPT_INITIATOR_MODE); | |
2657c800 | 666 | |
6e7b4292 | 667 | if (is_qla80XX(ha)) |
2657c800 SS |
668 | init_fw_cb->fw_options |= |
669 | __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB); | |
670 | ||
2a49a78e | 671 | init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE); |
afaf5a2d | 672 | |
d32cee3c PM |
673 | init_fw_cb->add_fw_options = 0; |
674 | init_fw_cb->add_fw_options |= | |
b3a271a9 MR |
675 | __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT); |
676 | init_fw_cb->add_fw_options |= | |
677 | __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE); | |
d32cee3c | 678 | |
2a49a78e VC |
679 | if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) |
680 | != QLA_SUCCESS) { | |
681 | DEBUG2(printk(KERN_WARNING | |
682 | "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n", | |
683 | ha->host_no, __func__)); | |
684 | goto exit_init_fw_cb; | |
685 | } | |
c0e344c9 | 686 | |
2a49a78e VC |
687 | if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], |
688 | init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) { | |
689 | DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n", | |
690 | ha->host_no, __func__)); | |
691 | goto exit_init_fw_cb; | |
afaf5a2d | 692 | } |
2a49a78e VC |
693 | status = QLA_SUCCESS; |
694 | ||
695 | exit_init_fw_cb: | |
696 | dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), | |
697 | init_fw_cb, init_fw_cb_dma); | |
beabe7c1 | 698 | exit_init_fw_cb_no_free: |
afaf5a2d DS |
699 | return status; |
700 | } | |
701 | ||
702 | /** | |
703 | * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP | |
704 | * @ha: Pointer to host adapter structure. | |
705 | **/ | |
706 | int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha) | |
707 | { | |
2a49a78e | 708 | struct addr_ctrl_blk *init_fw_cb; |
afaf5a2d DS |
709 | dma_addr_t init_fw_cb_dma; |
710 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
711 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
712 | ||
713 | init_fw_cb = dma_alloc_coherent(&ha->pdev->dev, | |
2a49a78e | 714 | sizeof(struct addr_ctrl_blk), |
afaf5a2d DS |
715 | &init_fw_cb_dma, GFP_KERNEL); |
716 | if (init_fw_cb == NULL) { | |
717 | printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no, | |
718 | __func__); | |
beabe7c1 | 719 | return QLA_ERROR; |
afaf5a2d DS |
720 | } |
721 | ||
722 | /* Get Initialize Firmware Control Block. */ | |
2a49a78e VC |
723 | memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk)); |
724 | if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) != | |
afaf5a2d DS |
725 | QLA_SUCCESS) { |
726 | DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n", | |
727 | ha->host_no, __func__)); | |
728 | dma_free_coherent(&ha->pdev->dev, | |
2a49a78e | 729 | sizeof(struct addr_ctrl_blk), |
afaf5a2d DS |
730 | init_fw_cb, init_fw_cb_dma); |
731 | return QLA_ERROR; | |
732 | } | |
733 | ||
734 | /* Save IP Address. */ | |
2a49a78e VC |
735 | qla4xxx_update_local_ip(ha, init_fw_cb); |
736 | dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), | |
737 | init_fw_cb, init_fw_cb_dma); | |
afaf5a2d DS |
738 | |
739 | return QLA_SUCCESS; | |
740 | } | |
741 | ||
742 | /** | |
743 | * qla4xxx_get_firmware_state - gets firmware state of HBA | |
744 | * @ha: Pointer to host adapter structure. | |
745 | **/ | |
746 | int qla4xxx_get_firmware_state(struct scsi_qla_host * ha) | |
747 | { | |
748 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
749 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
750 | ||
751 | /* Get firmware version */ | |
752 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
753 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
c0e344c9 | 754 | |
afaf5a2d | 755 | mbox_cmd[0] = MBOX_CMD_GET_FW_STATE; |
c0e344c9 DS |
756 | |
757 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) != | |
afaf5a2d DS |
758 | QLA_SUCCESS) { |
759 | DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ " | |
760 | "status %04X\n", ha->host_no, __func__, | |
761 | mbox_sts[0])); | |
762 | return QLA_ERROR; | |
763 | } | |
764 | ha->firmware_state = mbox_sts[1]; | |
765 | ha->board_id = mbox_sts[2]; | |
766 | ha->addl_fw_state = mbox_sts[3]; | |
767 | DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n", | |
768 | ha->host_no, __func__, ha->firmware_state);) | |
769 | ||
f4f5df23 | 770 | return QLA_SUCCESS; |
afaf5a2d DS |
771 | } |
772 | ||
773 | /** | |
774 | * qla4xxx_get_firmware_status - retrieves firmware status | |
775 | * @ha: Pointer to host adapter structure. | |
776 | **/ | |
777 | int qla4xxx_get_firmware_status(struct scsi_qla_host * ha) | |
778 | { | |
779 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
780 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
781 | ||
782 | /* Get firmware version */ | |
783 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
784 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
c0e344c9 | 785 | |
afaf5a2d | 786 | mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS; |
c0e344c9 DS |
787 | |
788 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) != | |
afaf5a2d DS |
789 | QLA_SUCCESS) { |
790 | DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ " | |
791 | "status %04X\n", ha->host_no, __func__, | |
792 | mbox_sts[0])); | |
793 | return QLA_ERROR; | |
794 | } | |
f4f5df23 | 795 | |
5b1c1bff KH |
796 | /* High-water mark of IOCBs */ |
797 | ha->iocb_hiwat = mbox_sts[2]; | |
798 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
799 | "%s: firmware IOCBs available = %d\n", __func__, | |
800 | ha->iocb_hiwat)); | |
801 | ||
802 | if (ha->iocb_hiwat > IOCB_HIWAT_CUSHION) | |
803 | ha->iocb_hiwat -= IOCB_HIWAT_CUSHION; | |
804 | ||
805 | /* Ideally, we should not enter this code, as the # of firmware | |
806 | * IOCBs is hard-coded in the firmware. We set a default | |
807 | * iocb_hiwat here just in case */ | |
808 | if (ha->iocb_hiwat == 0) { | |
809 | ha->iocb_hiwat = REQUEST_QUEUE_DEPTH / 4; | |
810 | DEBUG2(ql4_printk(KERN_WARNING, ha, | |
811 | "%s: Setting IOCB's to = %d\n", __func__, | |
812 | ha->iocb_hiwat)); | |
813 | } | |
f4f5df23 | 814 | |
afaf5a2d DS |
815 | return QLA_SUCCESS; |
816 | } | |
817 | ||
818 | /** | |
819 | * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry | |
820 | * @ha: Pointer to host adapter structure. | |
821 | * @fw_ddb_index: Firmware's device database index | |
822 | * @fw_ddb_entry: Pointer to firmware's device database entry structure | |
823 | * @num_valid_ddb_entries: Pointer to number of valid ddb entries | |
824 | * @next_ddb_index: Pointer to next valid device database index | |
825 | * @fw_ddb_device_state: Pointer to device state | |
826 | **/ | |
827 | int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha, | |
828 | uint16_t fw_ddb_index, | |
829 | struct dev_db_entry *fw_ddb_entry, | |
830 | dma_addr_t fw_ddb_entry_dma, | |
831 | uint32_t *num_valid_ddb_entries, | |
832 | uint32_t *next_ddb_index, | |
833 | uint32_t *fw_ddb_device_state, | |
834 | uint32_t *conn_err_detail, | |
835 | uint16_t *tcp_source_port_num, | |
836 | uint16_t *connection_id) | |
837 | { | |
838 | int status = QLA_ERROR; | |
2a49a78e | 839 | uint16_t options; |
afaf5a2d DS |
840 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
841 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
842 | ||
843 | /* Make sure the device index is valid */ | |
844 | if (fw_ddb_index >= MAX_DDB_ENTRIES) { | |
f4f5df23 | 845 | DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n", |
afaf5a2d DS |
846 | ha->host_no, __func__, fw_ddb_index)); |
847 | goto exit_get_fwddb; | |
848 | } | |
849 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
850 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
981c982c LC |
851 | if (fw_ddb_entry) |
852 | memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry)); | |
c0e344c9 | 853 | |
afaf5a2d DS |
854 | mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY; |
855 | mbox_cmd[1] = (uint32_t) fw_ddb_index; | |
856 | mbox_cmd[2] = LSDW(fw_ddb_entry_dma); | |
857 | mbox_cmd[3] = MSDW(fw_ddb_entry_dma); | |
c0e344c9 DS |
858 | mbox_cmd[4] = sizeof(struct dev_db_entry); |
859 | ||
860 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) == | |
afaf5a2d DS |
861 | QLA_ERROR) { |
862 | DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed" | |
863 | " with status 0x%04X\n", ha->host_no, __func__, | |
864 | mbox_sts[0])); | |
865 | goto exit_get_fwddb; | |
866 | } | |
867 | if (fw_ddb_index != mbox_sts[1]) { | |
f4f5df23 | 868 | DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n", |
afaf5a2d DS |
869 | ha->host_no, __func__, fw_ddb_index, |
870 | mbox_sts[1])); | |
871 | goto exit_get_fwddb; | |
872 | } | |
873 | if (fw_ddb_entry) { | |
2a49a78e VC |
874 | options = le16_to_cpu(fw_ddb_entry->options); |
875 | if (options & DDB_OPT_IPV6_DEVICE) { | |
c2660df3 | 876 | ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d " |
2a49a78e VC |
877 | "Next %d State %04x ConnErr %08x %pI6 " |
878 | ":%04d \"%s\"\n", __func__, fw_ddb_index, | |
879 | mbox_sts[0], mbox_sts[2], mbox_sts[3], | |
880 | mbox_sts[4], mbox_sts[5], | |
881 | fw_ddb_entry->ip_addr, | |
882 | le16_to_cpu(fw_ddb_entry->port), | |
883 | fw_ddb_entry->iscsi_name); | |
884 | } else { | |
c2660df3 | 885 | ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d " |
2a49a78e VC |
886 | "Next %d State %04x ConnErr %08x %pI4 " |
887 | ":%04d \"%s\"\n", __func__, fw_ddb_index, | |
888 | mbox_sts[0], mbox_sts[2], mbox_sts[3], | |
889 | mbox_sts[4], mbox_sts[5], | |
890 | fw_ddb_entry->ip_addr, | |
891 | le16_to_cpu(fw_ddb_entry->port), | |
892 | fw_ddb_entry->iscsi_name); | |
893 | } | |
afaf5a2d DS |
894 | } |
895 | if (num_valid_ddb_entries) | |
896 | *num_valid_ddb_entries = mbox_sts[2]; | |
897 | if (next_ddb_index) | |
898 | *next_ddb_index = mbox_sts[3]; | |
899 | if (fw_ddb_device_state) | |
900 | *fw_ddb_device_state = mbox_sts[4]; | |
901 | ||
902 | /* | |
903 | * RA: This mailbox has been changed to pass connection error and | |
904 | * details. Its true for ISP4010 as per Version E - Not sure when it | |
905 | * was changed. Get the time2wait from the fw_dd_entry field : | |
906 | * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY | |
907 | * struct. | |
908 | */ | |
909 | if (conn_err_detail) | |
910 | *conn_err_detail = mbox_sts[5]; | |
911 | if (tcp_source_port_num) | |
1482338f | 912 | *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16); |
afaf5a2d DS |
913 | if (connection_id) |
914 | *connection_id = (uint16_t) mbox_sts[6] & 0x00FF; | |
915 | status = QLA_SUCCESS; | |
916 | ||
917 | exit_get_fwddb: | |
918 | return status; | |
919 | } | |
920 | ||
b3a271a9 MR |
921 | int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index) |
922 | { | |
923 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
924 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
925 | int status; | |
926 | ||
927 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
928 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
929 | ||
930 | mbox_cmd[0] = MBOX_CMD_CONN_OPEN; | |
931 | mbox_cmd[1] = fw_ddb_index; | |
932 | ||
933 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], | |
934 | &mbox_sts[0]); | |
935 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
936 | "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n", | |
937 | __func__, status, mbox_sts[0], mbox_sts[1])); | |
938 | return status; | |
939 | } | |
940 | ||
afaf5a2d DS |
941 | /** |
942 | * qla4xxx_set_fwddb_entry - sets a ddb entry. | |
943 | * @ha: Pointer to host adapter structure. | |
944 | * @fw_ddb_index: Firmware's device database index | |
b3a271a9 MR |
945 | * @fw_ddb_entry_dma: dma address of ddb entry |
946 | * @mbx_sts: mailbox 0 to be returned or NULL | |
afaf5a2d DS |
947 | * |
948 | * This routine initializes or updates the adapter's device database | |
b3a271a9 | 949 | * entry for the specified device. |
afaf5a2d DS |
950 | **/ |
951 | int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index, | |
b3a271a9 | 952 | dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts) |
afaf5a2d DS |
953 | { |
954 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
955 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
f4f5df23 | 956 | int status; |
afaf5a2d DS |
957 | |
958 | /* Do not wait for completion. The firmware will send us an | |
959 | * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status. | |
960 | */ | |
961 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
962 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
963 | ||
964 | mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY; | |
965 | mbox_cmd[1] = (uint32_t) fw_ddb_index; | |
966 | mbox_cmd[2] = LSDW(fw_ddb_entry_dma); | |
967 | mbox_cmd[3] = MSDW(fw_ddb_entry_dma); | |
c0e344c9 | 968 | mbox_cmd[4] = sizeof(struct dev_db_entry); |
afaf5a2d | 969 | |
f4f5df23 | 970 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], |
b3a271a9 MR |
971 | &mbox_sts[0]); |
972 | if (mbx_sts) | |
973 | *mbx_sts = mbox_sts[0]; | |
f4f5df23 VC |
974 | DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n", |
975 | ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);) | |
976 | ||
977 | return status; | |
afaf5a2d DS |
978 | } |
979 | ||
b3a271a9 MR |
980 | int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha, |
981 | struct ddb_entry *ddb_entry, int options) | |
982 | { | |
983 | int status; | |
984 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
985 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
986 | ||
987 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
988 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
989 | ||
990 | mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT; | |
991 | mbox_cmd[1] = ddb_entry->fw_ddb_index; | |
992 | mbox_cmd[3] = options; | |
993 | ||
994 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], | |
995 | &mbox_sts[0]); | |
996 | if (status != QLA_SUCCESS) { | |
997 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
998 | "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT " | |
999 | "failed sts %04X %04X", __func__, | |
1000 | mbox_sts[0], mbox_sts[1])); | |
de2efea6 NJ |
1001 | if ((mbox_sts[0] == MBOX_STS_COMMAND_ERROR) && |
1002 | (mbox_sts[1] == DDB_NOT_LOGGED_IN)) { | |
1003 | set_bit(DDB_CONN_CLOSE_FAILURE, &ddb_entry->flags); | |
1004 | } | |
b3a271a9 MR |
1005 | } |
1006 | ||
1007 | return status; | |
1008 | } | |
1009 | ||
afaf5a2d DS |
1010 | /** |
1011 | * qla4xxx_get_crash_record - retrieves crash record. | |
1012 | * @ha: Pointer to host adapter structure. | |
1013 | * | |
1014 | * This routine retrieves a crash record from the QLA4010 after an 8002h aen. | |
1015 | **/ | |
1016 | void qla4xxx_get_crash_record(struct scsi_qla_host * ha) | |
1017 | { | |
1018 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1019 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1020 | struct crash_record *crash_record = NULL; | |
1021 | dma_addr_t crash_record_dma = 0; | |
1022 | uint32_t crash_record_size = 0; | |
c0e344c9 | 1023 | |
afaf5a2d DS |
1024 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
1025 | memset(&mbox_sts, 0, sizeof(mbox_cmd)); | |
1026 | ||
1027 | /* Get size of crash record. */ | |
1028 | mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD; | |
c0e344c9 DS |
1029 | |
1030 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) != | |
afaf5a2d DS |
1031 | QLA_SUCCESS) { |
1032 | DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n", | |
1033 | ha->host_no, __func__)); | |
1034 | goto exit_get_crash_record; | |
1035 | } | |
1036 | crash_record_size = mbox_sts[4]; | |
1037 | if (crash_record_size == 0) { | |
1038 | DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n", | |
1039 | ha->host_no, __func__)); | |
1040 | goto exit_get_crash_record; | |
1041 | } | |
1042 | ||
1043 | /* Alloc Memory for Crash Record. */ | |
1044 | crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size, | |
1045 | &crash_record_dma, GFP_KERNEL); | |
1046 | if (crash_record == NULL) | |
1047 | goto exit_get_crash_record; | |
1048 | ||
1049 | /* Get Crash Record. */ | |
c0e344c9 DS |
1050 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
1051 | memset(&mbox_sts, 0, sizeof(mbox_cmd)); | |
1052 | ||
afaf5a2d DS |
1053 | mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD; |
1054 | mbox_cmd[2] = LSDW(crash_record_dma); | |
1055 | mbox_cmd[3] = MSDW(crash_record_dma); | |
1056 | mbox_cmd[4] = crash_record_size; | |
c0e344c9 DS |
1057 | |
1058 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) != | |
afaf5a2d DS |
1059 | QLA_SUCCESS) |
1060 | goto exit_get_crash_record; | |
1061 | ||
1062 | /* Dump Crash Record. */ | |
1063 | ||
1064 | exit_get_crash_record: | |
1065 | if (crash_record) | |
1066 | dma_free_coherent(&ha->pdev->dev, crash_record_size, | |
1067 | crash_record, crash_record_dma); | |
1068 | } | |
1069 | ||
1070 | /** | |
1071 | * qla4xxx_get_conn_event_log - retrieves connection event log | |
1072 | * @ha: Pointer to host adapter structure. | |
1073 | **/ | |
1074 | void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha) | |
1075 | { | |
1076 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1077 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1078 | struct conn_event_log_entry *event_log = NULL; | |
1079 | dma_addr_t event_log_dma = 0; | |
1080 | uint32_t event_log_size = 0; | |
1081 | uint32_t num_valid_entries; | |
1082 | uint32_t oldest_entry = 0; | |
1083 | uint32_t max_event_log_entries; | |
1084 | uint8_t i; | |
1085 | ||
afaf5a2d DS |
1086 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
1087 | memset(&mbox_sts, 0, sizeof(mbox_cmd)); | |
1088 | ||
1089 | /* Get size of crash record. */ | |
1090 | mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG; | |
c0e344c9 DS |
1091 | |
1092 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) != | |
afaf5a2d DS |
1093 | QLA_SUCCESS) |
1094 | goto exit_get_event_log; | |
1095 | ||
1096 | event_log_size = mbox_sts[4]; | |
1097 | if (event_log_size == 0) | |
1098 | goto exit_get_event_log; | |
1099 | ||
1100 | /* Alloc Memory for Crash Record. */ | |
1101 | event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size, | |
1102 | &event_log_dma, GFP_KERNEL); | |
1103 | if (event_log == NULL) | |
1104 | goto exit_get_event_log; | |
1105 | ||
1106 | /* Get Crash Record. */ | |
c0e344c9 DS |
1107 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
1108 | memset(&mbox_sts, 0, sizeof(mbox_cmd)); | |
1109 | ||
afaf5a2d DS |
1110 | mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG; |
1111 | mbox_cmd[2] = LSDW(event_log_dma); | |
1112 | mbox_cmd[3] = MSDW(event_log_dma); | |
c0e344c9 DS |
1113 | |
1114 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) != | |
afaf5a2d DS |
1115 | QLA_SUCCESS) { |
1116 | DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event " | |
1117 | "log!\n", ha->host_no, __func__)); | |
1118 | goto exit_get_event_log; | |
1119 | } | |
1120 | ||
1121 | /* Dump Event Log. */ | |
1122 | num_valid_entries = mbox_sts[1]; | |
1123 | ||
1124 | max_event_log_entries = event_log_size / | |
1125 | sizeof(struct conn_event_log_entry); | |
1126 | ||
1127 | if (num_valid_entries > max_event_log_entries) | |
1128 | oldest_entry = num_valid_entries % max_event_log_entries; | |
1129 | ||
1130 | DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n", | |
1131 | ha->host_no, num_valid_entries)); | |
1132 | ||
11010fec | 1133 | if (ql4xextended_error_logging == 3) { |
afaf5a2d DS |
1134 | if (oldest_entry == 0) { |
1135 | /* Circular Buffer has not wrapped around */ | |
1136 | for (i=0; i < num_valid_entries; i++) { | |
1137 | qla4xxx_dump_buffer((uint8_t *)event_log+ | |
1138 | (i*sizeof(*event_log)), | |
1139 | sizeof(*event_log)); | |
1140 | } | |
1141 | } | |
1142 | else { | |
1143 | /* Circular Buffer has wrapped around - | |
1144 | * display accordingly*/ | |
1145 | for (i=oldest_entry; i < max_event_log_entries; i++) { | |
1146 | qla4xxx_dump_buffer((uint8_t *)event_log+ | |
1147 | (i*sizeof(*event_log)), | |
1148 | sizeof(*event_log)); | |
1149 | } | |
1150 | for (i=0; i < oldest_entry; i++) { | |
1151 | qla4xxx_dump_buffer((uint8_t *)event_log+ | |
1152 | (i*sizeof(*event_log)), | |
1153 | sizeof(*event_log)); | |
1154 | } | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | exit_get_event_log: | |
1159 | if (event_log) | |
1160 | dma_free_coherent(&ha->pdev->dev, event_log_size, event_log, | |
1161 | event_log_dma); | |
1162 | } | |
1163 | ||
09a0f719 VC |
1164 | /** |
1165 | * qla4xxx_abort_task - issues Abort Task | |
1166 | * @ha: Pointer to host adapter structure. | |
1167 | * @srb: Pointer to srb entry | |
1168 | * | |
1169 | * This routine performs a LUN RESET on the specified target/lun. | |
1170 | * The caller must ensure that the ddb_entry and lun_entry pointers | |
1171 | * are valid before calling this routine. | |
1172 | **/ | |
1173 | int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb) | |
1174 | { | |
1175 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1176 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1177 | struct scsi_cmnd *cmd = srb->cmd; | |
1178 | int status = QLA_SUCCESS; | |
1179 | unsigned long flags = 0; | |
1180 | uint32_t index; | |
1181 | ||
1182 | /* | |
1183 | * Send abort task command to ISP, so that the ISP will return | |
1184 | * request with ABORT status | |
1185 | */ | |
1186 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1187 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1188 | ||
1189 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1190 | index = (unsigned long)(unsigned char *)cmd->host_scribble; | |
1191 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1192 | ||
1193 | /* Firmware already posted completion on response queue */ | |
1194 | if (index == MAX_SRBS) | |
1195 | return status; | |
1196 | ||
1197 | mbox_cmd[0] = MBOX_CMD_ABORT_TASK; | |
6790d4fe | 1198 | mbox_cmd[1] = srb->ddb->fw_ddb_index; |
09a0f719 VC |
1199 | mbox_cmd[2] = index; |
1200 | /* Immediate Command Enable */ | |
1201 | mbox_cmd[5] = 0x01; | |
1202 | ||
1203 | qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], | |
1204 | &mbox_sts[0]); | |
1205 | if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) { | |
1206 | status = QLA_ERROR; | |
1207 | ||
9cb78c16 | 1208 | DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%llu: abort task FAILED: " |
09a0f719 VC |
1209 | "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n", |
1210 | ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0], | |
1211 | mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4])); | |
1212 | } | |
1213 | ||
1214 | return status; | |
1215 | } | |
1216 | ||
afaf5a2d DS |
1217 | /** |
1218 | * qla4xxx_reset_lun - issues LUN Reset | |
1219 | * @ha: Pointer to host adapter structure. | |
f4f5df23 VC |
1220 | * @ddb_entry: Pointer to device database entry |
1221 | * @lun: lun number | |
afaf5a2d DS |
1222 | * |
1223 | * This routine performs a LUN RESET on the specified target/lun. | |
1224 | * The caller must ensure that the ddb_entry and lun_entry pointers | |
1225 | * are valid before calling this routine. | |
1226 | **/ | |
1227 | int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry, | |
9cb78c16 | 1228 | uint64_t lun) |
afaf5a2d DS |
1229 | { |
1230 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1231 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
ae3ae252 | 1232 | uint32_t scsi_lun[2]; |
afaf5a2d DS |
1233 | int status = QLA_SUCCESS; |
1234 | ||
9cb78c16 | 1235 | DEBUG2(printk("scsi%ld:%d:%llu: lun reset issued\n", ha->host_no, |
f4f5df23 | 1236 | ddb_entry->fw_ddb_index, lun)); |
afaf5a2d DS |
1237 | |
1238 | /* | |
1239 | * Send lun reset command to ISP, so that the ISP will return all | |
1240 | * outstanding requests with RESET status | |
1241 | */ | |
1242 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1243 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
ae3ae252 | 1244 | int_to_scsilun(lun, (struct scsi_lun *) scsi_lun); |
c0e344c9 | 1245 | |
afaf5a2d DS |
1246 | mbox_cmd[0] = MBOX_CMD_LUN_RESET; |
1247 | mbox_cmd[1] = ddb_entry->fw_ddb_index; | |
ae3ae252 VC |
1248 | /* FW expects LUN bytes 0-3 in Incoming Mailbox 2 |
1249 | * (LUN byte 0 is LSByte, byte 3 is MSByte) */ | |
1250 | mbox_cmd[2] = cpu_to_le32(scsi_lun[0]); | |
1251 | /* FW expects LUN bytes 4-7 in Incoming Mailbox 3 | |
1252 | * (LUN byte 4 is LSByte, byte 7 is MSByte) */ | |
1253 | mbox_cmd[3] = cpu_to_le32(scsi_lun[1]); | |
afaf5a2d | 1254 | mbox_cmd[5] = 0x01; /* Immediate Command Enable */ |
c0e344c9 DS |
1255 | |
1256 | qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]); | |
afaf5a2d DS |
1257 | if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE && |
1258 | mbox_sts[0] != MBOX_STS_COMMAND_ERROR) | |
1259 | status = QLA_ERROR; | |
1260 | ||
1261 | return status; | |
1262 | } | |
1263 | ||
ce545039 MC |
1264 | /** |
1265 | * qla4xxx_reset_target - issues target Reset | |
1266 | * @ha: Pointer to host adapter structure. | |
1267 | * @db_entry: Pointer to device database entry | |
1268 | * @un_entry: Pointer to lun entry structure | |
1269 | * | |
1270 | * This routine performs a TARGET RESET on the specified target. | |
1271 | * The caller must ensure that the ddb_entry pointers | |
1272 | * are valid before calling this routine. | |
1273 | **/ | |
1274 | int qla4xxx_reset_target(struct scsi_qla_host *ha, | |
1275 | struct ddb_entry *ddb_entry) | |
1276 | { | |
1277 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1278 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1279 | int status = QLA_SUCCESS; | |
1280 | ||
1281 | DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no, | |
f4f5df23 | 1282 | ddb_entry->fw_ddb_index)); |
ce545039 MC |
1283 | |
1284 | /* | |
1285 | * Send target reset command to ISP, so that the ISP will return all | |
1286 | * outstanding requests with RESET status | |
1287 | */ | |
1288 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1289 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1290 | ||
1291 | mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET; | |
1292 | mbox_cmd[1] = ddb_entry->fw_ddb_index; | |
1293 | mbox_cmd[5] = 0x01; /* Immediate Command Enable */ | |
1294 | ||
1295 | qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], | |
1296 | &mbox_sts[0]); | |
1297 | if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE && | |
1298 | mbox_sts[0] != MBOX_STS_COMMAND_ERROR) | |
1299 | status = QLA_ERROR; | |
1300 | ||
1301 | return status; | |
1302 | } | |
afaf5a2d DS |
1303 | |
1304 | int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr, | |
1305 | uint32_t offset, uint32_t len) | |
1306 | { | |
1307 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1308 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1309 | ||
1310 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1311 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
c0e344c9 | 1312 | |
afaf5a2d DS |
1313 | mbox_cmd[0] = MBOX_CMD_READ_FLASH; |
1314 | mbox_cmd[1] = LSDW(dma_addr); | |
1315 | mbox_cmd[2] = MSDW(dma_addr); | |
1316 | mbox_cmd[3] = offset; | |
1317 | mbox_cmd[4] = len; | |
c0e344c9 DS |
1318 | |
1319 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) != | |
afaf5a2d DS |
1320 | QLA_SUCCESS) { |
1321 | DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ " | |
1322 | "status %04X %04X, offset %08x, len %08x\n", ha->host_no, | |
1323 | __func__, mbox_sts[0], mbox_sts[1], offset, len)); | |
1324 | return QLA_ERROR; | |
1325 | } | |
1326 | return QLA_SUCCESS; | |
1327 | } | |
1328 | ||
1329 | /** | |
7ad633c0 | 1330 | * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version |
afaf5a2d DS |
1331 | * @ha: Pointer to host adapter structure. |
1332 | * | |
7ad633c0 HZ |
1333 | * Retrieves the FW version, iSCSI draft version & bootloader version of HBA. |
1334 | * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to | |
1335 | * those mailboxes, if unused. | |
afaf5a2d | 1336 | **/ |
7ad633c0 | 1337 | int qla4xxx_about_firmware(struct scsi_qla_host *ha) |
afaf5a2d | 1338 | { |
7ad633c0 HZ |
1339 | struct about_fw_info *about_fw = NULL; |
1340 | dma_addr_t about_fw_dma; | |
afaf5a2d DS |
1341 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
1342 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
7ad633c0 HZ |
1343 | int status = QLA_ERROR; |
1344 | ||
1345 | about_fw = dma_alloc_coherent(&ha->pdev->dev, | |
1346 | sizeof(struct about_fw_info), | |
1347 | &about_fw_dma, GFP_KERNEL); | |
1348 | if (!about_fw) { | |
1349 | DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory " | |
1350 | "for about_fw\n", __func__)); | |
1351 | return status; | |
1352 | } | |
afaf5a2d | 1353 | |
7ad633c0 | 1354 | memset(about_fw, 0, sizeof(struct about_fw_info)); |
afaf5a2d DS |
1355 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
1356 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
c0e344c9 | 1357 | |
afaf5a2d | 1358 | mbox_cmd[0] = MBOX_CMD_ABOUT_FW; |
7ad633c0 HZ |
1359 | mbox_cmd[2] = LSDW(about_fw_dma); |
1360 | mbox_cmd[3] = MSDW(about_fw_dma); | |
1361 | mbox_cmd[4] = sizeof(struct about_fw_info); | |
1362 | ||
1363 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT, | |
1364 | &mbox_cmd[0], &mbox_sts[0]); | |
1365 | if (status != QLA_SUCCESS) { | |
1366 | DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW " | |
1367 | "failed w/ status %04X\n", __func__, | |
1368 | mbox_sts[0])); | |
1369 | goto exit_about_fw; | |
afaf5a2d DS |
1370 | } |
1371 | ||
7ad633c0 | 1372 | /* Save version information. */ |
eee06a0f AC |
1373 | ha->fw_info.fw_major = le16_to_cpu(about_fw->fw_major); |
1374 | ha->fw_info.fw_minor = le16_to_cpu(about_fw->fw_minor); | |
1375 | ha->fw_info.fw_patch = le16_to_cpu(about_fw->fw_patch); | |
1376 | ha->fw_info.fw_build = le16_to_cpu(about_fw->fw_build); | |
1377 | memcpy(ha->fw_info.fw_build_date, about_fw->fw_build_date, | |
1378 | sizeof(about_fw->fw_build_date)); | |
1379 | memcpy(ha->fw_info.fw_build_time, about_fw->fw_build_time, | |
1380 | sizeof(about_fw->fw_build_time)); | |
1381 | strcpy((char *)ha->fw_info.fw_build_user, | |
1382 | skip_spaces((char *)about_fw->fw_build_user)); | |
1383 | ha->fw_info.fw_load_source = le16_to_cpu(about_fw->fw_load_source); | |
1384 | ha->fw_info.iscsi_major = le16_to_cpu(about_fw->iscsi_major); | |
1385 | ha->fw_info.iscsi_minor = le16_to_cpu(about_fw->iscsi_minor); | |
1386 | ha->fw_info.bootload_major = le16_to_cpu(about_fw->bootload_major); | |
1387 | ha->fw_info.bootload_minor = le16_to_cpu(about_fw->bootload_minor); | |
1388 | ha->fw_info.bootload_patch = le16_to_cpu(about_fw->bootload_patch); | |
1389 | ha->fw_info.bootload_build = le16_to_cpu(about_fw->bootload_build); | |
1390 | strcpy((char *)ha->fw_info.extended_timestamp, | |
1391 | skip_spaces((char *)about_fw->extended_timestamp)); | |
1392 | ||
1393 | ha->fw_uptime_secs = le32_to_cpu(mbox_sts[5]); | |
1394 | ha->fw_uptime_msecs = le32_to_cpu(mbox_sts[6]); | |
7ad633c0 | 1395 | status = QLA_SUCCESS; |
afaf5a2d | 1396 | |
7ad633c0 HZ |
1397 | exit_about_fw: |
1398 | dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info), | |
1399 | about_fw, about_fw_dma); | |
1400 | return status; | |
afaf5a2d DS |
1401 | } |
1402 | ||
1e9e2be3 AC |
1403 | int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options, |
1404 | dma_addr_t dma_addr) | |
afaf5a2d DS |
1405 | { |
1406 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1407 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1408 | ||
1409 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1410 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1411 | ||
1412 | mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS; | |
b3a271a9 | 1413 | mbox_cmd[1] = options; |
afaf5a2d DS |
1414 | mbox_cmd[2] = LSDW(dma_addr); |
1415 | mbox_cmd[3] = MSDW(dma_addr); | |
1416 | ||
c0e344c9 | 1417 | if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) != |
afaf5a2d DS |
1418 | QLA_SUCCESS) { |
1419 | DEBUG2(printk("scsi%ld: %s: failed status %04X\n", | |
1420 | ha->host_no, __func__, mbox_sts[0])); | |
1421 | return QLA_ERROR; | |
1422 | } | |
1423 | return QLA_SUCCESS; | |
1424 | } | |
1425 | ||
b3a271a9 MR |
1426 | int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index, |
1427 | uint32_t *mbx_sts) | |
afaf5a2d | 1428 | { |
b3a271a9 | 1429 | int status; |
afaf5a2d DS |
1430 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
1431 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1432 | ||
1433 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1434 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1435 | ||
1436 | mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY; | |
b3a271a9 | 1437 | mbox_cmd[1] = ddb_index; |
afaf5a2d | 1438 | |
b3a271a9 MR |
1439 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], |
1440 | &mbox_sts[0]); | |
1441 | if (status != QLA_SUCCESS) { | |
1442 | DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", | |
1443 | __func__, mbox_sts[0])); | |
afaf5a2d DS |
1444 | } |
1445 | ||
b3a271a9 MR |
1446 | *mbx_sts = mbox_sts[0]; |
1447 | return status; | |
afaf5a2d DS |
1448 | } |
1449 | ||
b3a271a9 MR |
1450 | int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index) |
1451 | { | |
1452 | int status; | |
1453 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1454 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1455 | ||
1456 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1457 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1458 | ||
1459 | mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY; | |
1460 | mbox_cmd[1] = ddb_index; | |
1461 | ||
1462 | status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0], | |
1463 | &mbox_sts[0]); | |
1464 | if (status != QLA_SUCCESS) { | |
1465 | DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", | |
1466 | __func__, mbox_sts[0])); | |
1467 | } | |
1468 | ||
1469 | return status; | |
1470 | } | |
1471 | ||
d00efe3f MC |
1472 | int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr, |
1473 | uint32_t offset, uint32_t length, uint32_t options) | |
1474 | { | |
1475 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1476 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1477 | int status = QLA_SUCCESS; | |
1478 | ||
1479 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1480 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1481 | ||
1482 | mbox_cmd[0] = MBOX_CMD_WRITE_FLASH; | |
1483 | mbox_cmd[1] = LSDW(dma_addr); | |
1484 | mbox_cmd[2] = MSDW(dma_addr); | |
1485 | mbox_cmd[3] = offset; | |
1486 | mbox_cmd[4] = length; | |
1487 | mbox_cmd[5] = options; | |
1488 | ||
1489 | status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]); | |
1490 | if (status != QLA_SUCCESS) { | |
1491 | DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH " | |
1492 | "failed w/ status %04X, mbx1 %04X\n", | |
1493 | __func__, mbox_sts[0], mbox_sts[1])); | |
1494 | } | |
1495 | return status; | |
1496 | } | |
1497 | ||
2a991c21 MR |
1498 | int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha, |
1499 | struct dev_db_entry *fw_ddb_entry, | |
1500 | dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index) | |
1501 | { | |
1502 | uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO; | |
1503 | uint32_t dev_db_end_offset; | |
1504 | int status = QLA_ERROR; | |
1505 | ||
1506 | memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry)); | |
1507 | ||
1508 | dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry)); | |
1509 | dev_db_end_offset = FLASH_OFFSET_DB_END; | |
1510 | ||
1511 | if (dev_db_start_offset > dev_db_end_offset) { | |
1512 | DEBUG2(ql4_printk(KERN_ERR, ha, | |
1513 | "%s:Invalid DDB index %d", __func__, | |
1514 | ddb_index)); | |
1515 | goto exit_bootdb_failed; | |
1516 | } | |
1517 | ||
1518 | if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset, | |
1519 | sizeof(*fw_ddb_entry)) != QLA_SUCCESS) { | |
1520 | ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash" | |
1521 | "failed\n", ha->host_no, __func__); | |
1522 | goto exit_bootdb_failed; | |
1523 | } | |
1524 | ||
1525 | if (fw_ddb_entry->cookie == DDB_VALID_COOKIE) | |
1526 | status = QLA_SUCCESS; | |
1527 | ||
1528 | exit_bootdb_failed: | |
1529 | return status; | |
1530 | } | |
1531 | ||
1e9e2be3 AC |
1532 | int qla4xxx_flashdb_by_index(struct scsi_qla_host *ha, |
1533 | struct dev_db_entry *fw_ddb_entry, | |
1534 | dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index) | |
1535 | { | |
039acc1e | 1536 | uint32_t dev_db_start_offset; |
1e9e2be3 AC |
1537 | uint32_t dev_db_end_offset; |
1538 | int status = QLA_ERROR; | |
1539 | ||
1540 | memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry)); | |
1541 | ||
1542 | if (is_qla40XX(ha)) { | |
1543 | dev_db_start_offset = FLASH_OFFSET_DB_INFO; | |
039acc1e | 1544 | dev_db_end_offset = FLASH_OFFSET_DB_END; |
1e9e2be3 AC |
1545 | } else { |
1546 | dev_db_start_offset = FLASH_RAW_ACCESS_ADDR + | |
1547 | (ha->hw.flt_region_ddb << 2); | |
1548 | /* flt_ddb_size is DDB table size for both ports | |
1549 | * so divide it by 2 to calculate the offset for second port | |
1550 | */ | |
1551 | if (ha->port_num == 1) | |
1552 | dev_db_start_offset += (ha->hw.flt_ddb_size / 2); | |
039acc1e AC |
1553 | |
1554 | dev_db_end_offset = dev_db_start_offset + | |
1555 | (ha->hw.flt_ddb_size / 2); | |
1e9e2be3 AC |
1556 | } |
1557 | ||
1e9e2be3 AC |
1558 | dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry)); |
1559 | ||
1560 | if (dev_db_start_offset > dev_db_end_offset) { | |
1561 | DEBUG2(ql4_printk(KERN_ERR, ha, | |
1562 | "%s:Invalid DDB index %d", __func__, | |
1563 | ddb_index)); | |
1564 | goto exit_fdb_failed; | |
1565 | } | |
1566 | ||
1567 | if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset, | |
1568 | sizeof(*fw_ddb_entry)) != QLA_SUCCESS) { | |
1569 | ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash failed\n", | |
1570 | ha->host_no, __func__); | |
1571 | goto exit_fdb_failed; | |
1572 | } | |
1573 | ||
1574 | if (fw_ddb_entry->cookie == DDB_VALID_COOKIE) | |
1575 | status = QLA_SUCCESS; | |
1576 | ||
1577 | exit_fdb_failed: | |
1578 | return status; | |
1579 | } | |
1580 | ||
2a991c21 MR |
1581 | int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password, |
1582 | uint16_t idx) | |
1583 | { | |
1584 | int ret = 0; | |
1585 | int rval = QLA_ERROR; | |
4549415a | 1586 | uint32_t offset = 0, chap_size; |
2a991c21 MR |
1587 | struct ql4_chap_table *chap_table; |
1588 | dma_addr_t chap_dma; | |
1589 | ||
1590 | chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma); | |
50e92915 DC |
1591 | if (chap_table == NULL) |
1592 | return -ENOMEM; | |
2a991c21 | 1593 | |
4549415a LC |
1594 | chap_size = sizeof(struct ql4_chap_table); |
1595 | memset(chap_table, 0, chap_size); | |
1596 | ||
1597 | if (is_qla40XX(ha)) | |
1598 | offset = FLASH_CHAP_OFFSET | (idx * chap_size); | |
1599 | else { | |
1600 | offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2); | |
1601 | /* flt_chap_size is CHAP table size for both ports | |
1602 | * so divide it by 2 to calculate the offset for second port | |
1603 | */ | |
1604 | if (ha->port_num == 1) | |
1605 | offset += (ha->hw.flt_chap_size / 2); | |
1606 | offset += (idx * chap_size); | |
1607 | } | |
2a991c21 | 1608 | |
4549415a | 1609 | rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size); |
2a991c21 MR |
1610 | if (rval != QLA_SUCCESS) { |
1611 | ret = -EINVAL; | |
1612 | goto exit_get_chap; | |
1613 | } | |
1614 | ||
1615 | DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n", | |
1616 | __le16_to_cpu(chap_table->cookie))); | |
1617 | ||
1618 | if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) { | |
1619 | ql4_printk(KERN_ERR, ha, "No valid chap entry found\n"); | |
1620 | goto exit_get_chap; | |
1621 | } | |
1622 | ||
4d0a21f1 RS |
1623 | strlcpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN); |
1624 | strlcpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN); | |
2a991c21 MR |
1625 | chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE); |
1626 | ||
1627 | exit_get_chap: | |
1628 | dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma); | |
1629 | return ret; | |
1630 | } | |
1631 | ||
26ffd7b4 AC |
1632 | /** |
1633 | * qla4xxx_set_chap - Make a chap entry at the given index | |
1634 | * @ha: pointer to adapter structure | |
1635 | * @username: CHAP username to set | |
1636 | * @password: CHAP password to set | |
1637 | * @idx: CHAP index at which to make the entry | |
1638 | * @bidi: type of chap entry (chap_in or chap_out) | |
1639 | * | |
1640 | * Create chap entry at the given index with the information provided. | |
1641 | * | |
1642 | * Note: Caller should acquire the chap lock before getting here. | |
1643 | **/ | |
1644 | int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username, char *password, | |
1645 | uint16_t idx, int bidi) | |
b3a271a9 MR |
1646 | { |
1647 | int ret = 0; | |
1648 | int rval = QLA_ERROR; | |
1649 | uint32_t offset = 0; | |
1650 | struct ql4_chap_table *chap_table; | |
b1d0b63f | 1651 | uint32_t chap_size = 0; |
b3a271a9 MR |
1652 | dma_addr_t chap_dma; |
1653 | ||
1654 | chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma); | |
1655 | if (chap_table == NULL) { | |
1656 | ret = -ENOMEM; | |
1657 | goto exit_set_chap; | |
1658 | } | |
1659 | ||
1660 | memset(chap_table, 0, sizeof(struct ql4_chap_table)); | |
1661 | if (bidi) | |
1662 | chap_table->flags |= BIT_6; /* peer */ | |
1663 | else | |
1664 | chap_table->flags |= BIT_7; /* local */ | |
1665 | chap_table->secret_len = strlen(password); | |
4d0a21f1 RS |
1666 | strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN - 1); |
1667 | strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN - 1); | |
b3a271a9 | 1668 | chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE); |
b1d0b63f AC |
1669 | |
1670 | if (is_qla40XX(ha)) { | |
1671 | chap_size = MAX_CHAP_ENTRIES_40XX * sizeof(*chap_table); | |
1672 | offset = FLASH_CHAP_OFFSET; | |
1673 | } else { /* Single region contains CHAP info for both ports which is | |
1674 | * divided into half for each port. | |
1675 | */ | |
1676 | chap_size = ha->hw.flt_chap_size / 2; | |
1677 | offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2); | |
1678 | if (ha->port_num == 1) | |
1679 | offset += chap_size; | |
1680 | } | |
1681 | ||
1682 | offset += (idx * sizeof(struct ql4_chap_table)); | |
b3a271a9 MR |
1683 | rval = qla4xxx_set_flash(ha, chap_dma, offset, |
1684 | sizeof(struct ql4_chap_table), | |
1685 | FLASH_OPT_RMW_COMMIT); | |
4549415a LC |
1686 | |
1687 | if (rval == QLA_SUCCESS && ha->chap_list) { | |
1688 | /* Update ha chap_list cache */ | |
1689 | memcpy((struct ql4_chap_table *)ha->chap_list + idx, | |
1690 | chap_table, sizeof(struct ql4_chap_table)); | |
1691 | } | |
b3a271a9 MR |
1692 | dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma); |
1693 | if (rval != QLA_SUCCESS) | |
1694 | ret = -EINVAL; | |
1695 | ||
1696 | exit_set_chap: | |
1697 | return ret; | |
1698 | } | |
1699 | ||
1e9e2be3 AC |
1700 | |
1701 | int qla4xxx_get_uni_chap_at_index(struct scsi_qla_host *ha, char *username, | |
1702 | char *password, uint16_t chap_index) | |
1703 | { | |
1704 | int rval = QLA_ERROR; | |
1705 | struct ql4_chap_table *chap_table = NULL; | |
1706 | int max_chap_entries; | |
1707 | ||
1708 | if (!ha->chap_list) { | |
1709 | ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n"); | |
1710 | rval = QLA_ERROR; | |
1711 | goto exit_uni_chap; | |
1712 | } | |
1713 | ||
1714 | if (!username || !password) { | |
1715 | ql4_printk(KERN_ERR, ha, "No memory for username & secret\n"); | |
1716 | rval = QLA_ERROR; | |
1717 | goto exit_uni_chap; | |
1718 | } | |
1719 | ||
1720 | if (is_qla80XX(ha)) | |
1721 | max_chap_entries = (ha->hw.flt_chap_size / 2) / | |
1722 | sizeof(struct ql4_chap_table); | |
1723 | else | |
1724 | max_chap_entries = MAX_CHAP_ENTRIES_40XX; | |
1725 | ||
1726 | if (chap_index > max_chap_entries) { | |
1727 | ql4_printk(KERN_ERR, ha, "Invalid Chap index\n"); | |
1728 | rval = QLA_ERROR; | |
1729 | goto exit_uni_chap; | |
1730 | } | |
1731 | ||
1732 | mutex_lock(&ha->chap_sem); | |
1733 | chap_table = (struct ql4_chap_table *)ha->chap_list + chap_index; | |
1734 | if (chap_table->cookie != __constant_cpu_to_le16(CHAP_VALID_COOKIE)) { | |
1735 | rval = QLA_ERROR; | |
1736 | goto exit_unlock_uni_chap; | |
1737 | } | |
1738 | ||
33519aec | 1739 | if (!(chap_table->flags & BIT_7)) { |
1e9e2be3 AC |
1740 | ql4_printk(KERN_ERR, ha, "Unidirectional entry not set\n"); |
1741 | rval = QLA_ERROR; | |
1742 | goto exit_unlock_uni_chap; | |
1743 | } | |
1744 | ||
4d0a21f1 RS |
1745 | strlcpy(password, chap_table->secret, MAX_CHAP_SECRET_LEN); |
1746 | strlcpy(username, chap_table->name, MAX_CHAP_NAME_LEN); | |
1e9e2be3 AC |
1747 | |
1748 | rval = QLA_SUCCESS; | |
1749 | ||
1750 | exit_unlock_uni_chap: | |
1751 | mutex_unlock(&ha->chap_sem); | |
1752 | exit_uni_chap: | |
1753 | return rval; | |
1754 | } | |
1755 | ||
4549415a LC |
1756 | /** |
1757 | * qla4xxx_get_chap_index - Get chap index given username and secret | |
1758 | * @ha: pointer to adapter structure | |
1759 | * @username: CHAP username to be searched | |
1760 | * @password: CHAP password to be searched | |
1761 | * @bidi: Is this a BIDI CHAP | |
1762 | * @chap_index: CHAP index to be returned | |
1763 | * | |
1764 | * Match the username and password in the chap_list, return the index if a | |
1765 | * match is found. If a match is not found then add the entry in FLASH and | |
1766 | * return the index at which entry is written in the FLASH. | |
1767 | **/ | |
fca9f04d MC |
1768 | int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username, |
1769 | char *password, int bidi, uint16_t *chap_index) | |
4549415a LC |
1770 | { |
1771 | int i, rval; | |
1772 | int free_index = -1; | |
1773 | int found_index = 0; | |
1774 | int max_chap_entries = 0; | |
1775 | struct ql4_chap_table *chap_table; | |
1776 | ||
d11b0ca3 | 1777 | if (is_qla80XX(ha)) |
4549415a LC |
1778 | max_chap_entries = (ha->hw.flt_chap_size / 2) / |
1779 | sizeof(struct ql4_chap_table); | |
1780 | else | |
1781 | max_chap_entries = MAX_CHAP_ENTRIES_40XX; | |
1782 | ||
1783 | if (!ha->chap_list) { | |
1784 | ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n"); | |
1785 | return QLA_ERROR; | |
1786 | } | |
1787 | ||
fca9f04d MC |
1788 | if (!username || !password) { |
1789 | ql4_printk(KERN_ERR, ha, "Do not have username and psw\n"); | |
1790 | return QLA_ERROR; | |
1791 | } | |
1792 | ||
4549415a LC |
1793 | mutex_lock(&ha->chap_sem); |
1794 | for (i = 0; i < max_chap_entries; i++) { | |
1795 | chap_table = (struct ql4_chap_table *)ha->chap_list + i; | |
1796 | if (chap_table->cookie != | |
1797 | __constant_cpu_to_le16(CHAP_VALID_COOKIE)) { | |
1798 | if (i > MAX_RESRV_CHAP_IDX && free_index == -1) | |
1799 | free_index = i; | |
1800 | continue; | |
1801 | } | |
1802 | if (bidi) { | |
1803 | if (chap_table->flags & BIT_7) | |
1804 | continue; | |
1805 | } else { | |
1806 | if (chap_table->flags & BIT_6) | |
1807 | continue; | |
1808 | } | |
1809 | if (!strncmp(chap_table->secret, password, | |
1810 | MAX_CHAP_SECRET_LEN) && | |
1811 | !strncmp(chap_table->name, username, | |
1812 | MAX_CHAP_NAME_LEN)) { | |
1813 | *chap_index = i; | |
1814 | found_index = 1; | |
1815 | break; | |
1816 | } | |
1817 | } | |
1818 | ||
1819 | /* If chap entry is not present and a free index is available then | |
1820 | * write the entry in flash | |
1821 | */ | |
1822 | if (!found_index && free_index != -1) { | |
1823 | rval = qla4xxx_set_chap(ha, username, password, | |
1824 | free_index, bidi); | |
1825 | if (!rval) { | |
1826 | *chap_index = free_index; | |
1827 | found_index = 1; | |
1828 | } | |
1829 | } | |
1830 | ||
1831 | mutex_unlock(&ha->chap_sem); | |
1832 | ||
1833 | if (found_index) | |
1834 | return QLA_SUCCESS; | |
1835 | return QLA_ERROR; | |
1836 | } | |
1837 | ||
d00efe3f MC |
1838 | int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha, |
1839 | uint16_t fw_ddb_index, | |
1840 | uint16_t connection_id, | |
1841 | uint16_t option) | |
1842 | { | |
1843 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1844 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1845 | int status = QLA_SUCCESS; | |
1846 | ||
1847 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1848 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1849 | ||
1850 | mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT; | |
1851 | mbox_cmd[1] = fw_ddb_index; | |
1852 | mbox_cmd[2] = connection_id; | |
1853 | mbox_cmd[3] = option; | |
1854 | ||
1855 | status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]); | |
1856 | if (status != QLA_SUCCESS) { | |
1857 | DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE " | |
1858 | "option %04x failed w/ status %04X %04X\n", | |
1859 | __func__, option, mbox_sts[0], mbox_sts[1])); | |
1860 | } | |
1861 | return status; | |
1862 | } | |
1863 | ||
7ab284c9 NJ |
1864 | /** |
1865 | * qla4_84xx_extend_idc_tmo - Extend IDC Timeout. | |
1866 | * @ha: Pointer to host adapter structure. | |
1867 | * @ext_tmo: idc timeout value | |
1868 | * | |
1869 | * Requests firmware to extend the idc timeout value. | |
1870 | **/ | |
1871 | static int qla4_84xx_extend_idc_tmo(struct scsi_qla_host *ha, uint32_t ext_tmo) | |
1872 | { | |
1873 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1874 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1875 | int status; | |
1876 | ||
1877 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1878 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1879 | ext_tmo &= 0xf; | |
1880 | ||
1881 | mbox_cmd[0] = MBOX_CMD_IDC_TIME_EXTEND; | |
1882 | mbox_cmd[1] = ((ha->idc_info.request_desc & 0xfffff0ff) | | |
1883 | (ext_tmo << 8)); /* new timeout */ | |
1884 | mbox_cmd[2] = ha->idc_info.info1; | |
1885 | mbox_cmd[3] = ha->idc_info.info2; | |
1886 | mbox_cmd[4] = ha->idc_info.info3; | |
1887 | ||
1888 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT, | |
1889 | mbox_cmd, mbox_sts); | |
1890 | if (status != QLA_SUCCESS) { | |
1891 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
1892 | "scsi%ld: %s: failed status %04X\n", | |
1893 | ha->host_no, __func__, mbox_sts[0])); | |
1894 | return QLA_ERROR; | |
1895 | } else { | |
1896 | ql4_printk(KERN_INFO, ha, "%s: IDC timeout extended by %d secs\n", | |
1897 | __func__, ext_tmo); | |
1898 | } | |
1899 | ||
1900 | return QLA_SUCCESS; | |
1901 | } | |
1902 | ||
d00efe3f MC |
1903 | int qla4xxx_disable_acb(struct scsi_qla_host *ha) |
1904 | { | |
1905 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
1906 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
1907 | int status = QLA_SUCCESS; | |
1908 | ||
1909 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
1910 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1911 | ||
1912 | mbox_cmd[0] = MBOX_CMD_DISABLE_ACB; | |
1913 | ||
1914 | status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]); | |
1915 | if (status != QLA_SUCCESS) { | |
1916 | DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB " | |
1917 | "failed w/ status %04X %04X %04X", __func__, | |
1918 | mbox_sts[0], mbox_sts[1], mbox_sts[2])); | |
7ab284c9 NJ |
1919 | } else { |
1920 | if (is_qla8042(ha) && | |
831805a1 | 1921 | test_bit(DPC_POST_IDC_ACK, &ha->dpc_flags) && |
7ab284c9 NJ |
1922 | (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE)) { |
1923 | /* | |
1924 | * Disable ACB mailbox command takes time to complete | |
1925 | * based on the total number of targets connected. | |
1926 | * For 512 targets, it took approximately 5 secs to | |
1927 | * complete. Setting the timeout value to 8, with the 3 | |
1928 | * secs buffer. | |
1929 | */ | |
1930 | qla4_84xx_extend_idc_tmo(ha, IDC_EXTEND_TOV); | |
1931 | if (!wait_for_completion_timeout(&ha->disable_acb_comp, | |
1932 | IDC_EXTEND_TOV * HZ)) { | |
1933 | ql4_printk(KERN_WARNING, ha, "%s: Disable ACB Completion not received\n", | |
1934 | __func__); | |
1935 | } | |
1936 | } | |
d00efe3f MC |
1937 | } |
1938 | return status; | |
1939 | } | |
1940 | ||
6085491c HZ |
1941 | int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma, |
1942 | uint32_t acb_type, uint32_t len) | |
d00efe3f | 1943 | { |
6085491c HZ |
1944 | uint32_t mbox_cmd[MBOX_REG_COUNT]; |
1945 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
d00efe3f MC |
1946 | int status = QLA_SUCCESS; |
1947 | ||
6085491c HZ |
1948 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); |
1949 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
1950 | ||
d00efe3f | 1951 | mbox_cmd[0] = MBOX_CMD_GET_ACB; |
6085491c | 1952 | mbox_cmd[1] = acb_type; |
d00efe3f MC |
1953 | mbox_cmd[2] = LSDW(acb_dma); |
1954 | mbox_cmd[3] = MSDW(acb_dma); | |
6085491c | 1955 | mbox_cmd[4] = len; |
d00efe3f MC |
1956 | |
1957 | status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]); | |
1958 | if (status != QLA_SUCCESS) { | |
1959 | DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB " | |
1960 | "failed w/ status %04X\n", __func__, | |
1961 | mbox_sts[0])); | |
1962 | } | |
1963 | return status; | |
1964 | } | |
1965 | ||
1966 | int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd, | |
1967 | uint32_t *mbox_sts, dma_addr_t acb_dma) | |
1968 | { | |
1969 | int status = QLA_SUCCESS; | |
1970 | ||
1971 | memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT); | |
1972 | memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT); | |
1973 | mbox_cmd[0] = MBOX_CMD_SET_ACB; | |
1974 | mbox_cmd[1] = 0; /* Primary ACB */ | |
1975 | mbox_cmd[2] = LSDW(acb_dma); | |
1976 | mbox_cmd[3] = MSDW(acb_dma); | |
1977 | mbox_cmd[4] = sizeof(struct addr_ctrl_blk); | |
1978 | ||
1979 | status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]); | |
1980 | if (status != QLA_SUCCESS) { | |
1981 | DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB " | |
1982 | "failed w/ status %04X\n", __func__, | |
1983 | mbox_sts[0])); | |
1984 | } | |
1985 | return status; | |
1986 | } | |
b3a271a9 MR |
1987 | |
1988 | int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha, | |
1989 | struct ddb_entry *ddb_entry, | |
1990 | struct iscsi_cls_conn *cls_conn, | |
1991 | uint32_t *mbx_sts) | |
1992 | { | |
1993 | struct dev_db_entry *fw_ddb_entry; | |
1994 | struct iscsi_conn *conn; | |
1995 | struct iscsi_session *sess; | |
1996 | struct qla_conn *qla_conn; | |
1997 | struct sockaddr *dst_addr; | |
1998 | dma_addr_t fw_ddb_entry_dma; | |
1999 | int status = QLA_SUCCESS; | |
2000 | int rval = 0; | |
2001 | struct sockaddr_in *addr; | |
2002 | struct sockaddr_in6 *addr6; | |
2003 | char *ip; | |
2004 | uint16_t iscsi_opts = 0; | |
2005 | uint32_t options = 0; | |
173269ef | 2006 | uint16_t idx, *ptid; |
b3a271a9 MR |
2007 | |
2008 | fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry), | |
2009 | &fw_ddb_entry_dma, GFP_KERNEL); | |
2010 | if (!fw_ddb_entry) { | |
2011 | DEBUG2(ql4_printk(KERN_ERR, ha, | |
2012 | "%s: Unable to allocate dma buffer.\n", | |
2013 | __func__)); | |
2014 | rval = -ENOMEM; | |
2015 | goto exit_set_param_no_free; | |
2016 | } | |
2017 | ||
2018 | conn = cls_conn->dd_data; | |
2019 | qla_conn = conn->dd_data; | |
2020 | sess = conn->session; | |
d46bdeb1 | 2021 | dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr; |
b3a271a9 MR |
2022 | |
2023 | if (dst_addr->sa_family == AF_INET6) | |
2024 | options |= IPV6_DEFAULT_DDB_ENTRY; | |
2025 | ||
2026 | status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma); | |
2027 | if (status == QLA_ERROR) { | |
2028 | rval = -EINVAL; | |
2029 | goto exit_set_param; | |
2030 | } | |
2031 | ||
173269ef MR |
2032 | ptid = (uint16_t *)&fw_ddb_entry->isid[1]; |
2033 | *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id); | |
2034 | ||
2035 | DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n", | |
2036 | fw_ddb_entry->isid[5], fw_ddb_entry->isid[4], | |
2037 | fw_ddb_entry->isid[3], fw_ddb_entry->isid[2], | |
2038 | fw_ddb_entry->isid[1], fw_ddb_entry->isid[0])); | |
2039 | ||
b3a271a9 MR |
2040 | iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options); |
2041 | memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias)); | |
2042 | ||
2043 | memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name)); | |
2044 | ||
2045 | if (sess->targetname != NULL) { | |
2046 | memcpy(fw_ddb_entry->iscsi_name, sess->targetname, | |
2047 | min(strlen(sess->targetname), | |
2048 | sizeof(fw_ddb_entry->iscsi_name))); | |
2049 | } | |
2050 | ||
2051 | memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr)); | |
2052 | memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr)); | |
2053 | ||
2054 | fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE; | |
2055 | ||
2056 | if (dst_addr->sa_family == AF_INET) { | |
2057 | addr = (struct sockaddr_in *)dst_addr; | |
2058 | ip = (char *)&addr->sin_addr; | |
2059 | memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN); | |
2060 | fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port)); | |
2061 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2062 | "%s: Destination Address [%pI4]: index [%d]\n", | |
2063 | __func__, fw_ddb_entry->ip_addr, | |
2064 | ddb_entry->fw_ddb_index)); | |
2065 | } else if (dst_addr->sa_family == AF_INET6) { | |
2066 | addr6 = (struct sockaddr_in6 *)dst_addr; | |
2067 | ip = (char *)&addr6->sin6_addr; | |
2068 | memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN); | |
2069 | fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port)); | |
2070 | fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE; | |
2071 | DEBUG2(ql4_printk(KERN_INFO, ha, | |
2072 | "%s: Destination Address [%pI6]: index [%d]\n", | |
2073 | __func__, fw_ddb_entry->ip_addr, | |
2074 | ddb_entry->fw_ddb_index)); | |
2075 | } else { | |
2076 | ql4_printk(KERN_ERR, ha, | |
2077 | "%s: Failed to get IP Address\n", | |
2078 | __func__); | |
2079 | rval = -EINVAL; | |
2080 | goto exit_set_param; | |
2081 | } | |
2082 | ||
b3a271a9 MR |
2083 | /* CHAP */ |
2084 | if (sess->username != NULL && sess->password != NULL) { | |
2085 | if (strlen(sess->username) && strlen(sess->password)) { | |
2086 | iscsi_opts |= BIT_7; | |
b3a271a9 | 2087 | |
4549415a LC |
2088 | rval = qla4xxx_get_chap_index(ha, sess->username, |
2089 | sess->password, | |
2090 | LOCAL_CHAP, &idx); | |
b3a271a9 MR |
2091 | if (rval) |
2092 | goto exit_set_param; | |
2093 | ||
2094 | fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx); | |
2095 | } | |
2096 | } | |
2097 | ||
2098 | if (sess->username_in != NULL && sess->password_in != NULL) { | |
2099 | /* Check if BIDI CHAP */ | |
2100 | if (strlen(sess->username_in) && strlen(sess->password_in)) { | |
2101 | iscsi_opts |= BIT_4; | |
4549415a LC |
2102 | |
2103 | rval = qla4xxx_get_chap_index(ha, sess->username_in, | |
2104 | sess->password_in, | |
2105 | BIDI_CHAP, &idx); | |
b3a271a9 MR |
2106 | if (rval) |
2107 | goto exit_set_param; | |
2108 | } | |
2109 | } | |
2110 | ||
2111 | if (sess->initial_r2t_en) | |
2112 | iscsi_opts |= BIT_10; | |
2113 | ||
2114 | if (sess->imm_data_en) | |
2115 | iscsi_opts |= BIT_11; | |
2116 | ||
2117 | fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts); | |
2118 | ||
2119 | if (conn->max_recv_dlength) | |
2120 | fw_ddb_entry->iscsi_max_rcv_data_seg_len = | |
2121 | __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS)); | |
2122 | ||
2123 | if (sess->max_r2t) | |
2124 | fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t); | |
2125 | ||
2126 | if (sess->first_burst) | |
2127 | fw_ddb_entry->iscsi_first_burst_len = | |
2128 | __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS)); | |
2129 | ||
2130 | if (sess->max_burst) | |
2131 | fw_ddb_entry->iscsi_max_burst_len = | |
2132 | __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS)); | |
2133 | ||
2134 | if (sess->time2wait) | |
2135 | fw_ddb_entry->iscsi_def_time2wait = | |
2136 | cpu_to_le16(sess->time2wait); | |
2137 | ||
2138 | if (sess->time2retain) | |
2139 | fw_ddb_entry->iscsi_def_time2retain = | |
2140 | cpu_to_le16(sess->time2retain); | |
2141 | ||
2142 | status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index, | |
2143 | fw_ddb_entry_dma, mbx_sts); | |
2144 | ||
2145 | if (status != QLA_SUCCESS) | |
2146 | rval = -EINVAL; | |
2147 | exit_set_param: | |
2148 | dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry), | |
2149 | fw_ddb_entry, fw_ddb_entry_dma); | |
2150 | exit_set_param_no_free: | |
2151 | return rval; | |
2152 | } | |
2153 | ||
2154 | int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index, | |
2155 | uint16_t stats_size, dma_addr_t stats_dma) | |
2156 | { | |
2157 | int status = QLA_SUCCESS; | |
2158 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2159 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2160 | ||
2161 | memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT); | |
2162 | memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT); | |
2163 | mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA; | |
2164 | mbox_cmd[1] = fw_ddb_index; | |
2165 | mbox_cmd[2] = LSDW(stats_dma); | |
2166 | mbox_cmd[3] = MSDW(stats_dma); | |
2167 | mbox_cmd[4] = stats_size; | |
2168 | ||
2169 | status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]); | |
2170 | if (status != QLA_SUCCESS) { | |
2171 | DEBUG2(ql4_printk(KERN_WARNING, ha, | |
2172 | "%s: MBOX_CMD_GET_MANAGEMENT_DATA " | |
2173 | "failed w/ status %04X\n", __func__, | |
2174 | mbox_sts[0])); | |
2175 | } | |
2176 | return status; | |
2177 | } | |
8b0402e1 HZ |
2178 | |
2179 | int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx, | |
2180 | uint32_t ip_idx, uint32_t *sts) | |
2181 | { | |
2182 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2183 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2184 | int status = QLA_SUCCESS; | |
2185 | ||
2186 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
2187 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
2188 | mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE; | |
2189 | mbox_cmd[1] = acb_idx; | |
2190 | mbox_cmd[2] = ip_idx; | |
2191 | ||
2192 | status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]); | |
2193 | if (status != QLA_SUCCESS) { | |
2194 | DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: " | |
2195 | "MBOX_CMD_GET_IP_ADDR_STATE failed w/ " | |
2196 | "status %04X\n", __func__, mbox_sts[0])); | |
2197 | } | |
2198 | memcpy(sts, mbox_sts, sizeof(mbox_sts)); | |
2199 | return status; | |
2200 | } | |
7c07d139 HZ |
2201 | |
2202 | int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma, | |
2203 | uint32_t offset, uint32_t size) | |
2204 | { | |
2205 | int status = QLA_SUCCESS; | |
2206 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2207 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2208 | ||
2209 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
2210 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
2211 | ||
2212 | mbox_cmd[0] = MBOX_CMD_GET_NVRAM; | |
2213 | mbox_cmd[1] = LSDW(nvram_dma); | |
2214 | mbox_cmd[2] = MSDW(nvram_dma); | |
2215 | mbox_cmd[3] = offset; | |
2216 | mbox_cmd[4] = size; | |
2217 | ||
2218 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], | |
2219 | &mbox_sts[0]); | |
2220 | if (status != QLA_SUCCESS) { | |
2221 | DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed " | |
2222 | "status %04X\n", ha->host_no, __func__, | |
2223 | mbox_sts[0])); | |
2224 | } | |
2225 | return status; | |
2226 | } | |
2227 | ||
2228 | int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma, | |
2229 | uint32_t offset, uint32_t size) | |
2230 | { | |
2231 | int status = QLA_SUCCESS; | |
2232 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2233 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2234 | ||
2235 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
2236 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
2237 | ||
2238 | mbox_cmd[0] = MBOX_CMD_SET_NVRAM; | |
2239 | mbox_cmd[1] = LSDW(nvram_dma); | |
2240 | mbox_cmd[2] = MSDW(nvram_dma); | |
2241 | mbox_cmd[3] = offset; | |
2242 | mbox_cmd[4] = size; | |
2243 | ||
2244 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], | |
2245 | &mbox_sts[0]); | |
2246 | if (status != QLA_SUCCESS) { | |
2247 | DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed " | |
2248 | "status %04X\n", ha->host_no, __func__, | |
2249 | mbox_sts[0])); | |
2250 | } | |
2251 | return status; | |
2252 | } | |
5232f801 HZ |
2253 | |
2254 | int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha, | |
2255 | uint32_t region, uint32_t field0, | |
2256 | uint32_t field1) | |
2257 | { | |
2258 | int status = QLA_SUCCESS; | |
2259 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2260 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2261 | ||
2262 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
2263 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
2264 | ||
2265 | mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS; | |
2266 | mbox_cmd[3] = region; | |
2267 | mbox_cmd[4] = field0; | |
2268 | mbox_cmd[5] = field1; | |
2269 | ||
2270 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], | |
2271 | &mbox_sts[0]); | |
2272 | if (status != QLA_SUCCESS) { | |
2273 | DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed " | |
2274 | "status %04X\n", ha->host_no, __func__, | |
2275 | mbox_sts[0])); | |
2276 | } | |
2277 | return status; | |
2278 | } | |
cfb27874 MD |
2279 | |
2280 | /** | |
2281 | * qla4_8xxx_set_param - set driver version in firmware. | |
2282 | * @ha: Pointer to host adapter structure. | |
2283 | * @param: Parameter to set i.e driver version | |
2284 | **/ | |
2285 | int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param) | |
2286 | { | |
2287 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2288 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2289 | uint32_t status; | |
2290 | ||
2291 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
2292 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
2293 | ||
2294 | mbox_cmd[0] = MBOX_CMD_SET_PARAM; | |
2295 | if (param == SET_DRVR_VERSION) { | |
2296 | mbox_cmd[1] = SET_DRVR_VERSION; | |
2297 | strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION, | |
4d0a21f1 | 2298 | MAX_DRVR_VER_LEN - 1); |
cfb27874 MD |
2299 | } else { |
2300 | ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n", | |
2301 | __func__, param); | |
2302 | status = QLA_ERROR; | |
2303 | goto exit_set_param; | |
2304 | } | |
2305 | ||
2306 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd, | |
2307 | mbox_sts); | |
2308 | if (status == QLA_ERROR) | |
2309 | ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", | |
2310 | __func__, mbox_sts[0]); | |
2311 | ||
2312 | exit_set_param: | |
2313 | return status; | |
2314 | } | |
320a61de NJ |
2315 | |
2316 | /** | |
2317 | * qla4_83xx_post_idc_ack - post IDC ACK | |
2318 | * @ha: Pointer to host adapter structure. | |
2319 | * | |
2320 | * Posts IDC ACK for IDC Request Notification AEN. | |
2321 | **/ | |
2322 | int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha) | |
2323 | { | |
2324 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2325 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2326 | int status; | |
2327 | ||
2328 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
2329 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
2330 | ||
2331 | mbox_cmd[0] = MBOX_CMD_IDC_ACK; | |
2332 | mbox_cmd[1] = ha->idc_info.request_desc; | |
2333 | mbox_cmd[2] = ha->idc_info.info1; | |
2334 | mbox_cmd[3] = ha->idc_info.info2; | |
2335 | mbox_cmd[4] = ha->idc_info.info3; | |
2336 | ||
2337 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT, | |
2338 | mbox_cmd, mbox_sts); | |
2339 | if (status == QLA_ERROR) | |
2340 | ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__, | |
2341 | mbox_sts[0]); | |
2342 | else | |
7ab284c9 | 2343 | ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n", __func__); |
320a61de NJ |
2344 | |
2345 | return status; | |
2346 | } | |
7ab284c9 NJ |
2347 | |
2348 | int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config) | |
2349 | { | |
2350 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2351 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2352 | struct addr_ctrl_blk *acb = NULL; | |
2353 | uint32_t acb_len = sizeof(struct addr_ctrl_blk); | |
2354 | int rval = QLA_SUCCESS; | |
2355 | dma_addr_t acb_dma; | |
2356 | ||
2357 | acb = dma_alloc_coherent(&ha->pdev->dev, | |
2358 | sizeof(struct addr_ctrl_blk), | |
2359 | &acb_dma, GFP_KERNEL); | |
2360 | if (!acb) { | |
2361 | ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n", __func__); | |
2362 | rval = QLA_ERROR; | |
2363 | goto exit_config_acb; | |
2364 | } | |
2365 | memset(acb, 0, acb_len); | |
2366 | ||
2367 | switch (acb_config) { | |
2368 | case ACB_CONFIG_DISABLE: | |
2369 | rval = qla4xxx_get_acb(ha, acb_dma, 0, acb_len); | |
2370 | if (rval != QLA_SUCCESS) | |
2371 | goto exit_free_acb; | |
2372 | ||
2373 | rval = qla4xxx_disable_acb(ha); | |
2374 | if (rval != QLA_SUCCESS) | |
2375 | goto exit_free_acb; | |
2376 | ||
2377 | if (!ha->saved_acb) | |
2378 | ha->saved_acb = kzalloc(acb_len, GFP_KERNEL); | |
2379 | ||
2380 | if (!ha->saved_acb) { | |
2381 | ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n", | |
2382 | __func__); | |
2383 | rval = QLA_ERROR; | |
7b963c05 | 2384 | goto exit_free_acb; |
7ab284c9 NJ |
2385 | } |
2386 | memcpy(ha->saved_acb, acb, acb_len); | |
2387 | break; | |
2388 | case ACB_CONFIG_SET: | |
2389 | ||
2390 | if (!ha->saved_acb) { | |
2391 | ql4_printk(KERN_ERR, ha, "%s: Can't set ACB, Saved ACB not available\n", | |
2392 | __func__); | |
2393 | rval = QLA_ERROR; | |
2394 | goto exit_free_acb; | |
2395 | } | |
2396 | ||
2397 | memcpy(acb, ha->saved_acb, acb_len); | |
7ab284c9 NJ |
2398 | |
2399 | rval = qla4xxx_set_acb(ha, &mbox_cmd[0], &mbox_sts[0], acb_dma); | |
2400 | if (rval != QLA_SUCCESS) | |
2401 | goto exit_free_acb; | |
2402 | ||
2403 | break; | |
2404 | default: | |
2405 | ql4_printk(KERN_ERR, ha, "%s: Invalid ACB Configuration\n", | |
2406 | __func__); | |
2407 | } | |
2408 | ||
2409 | exit_free_acb: | |
2410 | dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), acb, | |
2411 | acb_dma); | |
2412 | exit_config_acb: | |
f65241e7 NJ |
2413 | if ((acb_config == ACB_CONFIG_SET) && ha->saved_acb) { |
2414 | kfree(ha->saved_acb); | |
2415 | ha->saved_acb = NULL; | |
2416 | } | |
7ab284c9 NJ |
2417 | DEBUG2(ql4_printk(KERN_INFO, ha, |
2418 | "%s %s\n", __func__, | |
2419 | rval == QLA_SUCCESS ? "SUCCEEDED" : "FAILED")); | |
2420 | return rval; | |
2421 | } | |
df86f771 VC |
2422 | |
2423 | int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config) | |
2424 | { | |
2425 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2426 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2427 | int status; | |
2428 | ||
2429 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
2430 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
2431 | ||
2432 | mbox_cmd[0] = MBOX_CMD_GET_PORT_CONFIG; | |
2433 | ||
2434 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT, | |
2435 | mbox_cmd, mbox_sts); | |
2436 | if (status == QLA_SUCCESS) | |
2437 | *config = mbox_sts[1]; | |
2438 | else | |
2439 | ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__, | |
2440 | mbox_sts[0]); | |
2441 | ||
2442 | return status; | |
2443 | } | |
2444 | ||
2445 | int qla4_83xx_set_port_config(struct scsi_qla_host *ha, uint32_t *config) | |
2446 | { | |
2447 | uint32_t mbox_cmd[MBOX_REG_COUNT]; | |
2448 | uint32_t mbox_sts[MBOX_REG_COUNT]; | |
2449 | int status; | |
2450 | ||
2451 | memset(&mbox_cmd, 0, sizeof(mbox_cmd)); | |
2452 | memset(&mbox_sts, 0, sizeof(mbox_sts)); | |
2453 | ||
2454 | mbox_cmd[0] = MBOX_CMD_SET_PORT_CONFIG; | |
2455 | mbox_cmd[1] = *config; | |
2456 | ||
2457 | status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT, | |
2458 | mbox_cmd, mbox_sts); | |
2459 | if (status != QLA_SUCCESS) | |
2460 | ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__, | |
2461 | mbox_sts[0]); | |
2462 | ||
2463 | return status; | |
2464 | } |