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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
41 | #include "scsi.h" | |
42 | #include <scsi/scsi_host.h> | |
43 | #include <linux/libata.h> | |
44 | #include <asm/io.h> | |
45 | #include "sata_promise.h" | |
46 | ||
47 | #define DRV_NAME "sata_promise" | |
6885433c | 48 | #define DRV_VERSION "1.02" |
1da177e4 LT |
49 | |
50 | ||
51 | enum { | |
52 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
53 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
54 | PDC_TBG_MODE = 0x41, /* TBG mode */ | |
55 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | |
56 | PDC_PCI_CTL = 0x48, /* PCI control and status register */ | |
57 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ | |
58 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
59 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
60 | PDC_SLEW_CTL = 0x470, /* slew rate control reg */ | |
61 | ||
62 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
63 | (1<<8) | (1<<9) | (1<<10), | |
64 | ||
65 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
66 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 67 | board_20619 = 2, /* FastTrak TX4000 */ |
1da177e4 LT |
68 | |
69 | PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */ | |
70 | ||
71 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
72 | }; | |
73 | ||
74 | ||
75 | struct pdc_port_priv { | |
76 | u8 *pkt; | |
77 | dma_addr_t pkt_dma; | |
78 | }; | |
79 | ||
80 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
81 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
82 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
83 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs); | |
84 | static void pdc_eng_timeout(struct ata_port *ap); | |
85 | static int pdc_port_start(struct ata_port *ap); | |
86 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a JG |
87 | static void pdc_pata_phy_reset(struct ata_port *ap); |
88 | static void pdc_sata_phy_reset(struct ata_port *ap); | |
1da177e4 LT |
89 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
90 | static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf); | |
91 | static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf); | |
92 | static void pdc_irq_clear(struct ata_port *ap); | |
93 | static int pdc_qc_issue_prot(struct ata_queued_cmd *qc); | |
94 | ||
374b1873 | 95 | |
1da177e4 LT |
96 | static Scsi_Host_Template pdc_ata_sht = { |
97 | .module = THIS_MODULE, | |
98 | .name = DRV_NAME, | |
99 | .ioctl = ata_scsi_ioctl, | |
100 | .queuecommand = ata_scsi_queuecmd, | |
101 | .eh_strategy_handler = ata_scsi_error, | |
102 | .can_queue = ATA_DEF_QUEUE, | |
103 | .this_id = ATA_SHT_THIS_ID, | |
104 | .sg_tablesize = LIBATA_MAX_PRD, | |
105 | .max_sectors = ATA_MAX_SECTORS, | |
106 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
107 | .emulated = ATA_SHT_EMULATED, | |
108 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
109 | .proc_name = DRV_NAME, | |
110 | .dma_boundary = ATA_DMA_BOUNDARY, | |
111 | .slave_configure = ata_scsi_slave_config, | |
112 | .bios_param = ata_std_bios_param, | |
113 | .ordered_flush = 1, | |
114 | }; | |
115 | ||
2cba582a | 116 | static struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
117 | .port_disable = ata_port_disable, |
118 | .tf_load = pdc_tf_load_mmio, | |
119 | .tf_read = ata_tf_read, | |
120 | .check_status = ata_check_status, | |
121 | .exec_command = pdc_exec_command_mmio, | |
122 | .dev_select = ata_std_dev_select, | |
2cba582a JG |
123 | |
124 | .phy_reset = pdc_sata_phy_reset, | |
125 | ||
1da177e4 LT |
126 | .qc_prep = pdc_qc_prep, |
127 | .qc_issue = pdc_qc_issue_prot, | |
128 | .eng_timeout = pdc_eng_timeout, | |
129 | .irq_handler = pdc_interrupt, | |
130 | .irq_clear = pdc_irq_clear, | |
2cba582a | 131 | |
1da177e4 LT |
132 | .scr_read = pdc_sata_scr_read, |
133 | .scr_write = pdc_sata_scr_write, | |
134 | .port_start = pdc_port_start, | |
135 | .port_stop = pdc_port_stop, | |
374b1873 | 136 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
137 | }; |
138 | ||
2cba582a JG |
139 | static struct ata_port_operations pdc_pata_ops = { |
140 | .port_disable = ata_port_disable, | |
141 | .tf_load = pdc_tf_load_mmio, | |
142 | .tf_read = ata_tf_read, | |
143 | .check_status = ata_check_status, | |
144 | .exec_command = pdc_exec_command_mmio, | |
145 | .dev_select = ata_std_dev_select, | |
146 | ||
147 | .phy_reset = pdc_pata_phy_reset, | |
148 | ||
149 | .qc_prep = pdc_qc_prep, | |
150 | .qc_issue = pdc_qc_issue_prot, | |
151 | .eng_timeout = pdc_eng_timeout, | |
152 | .irq_handler = pdc_interrupt, | |
153 | .irq_clear = pdc_irq_clear, | |
154 | ||
155 | .port_start = pdc_port_start, | |
156 | .port_stop = pdc_port_stop, | |
374b1873 | 157 | .host_stop = ata_pci_host_stop, |
2cba582a JG |
158 | }; |
159 | ||
1da177e4 LT |
160 | static struct ata_port_info pdc_port_info[] = { |
161 | /* board_2037x */ | |
162 | { | |
163 | .sht = &pdc_ata_sht, | |
164 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
165 | ATA_FLAG_SRST | ATA_FLAG_MMIO, | |
166 | .pio_mask = 0x1f, /* pio0-4 */ | |
167 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
168 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 169 | .port_ops = &pdc_sata_ops, |
1da177e4 LT |
170 | }, |
171 | ||
172 | /* board_20319 */ | |
173 | { | |
174 | .sht = &pdc_ata_sht, | |
175 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
176 | ATA_FLAG_SRST | ATA_FLAG_MMIO, | |
177 | .pio_mask = 0x1f, /* pio0-4 */ | |
178 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
179 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 180 | .port_ops = &pdc_sata_ops, |
1da177e4 | 181 | }, |
f497ba73 TL |
182 | |
183 | /* board_20619 */ | |
184 | { | |
185 | .sht = &pdc_ata_sht, | |
186 | .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST | | |
187 | ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS, | |
188 | .pio_mask = 0x1f, /* pio0-4 */ | |
189 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
190 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 191 | .port_ops = &pdc_pata_ops, |
f497ba73 | 192 | }, |
1da177e4 LT |
193 | }; |
194 | ||
195 | static struct pci_device_id pdc_ata_pci_tbl[] = { | |
196 | { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
197 | board_2037x }, | |
4c3a53d4 FJ |
198 | { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
199 | board_2037x }, | |
1da177e4 LT |
200 | { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
201 | board_2037x }, | |
202 | { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
203 | board_2037x }, | |
204 | { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
205 | board_2037x }, | |
206 | { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
207 | board_2037x }, | |
208 | { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
209 | board_2037x }, | |
210 | ||
211 | { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
212 | board_20319 }, | |
213 | { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
214 | board_20319 }, | |
93090495 DD |
215 | { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
216 | board_20319 }, | |
08b791c0 OM |
217 | { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
218 | board_20319 }, | |
1da177e4 LT |
219 | { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
220 | board_20319 }, | |
221 | ||
f497ba73 TL |
222 | { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
223 | board_20619 }, | |
224 | ||
1da177e4 LT |
225 | { } /* terminate list */ |
226 | }; | |
227 | ||
228 | ||
229 | static struct pci_driver pdc_ata_pci_driver = { | |
230 | .name = DRV_NAME, | |
231 | .id_table = pdc_ata_pci_tbl, | |
232 | .probe = pdc_ata_init_one, | |
233 | .remove = ata_pci_remove_one, | |
234 | }; | |
235 | ||
236 | ||
237 | static int pdc_port_start(struct ata_port *ap) | |
238 | { | |
239 | struct device *dev = ap->host_set->dev; | |
240 | struct pdc_port_priv *pp; | |
241 | int rc; | |
242 | ||
243 | rc = ata_port_start(ap); | |
244 | if (rc) | |
245 | return rc; | |
246 | ||
247 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
248 | if (!pp) { | |
249 | rc = -ENOMEM; | |
250 | goto err_out; | |
251 | } | |
252 | memset(pp, 0, sizeof(*pp)); | |
253 | ||
254 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
255 | if (!pp->pkt) { | |
256 | rc = -ENOMEM; | |
257 | goto err_out_kfree; | |
258 | } | |
259 | ||
260 | ap->private_data = pp; | |
261 | ||
262 | return 0; | |
263 | ||
264 | err_out_kfree: | |
265 | kfree(pp); | |
266 | err_out: | |
267 | ata_port_stop(ap); | |
268 | return rc; | |
269 | } | |
270 | ||
271 | ||
272 | static void pdc_port_stop(struct ata_port *ap) | |
273 | { | |
274 | struct device *dev = ap->host_set->dev; | |
275 | struct pdc_port_priv *pp = ap->private_data; | |
276 | ||
277 | ap->private_data = NULL; | |
278 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
279 | kfree(pp); | |
280 | ata_port_stop(ap); | |
281 | } | |
282 | ||
283 | ||
284 | static void pdc_reset_port(struct ata_port *ap) | |
285 | { | |
ea6ba10b | 286 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
287 | unsigned int i; |
288 | u32 tmp; | |
289 | ||
290 | for (i = 11; i > 0; i--) { | |
291 | tmp = readl(mmio); | |
292 | if (tmp & PDC_RESET) | |
293 | break; | |
294 | ||
295 | udelay(100); | |
296 | ||
297 | tmp |= PDC_RESET; | |
298 | writel(tmp, mmio); | |
299 | } | |
300 | ||
301 | tmp &= ~PDC_RESET; | |
302 | writel(tmp, mmio); | |
303 | readl(mmio); /* flush */ | |
304 | } | |
305 | ||
2cba582a | 306 | static void pdc_sata_phy_reset(struct ata_port *ap) |
1da177e4 LT |
307 | { |
308 | pdc_reset_port(ap); | |
309 | sata_phy_reset(ap); | |
310 | } | |
311 | ||
2cba582a JG |
312 | static void pdc_pata_phy_reset(struct ata_port *ap) |
313 | { | |
314 | /* FIXME: add cable detect. Don't assume 40-pin cable */ | |
315 | ap->cbl = ATA_CBL_PATA40; | |
316 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
317 | ||
318 | pdc_reset_port(ap); | |
319 | ata_port_probe(ap); | |
320 | ata_bus_reset(ap); | |
321 | } | |
322 | ||
1da177e4 LT |
323 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
324 | { | |
325 | if (sc_reg > SCR_CONTROL) | |
326 | return 0xffffffffU; | |
b181d3b0 | 327 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
328 | } |
329 | ||
330 | ||
331 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
332 | u32 val) | |
333 | { | |
334 | if (sc_reg > SCR_CONTROL) | |
335 | return; | |
b181d3b0 | 336 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
337 | } |
338 | ||
339 | static void pdc_qc_prep(struct ata_queued_cmd *qc) | |
340 | { | |
341 | struct pdc_port_priv *pp = qc->ap->private_data; | |
342 | unsigned int i; | |
343 | ||
344 | VPRINTK("ENTER\n"); | |
345 | ||
346 | switch (qc->tf.protocol) { | |
347 | case ATA_PROT_DMA: | |
348 | ata_qc_prep(qc); | |
349 | /* fall through */ | |
350 | ||
351 | case ATA_PROT_NODATA: | |
352 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
353 | qc->dev->devno, pp->pkt); | |
354 | ||
355 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
356 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
357 | else | |
358 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
359 | ||
360 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
361 | break; | |
362 | ||
363 | default: | |
364 | break; | |
365 | } | |
366 | } | |
367 | ||
368 | static void pdc_eng_timeout(struct ata_port *ap) | |
369 | { | |
b8f6153e | 370 | struct ata_host_set *host_set = ap->host_set; |
1da177e4 LT |
371 | u8 drv_stat; |
372 | struct ata_queued_cmd *qc; | |
b8f6153e | 373 | unsigned long flags; |
1da177e4 LT |
374 | |
375 | DPRINTK("ENTER\n"); | |
376 | ||
b8f6153e JG |
377 | spin_lock_irqsave(&host_set->lock, flags); |
378 | ||
1da177e4 LT |
379 | qc = ata_qc_from_tag(ap, ap->active_tag); |
380 | if (!qc) { | |
381 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | |
382 | ap->id); | |
383 | goto out; | |
384 | } | |
385 | ||
386 | /* hack alert! We cannot use the supplied completion | |
387 | * function from inside the ->eh_strategy_handler() thread. | |
388 | * libata is the only user of ->eh_strategy_handler() in | |
389 | * any kernel, so the default scsi_done() assumes it is | |
390 | * not being called from the SCSI EH. | |
391 | */ | |
392 | qc->scsidone = scsi_finish_command; | |
393 | ||
394 | switch (qc->tf.protocol) { | |
395 | case ATA_PROT_DMA: | |
396 | case ATA_PROT_NODATA: | |
397 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); | |
398 | ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR); | |
399 | break; | |
400 | ||
401 | default: | |
402 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
403 | ||
404 | printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n", | |
405 | ap->id, qc->tf.command, drv_stat); | |
406 | ||
407 | ata_qc_complete(qc, drv_stat); | |
408 | break; | |
409 | } | |
410 | ||
411 | out: | |
b8f6153e | 412 | spin_unlock_irqrestore(&host_set->lock, flags); |
1da177e4 LT |
413 | DPRINTK("EXIT\n"); |
414 | } | |
415 | ||
416 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
417 | struct ata_queued_cmd *qc) | |
418 | { | |
419 | u8 status; | |
420 | unsigned int handled = 0, have_err = 0; | |
421 | u32 tmp; | |
ea6ba10b | 422 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
423 | |
424 | tmp = readl(mmio); | |
425 | if (tmp & PDC_ERR_MASK) { | |
426 | have_err = 1; | |
427 | pdc_reset_port(ap); | |
428 | } | |
429 | ||
430 | switch (qc->tf.protocol) { | |
431 | case ATA_PROT_DMA: | |
432 | case ATA_PROT_NODATA: | |
433 | status = ata_wait_idle(ap); | |
434 | if (have_err) | |
435 | status |= ATA_ERR; | |
436 | ata_qc_complete(qc, status); | |
437 | handled = 1; | |
438 | break; | |
439 | ||
440 | default: | |
ee500aab AL |
441 | ap->stats.idle_irq++; |
442 | break; | |
1da177e4 LT |
443 | } |
444 | ||
ee500aab | 445 | return handled; |
1da177e4 LT |
446 | } |
447 | ||
448 | static void pdc_irq_clear(struct ata_port *ap) | |
449 | { | |
450 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 451 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
452 | |
453 | readl(mmio + PDC_INT_SEQMASK); | |
454 | } | |
455 | ||
456 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs) | |
457 | { | |
458 | struct ata_host_set *host_set = dev_instance; | |
459 | struct ata_port *ap; | |
460 | u32 mask = 0; | |
461 | unsigned int i, tmp; | |
462 | unsigned int handled = 0; | |
ea6ba10b | 463 | void __iomem *mmio_base; |
1da177e4 LT |
464 | |
465 | VPRINTK("ENTER\n"); | |
466 | ||
467 | if (!host_set || !host_set->mmio_base) { | |
468 | VPRINTK("QUICK EXIT\n"); | |
469 | return IRQ_NONE; | |
470 | } | |
471 | ||
472 | mmio_base = host_set->mmio_base; | |
473 | ||
474 | /* reading should also clear interrupts */ | |
475 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
476 | ||
477 | if (mask == 0xffffffff) { | |
478 | VPRINTK("QUICK EXIT 2\n"); | |
479 | return IRQ_NONE; | |
480 | } | |
481 | mask &= 0xffff; /* only 16 tags possible */ | |
482 | if (!mask) { | |
483 | VPRINTK("QUICK EXIT 3\n"); | |
484 | return IRQ_NONE; | |
485 | } | |
486 | ||
487 | spin_lock(&host_set->lock); | |
488 | ||
489 | writel(mask, mmio_base + PDC_INT_SEQMASK); | |
490 | ||
491 | for (i = 0; i < host_set->n_ports; i++) { | |
492 | VPRINTK("port %u\n", i); | |
493 | ap = host_set->ports[i]; | |
494 | tmp = mask & (1 << (i + 1)); | |
c1389503 TH |
495 | if (tmp && ap && |
496 | !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
497 | struct ata_queued_cmd *qc; |
498 | ||
499 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
500 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) | |
501 | handled += pdc_host_intr(ap, qc); | |
502 | } | |
503 | } | |
504 | ||
505 | spin_unlock(&host_set->lock); | |
506 | ||
507 | VPRINTK("EXIT\n"); | |
508 | ||
509 | return IRQ_RETVAL(handled); | |
510 | } | |
511 | ||
512 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
513 | { | |
514 | struct ata_port *ap = qc->ap; | |
515 | struct pdc_port_priv *pp = ap->private_data; | |
516 | unsigned int port_no = ap->port_no; | |
517 | u8 seq = (u8) (port_no + 1); | |
518 | ||
519 | VPRINTK("ENTER, ap %p\n", ap); | |
520 | ||
521 | writel(0x00000001, ap->host_set->mmio_base + (seq * 4)); | |
522 | readl(ap->host_set->mmio_base + (seq * 4)); /* flush */ | |
523 | ||
524 | pp->pkt[2] = seq; | |
525 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
526 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
527 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
528 | } |
529 | ||
530 | static int pdc_qc_issue_prot(struct ata_queued_cmd *qc) | |
531 | { | |
532 | switch (qc->tf.protocol) { | |
533 | case ATA_PROT_DMA: | |
534 | case ATA_PROT_NODATA: | |
535 | pdc_packet_start(qc); | |
536 | return 0; | |
537 | ||
538 | case ATA_PROT_ATAPI_DMA: | |
539 | BUG(); | |
540 | break; | |
541 | ||
542 | default: | |
543 | break; | |
544 | } | |
545 | ||
546 | return ata_qc_issue_prot(qc); | |
547 | } | |
548 | ||
549 | static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf) | |
550 | { | |
551 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
552 | tf->protocol == ATA_PROT_NODATA); | |
553 | ata_tf_load(ap, tf); | |
554 | } | |
555 | ||
556 | ||
557 | static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf) | |
558 | { | |
559 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
560 | tf->protocol == ATA_PROT_NODATA); | |
561 | ata_exec_command(ap, tf); | |
562 | } | |
563 | ||
564 | ||
565 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
566 | { | |
567 | port->cmd_addr = base; | |
568 | port->data_addr = base; | |
569 | port->feature_addr = | |
570 | port->error_addr = base + 0x4; | |
571 | port->nsect_addr = base + 0x8; | |
572 | port->lbal_addr = base + 0xc; | |
573 | port->lbam_addr = base + 0x10; | |
574 | port->lbah_addr = base + 0x14; | |
575 | port->device_addr = base + 0x18; | |
576 | port->command_addr = | |
577 | port->status_addr = base + 0x1c; | |
578 | port->altstatus_addr = | |
579 | port->ctl_addr = base + 0x38; | |
580 | } | |
581 | ||
582 | ||
583 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
584 | { | |
ea6ba10b | 585 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
586 | u32 tmp; |
587 | ||
588 | /* | |
589 | * Except for the hotplug stuff, this is voodoo from the | |
590 | * Promise driver. Label this entire section | |
591 | * "TODO: figure out why we do this" | |
592 | */ | |
593 | ||
594 | /* change FIFO_SHD to 8 dwords, enable BMR_BURST */ | |
595 | tmp = readl(mmio + PDC_FLASH_CTL); | |
596 | tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */ | |
597 | writel(tmp, mmio + PDC_FLASH_CTL); | |
598 | ||
599 | /* clear plug/unplug flags for all ports */ | |
600 | tmp = readl(mmio + PDC_SATA_PLUG_CSR); | |
601 | writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR); | |
602 | ||
603 | /* mask plug/unplug ints */ | |
604 | tmp = readl(mmio + PDC_SATA_PLUG_CSR); | |
605 | writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR); | |
606 | ||
607 | /* reduce TBG clock to 133 Mhz. */ | |
608 | tmp = readl(mmio + PDC_TBG_MODE); | |
609 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
610 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
611 | writel(tmp, mmio + PDC_TBG_MODE); | |
612 | ||
613 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
614 | msleep(10); | |
615 | ||
616 | /* adjust slew rate control register. */ | |
617 | tmp = readl(mmio + PDC_SLEW_CTL); | |
618 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
619 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
620 | writel(tmp, mmio + PDC_SLEW_CTL); | |
621 | } | |
622 | ||
623 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
624 | { | |
625 | static int printed_version; | |
626 | struct ata_probe_ent *probe_ent = NULL; | |
627 | unsigned long base; | |
ea6ba10b | 628 | void __iomem *mmio_base; |
1da177e4 LT |
629 | unsigned int board_idx = (unsigned int) ent->driver_data; |
630 | int pci_dev_busy = 0; | |
631 | int rc; | |
632 | ||
633 | if (!printed_version++) | |
634 | printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); | |
635 | ||
636 | /* | |
637 | * If this driver happens to only be useful on Apple's K2, then | |
638 | * we should check that here as it has a normal Serverworks ID | |
639 | */ | |
640 | rc = pci_enable_device(pdev); | |
641 | if (rc) | |
642 | return rc; | |
643 | ||
644 | rc = pci_request_regions(pdev, DRV_NAME); | |
645 | if (rc) { | |
646 | pci_dev_busy = 1; | |
647 | goto err_out; | |
648 | } | |
649 | ||
650 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
651 | if (rc) | |
652 | goto err_out_regions; | |
653 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
654 | if (rc) | |
655 | goto err_out_regions; | |
656 | ||
657 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
658 | if (probe_ent == NULL) { | |
659 | rc = -ENOMEM; | |
660 | goto err_out_regions; | |
661 | } | |
662 | ||
663 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
664 | probe_ent->dev = pci_dev_to_dev(pdev); | |
665 | INIT_LIST_HEAD(&probe_ent->node); | |
666 | ||
374b1873 | 667 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
668 | if (mmio_base == NULL) { |
669 | rc = -ENOMEM; | |
670 | goto err_out_free_ent; | |
671 | } | |
672 | base = (unsigned long) mmio_base; | |
673 | ||
674 | probe_ent->sht = pdc_port_info[board_idx].sht; | |
675 | probe_ent->host_flags = pdc_port_info[board_idx].host_flags; | |
676 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; | |
677 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
678 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
679 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
680 | ||
681 | probe_ent->irq = pdev->irq; | |
682 | probe_ent->irq_flags = SA_SHIRQ; | |
683 | probe_ent->mmio_base = mmio_base; | |
684 | ||
685 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
686 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
687 | ||
688 | probe_ent->port[0].scr_addr = base + 0x400; | |
689 | probe_ent->port[1].scr_addr = base + 0x500; | |
690 | ||
691 | /* notice 4-port boards */ | |
692 | switch (board_idx) { | |
693 | case board_20319: | |
694 | probe_ent->n_ports = 4; | |
695 | ||
696 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
697 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
698 | ||
699 | probe_ent->port[2].scr_addr = base + 0x600; | |
700 | probe_ent->port[3].scr_addr = base + 0x700; | |
701 | break; | |
702 | case board_2037x: | |
703 | probe_ent->n_ports = 2; | |
704 | break; | |
f497ba73 TL |
705 | case board_20619: |
706 | probe_ent->n_ports = 4; | |
707 | ||
708 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
709 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
710 | ||
711 | probe_ent->port[2].scr_addr = base + 0x600; | |
712 | probe_ent->port[3].scr_addr = base + 0x700; | |
713 | break; | |
1da177e4 LT |
714 | default: |
715 | BUG(); | |
716 | break; | |
717 | } | |
718 | ||
719 | pci_set_master(pdev); | |
720 | ||
721 | /* initialize adapter */ | |
722 | pdc_host_init(board_idx, probe_ent); | |
723 | ||
724 | /* FIXME: check ata_device_add return value */ | |
725 | ata_device_add(probe_ent); | |
726 | kfree(probe_ent); | |
727 | ||
728 | return 0; | |
729 | ||
730 | err_out_free_ent: | |
731 | kfree(probe_ent); | |
732 | err_out_regions: | |
733 | pci_release_regions(pdev); | |
734 | err_out: | |
735 | if (!pci_dev_busy) | |
736 | pci_disable_device(pdev); | |
737 | return rc; | |
738 | } | |
739 | ||
740 | ||
741 | static int __init pdc_ata_init(void) | |
742 | { | |
743 | return pci_module_init(&pdc_ata_pci_driver); | |
744 | } | |
745 | ||
746 | ||
747 | static void __exit pdc_ata_exit(void) | |
748 | { | |
749 | pci_unregister_driver(&pdc_ata_pci_driver); | |
750 | } | |
751 | ||
752 | ||
753 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 754 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
755 | MODULE_LICENSE("GPL"); |
756 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
757 | MODULE_VERSION(DRV_VERSION); | |
758 | ||
759 | module_init(pdc_ata_init); | |
760 | module_exit(pdc_ata_exit); |