[deliverable/linux.git] / drivers / scsi / sata_sil.c

/*
 *  sata_sil.c - Silicon Image SATA
 *
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003-2005 Red Hat, Inc.
 *  Copyright 2003 Benjamin Herrenschmidt
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_sil"
#define DRV_VERSION	"0.9"

enum {
	sil_3112		= 0,
	sil_3114		= 1,

	SIL_FIFO_R0		= 0x40,
	SIL_FIFO_W0		= 0x41,
	SIL_FIFO_R1		= 0x44,
	SIL_FIFO_W1		= 0x45,
	SIL_FIFO_R2		= 0x240,
	SIL_FIFO_W2		= 0x241,
	SIL_FIFO_R3		= 0x244,
	SIL_FIFO_W3		= 0x245,

	SIL_SYSCFG		= 0x48,
	SIL_MASK_IDE0_INT	= (1 << 22),
	SIL_MASK_IDE1_INT	= (1 << 23),
	SIL_MASK_IDE2_INT	= (1 << 24),
	SIL_MASK_IDE3_INT	= (1 << 25),
	SIL_MASK_2PORT		= SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
	SIL_MASK_4PORT		= SIL_MASK_2PORT |
				  SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,

	SIL_IDE2_BMDMA		= 0x200,

	SIL_INTR_STEERING	= (1 << 1),
	SIL_QUIRK_MOD15WRITE	= (1 << 0),
	SIL_QUIRK_UDMA5MAX	= (1 << 1),
};

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static void sil_post_set_mode (struct ata_port *ap);

static struct pci_device_id sil_pci_tbl[] = {
	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ }	/* terminate list */
};


/* TODO firmware versions should be added - eric */
static const struct sil_drivelist {
	const char * product;
	unsigned int quirk;
} sil_blacklist [] = {
	{ "ST320012AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST330013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST340017AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST360015AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380023AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST3120023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120026AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3200822AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST340014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST360014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST380011ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120022ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160021ASL",	SIL_QUIRK_MOD15WRITE },
	{ "Maxtor 4D060H3",	SIL_QUIRK_UDMA5MAX },
	{ }
};

static struct pci_driver sil_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sil_pci_tbl,
	.probe			= sil_init_one,
	.remove			= ata_pci_remove_one,
};

static Scsi_Host_Template sil_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
	.ordered_flush		= 1,
};

static struct ata_port_operations sil_ops = {
	.port_disable		= ata_port_disable,
	.dev_config		= sil_dev_config,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.post_set_mode		= sil_post_set_mode,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= sil_scr_read,
	.scr_write		= sil_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_host_stop,
};

static struct ata_port_info sil_port_info[] = {
	/* sil_3112 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	}, /* sil_3114 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
};

/* per-port register offsets */
/* TODO: we can probably calculate rather than use a table */
static const struct {
	unsigned long tf;	/* ATA taskfile register block */
	unsigned long ctl;	/* ATA control/altstatus register block */
	unsigned long bmdma;	/* DMA register block */
	unsigned long scr;	/* SATA control register block */
	unsigned long sien;	/* SATA Interrupt Enable register */
	unsigned long xfer_mode;/* data transfer mode register */
} sil_port[] = {
	/* port 0 ... */
	{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
	{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
	{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
	{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
	/* ... port 3 */
};

MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
{
	u8 cache_line = 0;
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	return cache_line;
}

static void sil_post_set_mode (struct ata_port *ap)
{
	struct ata_host_set *host_set = ap->host_set;
	struct ata_device *dev;
	void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
	u32 tmp, dev_mode[2];
	unsigned int i;

	for (i = 0; i < 2; i++) {
		dev = &ap->device[i];
		if (!ata_dev_present(dev))
			dev_mode[i] = 0;	/* PIO0/1/2 */
		else if (dev->flags & ATA_DFLAG_PIO)
			dev_mode[i] = 1;	/* PIO3/4 */
		else
			dev_mode[i] = 3;	/* UDMA */
		/* value 2 indicates MDMA */
	}

	tmp = readl(addr);
	tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
	tmp |= dev_mode[0];
	tmp |= (dev_mode[1] << 4);
	writel(tmp, addr);
	readl(addr);	/* flush */
}

static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
{
	unsigned long offset = ap->ioaddr.scr_addr;

	switch (sc_reg) {
	case SCR_STATUS:
		return offset + 4;
	case SCR_ERROR:
		return offset + 8;
	case SCR_CONTROL:
		return offset;
	default:
		/* do nothing */
		break;
	}

	return 0;
}

static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	void *mmio = (void *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		return readl(mmio);
	return 0xffffffffU;
}

static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	void *mmio = (void *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		writel(val, mmio);
}

/**
 *	sil_dev_config - Apply device/host-specific errata fixups
 *	@ap: Port containing device to be examined
 *	@dev: Device to be examined
 *
 *	After the IDENTIFY [PACKET] DEVICE step is complete, and a
 *	device is known to be present, this function is called.
 *	We apply two errata fixups which are specific to Silicon Image,
 *	a Seagate and a Maxtor fixup.
 *
 *	For certain Seagate devices, we must limit the maximum sectors
 *	to under 8K.
 *
 *	For certain Maxtor devices, we must not program the drive
 *	beyond udma5.
 *
 *	Both fixups are unfairly pessimistic.  As soon as I get more
 *	information on these errata, I will create a more exhaustive
 *	list, and apply the fixups to only the specific
 *	devices/hosts/firmwares that need it.
 *
 *	20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
 *	The Maxtor quirk is in the blacklist, but I'm keeping the original
 *	pessimistic fix for the following reasons...
 *	- There seems to be less info on it, only one device gleaned off the
 *	Windows	driver, maybe only one is affected.  More info would be greatly
 *	appreciated.
 *	- But then again UDMA5 is hardly anything to complain about
 */
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
{
	unsigned int n, quirks = 0;
	unsigned char model_num[40];
	const char *s;
	unsigned int len;

	ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
			  sizeof(model_num));
	s = &model_num[0];
	len = strnlen(s, sizeof(model_num));

	/* ATAPI specifies that empty space is blank-filled; remove blanks */
	while ((len > 0) && (s[len - 1] == ' '))
		len--;

	for (n = 0; sil_blacklist[n].product; n++) 
		if (!memcmp(sil_blacklist[n].product, s,
			    strlen(sil_blacklist[n].product))) {
			quirks = sil_blacklist[n].quirk;
			break;
		}
	
	/* limit requests to 15 sectors */
	if (quirks & SIL_QUIRK_MOD15WRITE) {
		printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
		       ap->id, dev->devno);
		ap->host->max_sectors = 15;
		ap->host->hostt->max_sectors = 15;
		dev->flags |= ATA_DFLAG_LOCK_SECTORS;
		return;
	}

	/* limit to udma5 */
	if (quirks & SIL_QUIRK_UDMA5MAX) {
		printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
		       ap->id, dev->devno, s);
		ap->udma_mask &= ATA_UDMA5;
		return;
	}
}

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void *mmio_base;
	int rc;
	unsigned int i;
	int pci_dev_busy = 0;
	u32 tmp, irq_mask;
	u8 cls;

	if (!printed_version++)
		printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");

	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pci_enable_device(pdev);
	if (rc)
		return rc;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	memset(probe_ent, 0, sizeof(*probe_ent));
	INIT_LIST_HEAD(&probe_ent->node);
	probe_ent->dev = pci_dev_to_dev(pdev);
	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
	probe_ent->sht = sil_port_info[ent->driver_data].sht;
	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
       	probe_ent->irq = pdev->irq;
       	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;

	mmio_base = ioremap(pci_resource_start(pdev, 5),
		            pci_resource_len(pdev, 5));
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}

	probe_ent->mmio_base = mmio_base;

	base = (unsigned long) mmio_base;

	for (i = 0; i < probe_ent->n_ports; i++) {
		probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
		probe_ent->port[i].altstatus_addr =
		probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
		probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
		probe_ent->port[i].scr_addr = base + sil_port[i].scr;
		ata_std_ports(&probe_ent->port[i]);
	}

	/* Initialize FIFO PCI bus arbitration */
	cls = sil_get_device_cache_line(pdev);
	if (cls) {
		cls >>= 3;
		cls++;  /* cls = (line_size/8)+1 */
		writeb(cls, mmio_base + SIL_FIFO_R0);
		writeb(cls, mmio_base + SIL_FIFO_W0);
		writeb(cls, mmio_base + SIL_FIFO_R1);
		writeb(cls, mmio_base + SIL_FIFO_W1);
		if (ent->driver_data == sil_3114) {
			writeb(cls, mmio_base + SIL_FIFO_R2);
			writeb(cls, mmio_base + SIL_FIFO_W2);
			writeb(cls, mmio_base + SIL_FIFO_R3);
			writeb(cls, mmio_base + SIL_FIFO_W3);
		}
	} else
		printk(KERN_WARNING DRV_NAME "(%s): cache line size not set.  Driver may not function\n",
			pci_name(pdev));

	if (ent->driver_data == sil_3114) {
		irq_mask = SIL_MASK_4PORT;

		/* flip the magic "make 4 ports work" bit */
		tmp = readl(mmio_base + SIL_IDE2_BMDMA);
		if ((tmp & SIL_INTR_STEERING) == 0)
			writel(tmp | SIL_INTR_STEERING,
			       mmio_base + SIL_IDE2_BMDMA);

	} else {
		irq_mask = SIL_MASK_2PORT;
	}

	/* make sure IDE0/1/2/3 interrupts are not masked */
	tmp = readl(mmio_base + SIL_SYSCFG);
	if (tmp & irq_mask) {
		tmp &= ~irq_mask;
		writel(tmp, mmio_base + SIL_SYSCFG);
		readl(mmio_base + SIL_SYSCFG);	/* flush */
	}

	/* mask all SATA phy-related interrupts */
	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	for (i = 0; i < probe_ent->n_ports; i++)
		writel(0, mmio_base + sil_port[i].sien);

	pci_set_master(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}

static int __init sil_init(void)
{
	return pci_module_init(&sil_pci_driver);
}

static void __exit sil_exit(void)
{
	pci_unregister_driver(&sil_pci_driver);
}


module_init(sil_init);
module_exit(sil_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sil.c - Silicon Image SATA
	3	*
	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
af36d7f0	8	* Copyright 2003-2005 Red Hat, Inc.
1da177e4 LT	9	* Copyright 2003 Benjamin Herrenschmidt
1da177e4 LT	10	*
af36d7f0 JG	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2, or (at your option)
	15	* any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; see the file COPYING. If not, write to
	24	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
	26	*
	27	* libata documentation is available via 'make {ps\|pdf}docs',
	28	* as Documentation/DocBook/libata.*
1da177e4 LT	29	*
	30	*/
	31
	32	#include <linux/kernel.h>
	33	#include <linux/module.h>
	34	#include <linux/pci.h>
	35	#include <linux/init.h>
	36	#include <linux/blkdev.h>
	37	#include <linux/delay.h>
	38	#include <linux/interrupt.h>
	39	#include "scsi.h"
	40	#include <scsi/scsi_host.h>
	41	#include <linux/libata.h>
	42
	43	#define DRV_NAME "sata_sil"
	44	#define DRV_VERSION "0.9"
	45
	46	enum {
	47	sil_3112 = 0,
	48	sil_3114 = 1,
	49
	50	SIL_FIFO_R0 = 0x40,
	51	SIL_FIFO_W0 = 0x41,
	52	SIL_FIFO_R1 = 0x44,
	53	SIL_FIFO_W1 = 0x45,
	54	SIL_FIFO_R2 = 0x240,
	55	SIL_FIFO_W2 = 0x241,
	56	SIL_FIFO_R3 = 0x244,
	57	SIL_FIFO_W3 = 0x245,
	58
	59	SIL_SYSCFG = 0x48,
	60	SIL_MASK_IDE0_INT = (1 << 22),
	61	SIL_MASK_IDE1_INT = (1 << 23),
	62	SIL_MASK_IDE2_INT = (1 << 24),
	63	SIL_MASK_IDE3_INT = (1 << 25),
	64	SIL_MASK_2PORT = SIL_MASK_IDE0_INT \| SIL_MASK_IDE1_INT,
	65	SIL_MASK_4PORT = SIL_MASK_2PORT \|
	66	SIL_MASK_IDE2_INT \| SIL_MASK_IDE3_INT,
	67
	68	SIL_IDE2_BMDMA = 0x200,
	69
	70	SIL_INTR_STEERING = (1 << 1),
	71	SIL_QUIRK_MOD15WRITE = (1 << 0),
	72	SIL_QUIRK_UDMA5MAX = (1 << 1),
	73	};
	74
	75	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	76	static void sil_dev_config(struct ata_port ap, struct ata_device dev);
	77	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
	78	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	79	static void sil_post_set_mode (struct ata_port *ap);
	80
	81	static struct pci_device_id sil_pci_tbl[] = {
	82	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	83	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	84	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	85	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
	86	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	87	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
525a0997	88	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
1da177e4 LT	89	{ } /* terminate list */
	90	};
	91
	92
	93	/* TODO firmware versions should be added - eric */
	94	static const struct sil_drivelist {
	95	const char * product;
	96	unsigned int quirk;
	97	} sil_blacklist [] = {
	98	{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
	99	{ "ST330013AS", SIL_QUIRK_MOD15WRITE },
	100	{ "ST340017AS", SIL_QUIRK_MOD15WRITE },
	101	{ "ST360015AS", SIL_QUIRK_MOD15WRITE },
	102	{ "ST380013AS", SIL_QUIRK_MOD15WRITE },
	103	{ "ST380023AS", SIL_QUIRK_MOD15WRITE },
	104	{ "ST3120023AS", SIL_QUIRK_MOD15WRITE },
	105	{ "ST3160023AS", SIL_QUIRK_MOD15WRITE },
	106	{ "ST3120026AS", SIL_QUIRK_MOD15WRITE },
	107	{ "ST3200822AS", SIL_QUIRK_MOD15WRITE },
	108	{ "ST340014ASL", SIL_QUIRK_MOD15WRITE },
	109	{ "ST360014ASL", SIL_QUIRK_MOD15WRITE },
	110	{ "ST380011ASL", SIL_QUIRK_MOD15WRITE },
	111	{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
	112	{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
	113	{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
	114	{ }
	115	};
	116
	117	static struct pci_driver sil_pci_driver = {
	118	.name = DRV_NAME,
	119	.id_table = sil_pci_tbl,
	120	.probe = sil_init_one,
	121	.remove = ata_pci_remove_one,
	122	};
	123
	124	static Scsi_Host_Template sil_sht = {
	125	.module = THIS_MODULE,
	126	.name = DRV_NAME,
	127	.ioctl = ata_scsi_ioctl,
	128	.queuecommand = ata_scsi_queuecmd,
	129	.eh_strategy_handler = ata_scsi_error,
	130	.can_queue = ATA_DEF_QUEUE,
	131	.this_id = ATA_SHT_THIS_ID,
	132	.sg_tablesize = LIBATA_MAX_PRD,
	133	.max_sectors = ATA_MAX_SECTORS,
	134	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	135	.emulated = ATA_SHT_EMULATED,
	136	.use_clustering = ATA_SHT_USE_CLUSTERING,
	137	.proc_name = DRV_NAME,
	138	.dma_boundary = ATA_DMA_BOUNDARY,
	139	.slave_configure = ata_scsi_slave_config,
	140	.bios_param = ata_std_bios_param,
	141	.ordered_flush = 1,
	142	};
	143
	144	static struct ata_port_operations sil_ops = {
	145	.port_disable = ata_port_disable,
	146	.dev_config = sil_dev_config,
	147	.tf_load = ata_tf_load,
	148	.tf_read = ata_tf_read,
	149	.check_status = ata_check_status,
	150	.exec_command = ata_exec_command,
	151	.dev_select = ata_std_dev_select,
	152	.phy_reset = sata_phy_reset,
153	.post_set_mode = sil_post_set_mode,
154	.bmdma_setup = ata_bmdma_setup,
155	.bmdma_start = ata_bmdma_start,
156	.bmdma_stop = ata_bmdma_stop,
157	.bmdma_status = ata_bmdma_status,
158	.qc_prep = ata_qc_prep,
159	.qc_issue = ata_qc_issue_prot,
160	.eng_timeout = ata_eng_timeout,
161	.irq_handler = ata_interrupt,
162	.irq_clear = ata_bmdma_irq_clear,
163	.scr_read = sil_scr_read,
164	.scr_write = sil_scr_write,
165	.port_start = ata_port_start,
166	.port_stop = ata_port_stop,
aa8f0dc6	167	.host_stop = ata_host_stop,
1da177e4 LT	168	};
	169
	170	static struct ata_port_info sil_port_info[] = {
	171	/* sil_3112 */
	172	{
	173	.sht = &sil_sht,
	174	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	175	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
	176	.pio_mask = 0x1f, /* pio0-4 */
	177	.mwdma_mask = 0x07, /* mwdma0-2 */
	178	.udma_mask = 0x3f, /* udma0-5 */
	179	.port_ops = &sil_ops,
	180	}, /* sil_3114 */
	181	{
	182	.sht = &sil_sht,
	183	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	184	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
	185	.pio_mask = 0x1f, /* pio0-4 */
	186	.mwdma_mask = 0x07, /* mwdma0-2 */
	187	.udma_mask = 0x3f, /* udma0-5 */
	188	.port_ops = &sil_ops,
	189	},
	190	};
	191
	192	/* per-port register offsets */
	193	/* TODO: we can probably calculate rather than use a table */
	194	static const struct {
	195	unsigned long tf; /* ATA taskfile register block */
	196	unsigned long ctl; /* ATA control/altstatus register block */
	197	unsigned long bmdma; /* DMA register block */
	198	unsigned long scr; /* SATA control register block */
	199	unsigned long sien; /* SATA Interrupt Enable register */
	200	unsigned long xfer_mode;/* data transfer mode register */
	201	} sil_port[] = {
	202	/* port 0 ... */
	203	{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
	204	{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
	205	{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
	206	{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
	207	/* ... port 3 */
	208	};
	209
	210	MODULE_AUTHOR("Jeff Garzik");
	211	MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
	212	MODULE_LICENSE("GPL");
	213	MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
	214	MODULE_VERSION(DRV_VERSION);
	215
	216	static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
	217	{
	218	u8 cache_line = 0;
	219	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	220	return cache_line;
	221	}
	222
	223	static void sil_post_set_mode (struct ata_port *ap)
	224	{
	225	struct ata_host_set *host_set = ap->host_set;
	226	struct ata_device *dev;
	227	void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
	228	u32 tmp, dev_mode[2];
	229	unsigned int i;
	230
	231	for (i = 0; i < 2; i++) {
232	dev = &ap->device[i];
233	if (!ata_dev_present(dev))
234	dev_mode[i] = 0; /* PIO0/1/2 */
235	else if (dev->flags & ATA_DFLAG_PIO)
236	dev_mode[i] = 1; /* PIO3/4 */
237	else
238	dev_mode[i] = 3; /* UDMA */
239	/* value 2 indicates MDMA */
240	}
241
242	tmp = readl(addr);
243	tmp &= ~((1<<5) \| (1<<4) \| (1<<1) \| (1<<0));
244	tmp \|= dev_mode[0];
245	tmp \|= (dev_mode[1] << 4);
246	writel(tmp, addr);
247	readl(addr); /* flush */
248	}
249
250	static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
251	{
252	unsigned long offset = ap->ioaddr.scr_addr;
253
254	switch (sc_reg) {
255	case SCR_STATUS:
256	return offset + 4;
257	case SCR_ERROR:
258	return offset + 8;
259	case SCR_CONTROL:
260	return offset;
261	default:
262	/* do nothing */
263	break;
264	}
265
266	return 0;
267	}
268
269	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
270	{
271	void mmio = (void ) sil_scr_addr(ap, sc_reg);
272	if (mmio)
273	return readl(mmio);
274	return 0xffffffffU;
275	}
276
277	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
278	{
279	void mmio = (void ) sil_scr_addr(ap, sc_reg);
280	if (mmio)
281	writel(val, mmio);
282	}
283
284	/**
285	* sil_dev_config - Apply device/host-specific errata fixups
286	* @ap: Port containing device to be examined
287	* @dev: Device to be examined
288	*
289	* After the IDENTIFY [PACKET] DEVICE step is complete, and a
290	* device is known to be present, this function is called.
291	* We apply two errata fixups which are specific to Silicon Image,
292	* a Seagate and a Maxtor fixup.
293	*
294	* For certain Seagate devices, we must limit the maximum sectors
295	* to under 8K.
296	*
297	* For certain Maxtor devices, we must not program the drive
298	* beyond udma5.
299	*
300	* Both fixups are unfairly pessimistic. As soon as I get more
301	* information on these errata, I will create a more exhaustive
302	* list, and apply the fixups to only the specific
303	* devices/hosts/firmwares that need it.
304	*
305	* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
306	* The Maxtor quirk is in the blacklist, but I'm keeping the original
307	* pessimistic fix for the following reasons...
308	* - There seems to be less info on it, only one device gleaned off the
309	* Windows driver, maybe only one is affected. More info would be greatly
310	* appreciated.
311	* - But then again UDMA5 is hardly anything to complain about
312	*/
313	static void sil_dev_config(struct ata_port ap, struct ata_device dev)
314	{
315	unsigned int n, quirks = 0;
316	unsigned char model_num[40];
317	const char *s;
318	unsigned int len;
319
320	ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
321	sizeof(model_num));
322	s = &model_num[0];
323	len = strnlen(s, sizeof(model_num));
324
325	/* ATAPI specifies that empty space is blank-filled; remove blanks */
326	while ((len > 0) && (s[len - 1] == ' '))
327	len--;
328
329	for (n = 0; sil_blacklist[n].product; n++)
330	if (!memcmp(sil_blacklist[n].product, s,
331	strlen(sil_blacklist[n].product))) {
332	quirks = sil_blacklist[n].quirk;
333	break;
334	}
335
336	/* limit requests to 15 sectors */
337	if (quirks & SIL_QUIRK_MOD15WRITE) {
338	printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
339	ap->id, dev->devno);
340	ap->host->max_sectors = 15;
341	ap->host->hostt->max_sectors = 15;
342	dev->flags \|= ATA_DFLAG_LOCK_SECTORS;
343	return;
344	}
345
346	/* limit to udma5 */
347	if (quirks & SIL_QUIRK_UDMA5MAX) {
348	printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
349	ap->id, dev->devno, s);
350	ap->udma_mask &= ATA_UDMA5;
351	return;
352	}
353	}
354
355	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent)
356	{
357	static int printed_version;
358	struct ata_probe_ent *probe_ent = NULL;
359	unsigned long base;
360	void *mmio_base;
361	int rc;
362	unsigned int i;
363	int pci_dev_busy = 0;
364	u32 tmp, irq_mask;
365	u8 cls;
366
367	if (!printed_version++)
368	printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
369
370	/*
371	* If this driver happens to only be useful on Apple's K2, then
372	* we should check that here as it has a normal Serverworks ID
373	*/
374	rc = pci_enable_device(pdev);
375	if (rc)
376	return rc;
377
378	rc = pci_request_regions(pdev, DRV_NAME);
379	if (rc) {
380	pci_dev_busy = 1;
381	goto err_out;
382	}
383
384	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
385	if (rc)
386	goto err_out_regions;
387	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
388	if (rc)
389	goto err_out_regions;
390
391	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
392	if (probe_ent == NULL) {
393	rc = -ENOMEM;
394	goto err_out_regions;
395	}
396
397	memset(probe_ent, 0, sizeof(*probe_ent));
398	INIT_LIST_HEAD(&probe_ent->node);
399	probe_ent->dev = pci_dev_to_dev(pdev);
400	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
401	probe_ent->sht = sil_port_info[ent->driver_data].sht;
402	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
403	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
404	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
405	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
406	probe_ent->irq = pdev->irq;
407	probe_ent->irq_flags = SA_SHIRQ;
408	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
409
410	mmio_base = ioremap(pci_resource_start(pdev, 5),
411	pci_resource_len(pdev, 5));
412	if (mmio_base == NULL) {
413	rc = -ENOMEM;
414	goto err_out_free_ent;
415	}
416
417	probe_ent->mmio_base = mmio_base;
418
419	base = (unsigned long) mmio_base;
420
421	for (i = 0; i < probe_ent->n_ports; i++) {
422	probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
423	probe_ent->port[i].altstatus_addr =
424	probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
425	probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
426	probe_ent->port[i].scr_addr = base + sil_port[i].scr;
427	ata_std_ports(&probe_ent->port[i]);
428	}
429
430	/* Initialize FIFO PCI bus arbitration */
431	cls = sil_get_device_cache_line(pdev);
432	if (cls) {
433	cls >>= 3;
434	cls++; /* cls = (line_size/8)+1 */
435	writeb(cls, mmio_base + SIL_FIFO_R0);
436	writeb(cls, mmio_base + SIL_FIFO_W0);
437	writeb(cls, mmio_base + SIL_FIFO_R1);
e1dd23a0 JA	438	writeb(cls, mmio_base + SIL_FIFO_W1);
	439	if (ent->driver_data == sil_3114) {
	440	writeb(cls, mmio_base + SIL_FIFO_R2);
	441	writeb(cls, mmio_base + SIL_FIFO_W2);
	442	writeb(cls, mmio_base + SIL_FIFO_R3);
	443	writeb(cls, mmio_base + SIL_FIFO_W3);
	444	}
1da177e4 LT	445	} else
	446	printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n",
	447	pci_name(pdev));
	448
	449	if (ent->driver_data == sil_3114) {
	450	irq_mask = SIL_MASK_4PORT;
	451
	452	/* flip the magic "make 4 ports work" bit */
	453	tmp = readl(mmio_base + SIL_IDE2_BMDMA);
	454	if ((tmp & SIL_INTR_STEERING) == 0)
	455	writel(tmp \| SIL_INTR_STEERING,
	456	mmio_base + SIL_IDE2_BMDMA);
	457
	458	} else {
	459	irq_mask = SIL_MASK_2PORT;
	460	}
	461
	462	/* make sure IDE0/1/2/3 interrupts are not masked */
	463	tmp = readl(mmio_base + SIL_SYSCFG);
	464	if (tmp & irq_mask) {
	465	tmp &= ~irq_mask;
	466	writel(tmp, mmio_base + SIL_SYSCFG);
	467	readl(mmio_base + SIL_SYSCFG); /* flush */
	468	}
	469
	470	/* mask all SATA phy-related interrupts */
	471	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	472	for (i = 0; i < probe_ent->n_ports; i++)
	473	writel(0, mmio_base + sil_port[i].sien);
	474
	475	pci_set_master(pdev);
	476
	477	/* FIXME: check ata_device_add return value */
	478	ata_device_add(probe_ent);
	479	kfree(probe_ent);
	480
	481	return 0;
	482
	483	err_out_free_ent:
	484	kfree(probe_ent);
	485	err_out_regions:
	486	pci_release_regions(pdev);
	487	err_out:
	488	if (!pci_dev_busy)
	489	pci_disable_device(pdev);
	490	return rc;
	491	}
	492
	493	static int __init sil_init(void)
	494	{
	495	return pci_module_init(&sil_pci_driver);
	496	}
	497
	498	static void __exit sil_exit(void)
	499	{
	500	pci_unregister_driver(&sil_pci_driver);
	501	}
	502
	503
	504	module_init(sil_init);
	505	module_exit(sil_exit);