[deliverable/linux.git] / drivers / scsi / sata_sil.c

/*
 *  sata_sil.c - Silicon Image SATA
 *
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003 Red Hat, Inc.
 *  Copyright 2003 Benjamin Herrenschmidt
 *
 *  The contents of this file are subject to the Open
 *  Software License version 1.1 that can be found at
 *  http://www.opensource.org/licenses/osl-1.1.txt and is included herein
 *  by reference.
 *
 *  Alternatively, the contents of this file may be used under the terms
 *  of the GNU General Public License version 2 (the "GPL") as distributed
 *  in the kernel source COPYING file, in which case the provisions of
 *  the GPL are applicable instead of the above.  If you wish to allow
 *  the use of your version of this file only under the terms of the
 *  GPL and not to allow others to use your version of this file under
 *  the OSL, indicate your decision by deleting the provisions above and
 *  replace them with the notice and other provisions required by the GPL.
 *  If you do not delete the provisions above, a recipient may use your
 *  version of this file under either the OSL or the GPL.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_sil"
#define DRV_VERSION	"0.9"

enum {
	sil_3112		= 0,
	sil_3114		= 1,

	SIL_FIFO_R0		= 0x40,
	SIL_FIFO_W0		= 0x41,
	SIL_FIFO_R1		= 0x44,
	SIL_FIFO_W1		= 0x45,
	SIL_FIFO_R2		= 0x240,
	SIL_FIFO_W2		= 0x241,
	SIL_FIFO_R3		= 0x244,
	SIL_FIFO_W3		= 0x245,

	SIL_SYSCFG		= 0x48,
	SIL_MASK_IDE0_INT	= (1 << 22),
	SIL_MASK_IDE1_INT	= (1 << 23),
	SIL_MASK_IDE2_INT	= (1 << 24),
	SIL_MASK_IDE3_INT	= (1 << 25),
	SIL_MASK_2PORT		= SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
	SIL_MASK_4PORT		= SIL_MASK_2PORT |
				  SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,

	SIL_IDE2_BMDMA		= 0x200,

	SIL_INTR_STEERING	= (1 << 1),
	SIL_QUIRK_MOD15WRITE	= (1 << 0),
	SIL_QUIRK_UDMA5MAX	= (1 << 1),
};

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static void sil_post_set_mode (struct ata_port *ap);

static struct pci_device_id sil_pci_tbl[] = {
	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ }	/* terminate list */
};


/* TODO firmware versions should be added - eric */
static const struct sil_drivelist {
	const char * product;
	unsigned int quirk;
} sil_blacklist [] = {
	{ "ST320012AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST330013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST340017AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST360015AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380023AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST3120023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120026AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3200822AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST340014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST360014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST380011ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120022ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160021ASL",	SIL_QUIRK_MOD15WRITE },
	{ "Maxtor 4D060H3",	SIL_QUIRK_UDMA5MAX },
	{ }
};

static struct pci_driver sil_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sil_pci_tbl,
	.probe			= sil_init_one,
	.remove			= ata_pci_remove_one,
};

static Scsi_Host_Template sil_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
	.ordered_flush		= 1,
};

static struct ata_port_operations sil_ops = {
	.port_disable		= ata_port_disable,
	.dev_config		= sil_dev_config,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.post_set_mode		= sil_post_set_mode,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= sil_scr_read,
	.scr_write		= sil_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
};

static struct ata_port_info sil_port_info[] = {
	/* sil_3112 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	}, /* sil_3114 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
};

/* per-port register offsets */
/* TODO: we can probably calculate rather than use a table */
static const struct {
	unsigned long tf;	/* ATA taskfile register block */
	unsigned long ctl;	/* ATA control/altstatus register block */
	unsigned long bmdma;	/* DMA register block */
	unsigned long scr;	/* SATA control register block */
	unsigned long sien;	/* SATA Interrupt Enable register */
	unsigned long xfer_mode;/* data transfer mode register */
} sil_port[] = {
	/* port 0 ... */
	{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
	{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
	{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
	{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
	/* ... port 3 */
};

MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
{
	u8 cache_line = 0;
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	return cache_line;
}

static void sil_post_set_mode (struct ata_port *ap)
{
	struct ata_host_set *host_set = ap->host_set;
	struct ata_device *dev;
	void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
	u32 tmp, dev_mode[2];
	unsigned int i;

	for (i = 0; i < 2; i++) {
		dev = &ap->device[i];
		if (!ata_dev_present(dev))
			dev_mode[i] = 0;	/* PIO0/1/2 */
		else if (dev->flags & ATA_DFLAG_PIO)
			dev_mode[i] = 1;	/* PIO3/4 */
		else
			dev_mode[i] = 3;	/* UDMA */
		/* value 2 indicates MDMA */
	}

	tmp = readl(addr);
	tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
	tmp |= dev_mode[0];
	tmp |= (dev_mode[1] << 4);
	writel(tmp, addr);
	readl(addr);	/* flush */
}

static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
{
	unsigned long offset = ap->ioaddr.scr_addr;

	switch (sc_reg) {
	case SCR_STATUS:
		return offset + 4;
	case SCR_ERROR:
		return offset + 8;
	case SCR_CONTROL:
		return offset;
	default:
		/* do nothing */
		break;
	}

	return 0;
}

static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	void *mmio = (void *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		return readl(mmio);
	return 0xffffffffU;
}

static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	void *mmio = (void *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		writel(val, mmio);
}

/**
 *	sil_dev_config - Apply device/host-specific errata fixups
 *	@ap: Port containing device to be examined
 *	@dev: Device to be examined
 *
 *	After the IDENTIFY [PACKET] DEVICE step is complete, and a
 *	device is known to be present, this function is called.
 *	We apply two errata fixups which are specific to Silicon Image,
 *	a Seagate and a Maxtor fixup.
 *
 *	For certain Seagate devices, we must limit the maximum sectors
 *	to under 8K.
 *
 *	For certain Maxtor devices, we must not program the drive
 *	beyond udma5.
 *
 *	Both fixups are unfairly pessimistic.  As soon as I get more
 *	information on these errata, I will create a more exhaustive
 *	list, and apply the fixups to only the specific
 *	devices/hosts/firmwares that need it.
 *
 *	20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
 *	The Maxtor quirk is in the blacklist, but I'm keeping the original
 *	pessimistic fix for the following reasons...
 *	- There seems to be less info on it, only one device gleaned off the
 *	Windows	driver, maybe only one is affected.  More info would be greatly
 *	appreciated.
 *	- But then again UDMA5 is hardly anything to complain about
 */
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
{
	unsigned int n, quirks = 0;
	unsigned char model_num[40];
	const char *s;
	unsigned int len;

	ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
			  sizeof(model_num));
	s = &model_num[0];
	len = strnlen(s, sizeof(model_num));

	/* ATAPI specifies that empty space is blank-filled; remove blanks */
	while ((len > 0) && (s[len - 1] == ' '))
		len--;

	for (n = 0; sil_blacklist[n].product; n++) 
		if (!memcmp(sil_blacklist[n].product, s,
			    strlen(sil_blacklist[n].product))) {
			quirks = sil_blacklist[n].quirk;
			break;
		}
	
	/* limit requests to 15 sectors */
	if (quirks & SIL_QUIRK_MOD15WRITE) {
		printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
		       ap->id, dev->devno);
		ap->host->max_sectors = 15;
		ap->host->hostt->max_sectors = 15;
		dev->flags |= ATA_DFLAG_LOCK_SECTORS;
		return;
	}

	/* limit to udma5 */
	if (quirks & SIL_QUIRK_UDMA5MAX) {
		printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
		       ap->id, dev->devno, s);
		ap->udma_mask &= ATA_UDMA5;
		return;
	}
}

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void *mmio_base;
	int rc;
	unsigned int i;
	int pci_dev_busy = 0;
	u32 tmp, irq_mask;
	u8 cls;

	if (!printed_version++)
		printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");

	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pci_enable_device(pdev);
	if (rc)
		return rc;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	memset(probe_ent, 0, sizeof(*probe_ent));
	INIT_LIST_HEAD(&probe_ent->node);
	probe_ent->dev = pci_dev_to_dev(pdev);
	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
	probe_ent->sht = sil_port_info[ent->driver_data].sht;
	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
       	probe_ent->irq = pdev->irq;
       	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;

	mmio_base = ioremap(pci_resource_start(pdev, 5),
		            pci_resource_len(pdev, 5));
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}

	probe_ent->mmio_base = mmio_base;

	base = (unsigned long) mmio_base;

	for (i = 0; i < probe_ent->n_ports; i++) {
		probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
		probe_ent->port[i].altstatus_addr =
		probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
		probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
		probe_ent->port[i].scr_addr = base + sil_port[i].scr;
		ata_std_ports(&probe_ent->port[i]);
	}

	/* Initialize FIFO PCI bus arbitration */
	cls = sil_get_device_cache_line(pdev);
	if (cls) {
		cls >>= 3;
		cls++;  /* cls = (line_size/8)+1 */
		writeb(cls, mmio_base + SIL_FIFO_R0);
		writeb(cls, mmio_base + SIL_FIFO_W0);
		writeb(cls, mmio_base + SIL_FIFO_R1);
		writeb(cls, mmio_base + SIL_FIFO_W2);
	} else
		printk(KERN_WARNING DRV_NAME "(%s): cache line size not set.  Driver may not function\n",
			pci_name(pdev));

	if (ent->driver_data == sil_3114) {
		irq_mask = SIL_MASK_4PORT;

		/* flip the magic "make 4 ports work" bit */
		tmp = readl(mmio_base + SIL_IDE2_BMDMA);
		if ((tmp & SIL_INTR_STEERING) == 0)
			writel(tmp | SIL_INTR_STEERING,
			       mmio_base + SIL_IDE2_BMDMA);

	} else {
		irq_mask = SIL_MASK_2PORT;
	}

	/* make sure IDE0/1/2/3 interrupts are not masked */
	tmp = readl(mmio_base + SIL_SYSCFG);
	if (tmp & irq_mask) {
		tmp &= ~irq_mask;
		writel(tmp, mmio_base + SIL_SYSCFG);
		readl(mmio_base + SIL_SYSCFG);	/* flush */
	}

	/* mask all SATA phy-related interrupts */
	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	for (i = 0; i < probe_ent->n_ports; i++)
		writel(0, mmio_base + sil_port[i].sien);

	pci_set_master(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}

static int __init sil_init(void)
{
	return pci_module_init(&sil_pci_driver);
}

static void __exit sil_exit(void)
{
	pci_unregister_driver(&sil_pci_driver);
}


module_init(sil_init);
module_exit(sil_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sil.c - Silicon Image SATA
	3	*
	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2003 Red Hat, Inc.
	9	* Copyright 2003 Benjamin Herrenschmidt
	10	*
	11	* The contents of this file are subject to the Open
	12	* Software License version 1.1 that can be found at
	13	* http://www.opensource.org/licenses/osl-1.1.txt and is included herein
	14	* by reference.
	15	*
	16	* Alternatively, the contents of this file may be used under the terms
	17	* of the GNU General Public License version 2 (the "GPL") as distributed
	18	* in the kernel source COPYING file, in which case the provisions of
	19	* the GPL are applicable instead of the above. If you wish to allow
	20	* the use of your version of this file only under the terms of the
	21	* GPL and not to allow others to use your version of this file under
	22	* the OSL, indicate your decision by deleting the provisions above and
	23	* replace them with the notice and other provisions required by the GPL.
	24	* If you do not delete the provisions above, a recipient may use your
	25	* version of this file under either the OSL or the GPL.
	26	*
	27	*/
	28
	29	#include <linux/kernel.h>
	30	#include <linux/module.h>
	31	#include <linux/pci.h>
	32	#include <linux/init.h>
	33	#include <linux/blkdev.h>
	34	#include <linux/delay.h>
	35	#include <linux/interrupt.h>
	36	#include "scsi.h"
	37	#include <scsi/scsi_host.h>
	38	#include <linux/libata.h>
	39
	40	#define DRV_NAME "sata_sil"
	41	#define DRV_VERSION "0.9"
	42
	43	enum {
	44	sil_3112 = 0,
	45	sil_3114 = 1,
	46
	47	SIL_FIFO_R0 = 0x40,
	48	SIL_FIFO_W0 = 0x41,
	49	SIL_FIFO_R1 = 0x44,
	50	SIL_FIFO_W1 = 0x45,
	51	SIL_FIFO_R2 = 0x240,
	52	SIL_FIFO_W2 = 0x241,
	53	SIL_FIFO_R3 = 0x244,
	54	SIL_FIFO_W3 = 0x245,
	55
	56	SIL_SYSCFG = 0x48,
	57	SIL_MASK_IDE0_INT = (1 << 22),
	58	SIL_MASK_IDE1_INT = (1 << 23),
	59	SIL_MASK_IDE2_INT = (1 << 24),
	60	SIL_MASK_IDE3_INT = (1 << 25),
	61	SIL_MASK_2PORT = SIL_MASK_IDE0_INT \| SIL_MASK_IDE1_INT,
	62	SIL_MASK_4PORT = SIL_MASK_2PORT \|
	63	SIL_MASK_IDE2_INT \| SIL_MASK_IDE3_INT,
	64
65	SIL_IDE2_BMDMA = 0x200,
66
67	SIL_INTR_STEERING = (1 << 1),
68	SIL_QUIRK_MOD15WRITE = (1 << 0),
69	SIL_QUIRK_UDMA5MAX = (1 << 1),
70	};
71
72	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent);
73	static void sil_dev_config(struct ata_port ap, struct ata_device dev);
74	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
75	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
76	static void sil_post_set_mode (struct ata_port *ap);
77
78	static struct pci_device_id sil_pci_tbl[] = {
79	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
80	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
81	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
82	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
83	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
84	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
525a0997	85	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
1da177e4 LT	86	{ } /* terminate list */
	87	};
	88
	89
	90	/* TODO firmware versions should be added - eric */
	91	static const struct sil_drivelist {
	92	const char * product;
	93	unsigned int quirk;
	94	} sil_blacklist [] = {
	95	{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
	96	{ "ST330013AS", SIL_QUIRK_MOD15WRITE },
	97	{ "ST340017AS", SIL_QUIRK_MOD15WRITE },
	98	{ "ST360015AS", SIL_QUIRK_MOD15WRITE },
	99	{ "ST380013AS", SIL_QUIRK_MOD15WRITE },
	100	{ "ST380023AS", SIL_QUIRK_MOD15WRITE },
	101	{ "ST3120023AS", SIL_QUIRK_MOD15WRITE },
	102	{ "ST3160023AS", SIL_QUIRK_MOD15WRITE },
	103	{ "ST3120026AS", SIL_QUIRK_MOD15WRITE },
	104	{ "ST3200822AS", SIL_QUIRK_MOD15WRITE },
	105	{ "ST340014ASL", SIL_QUIRK_MOD15WRITE },
	106	{ "ST360014ASL", SIL_QUIRK_MOD15WRITE },
	107	{ "ST380011ASL", SIL_QUIRK_MOD15WRITE },
	108	{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
	109	{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
	110	{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
	111	{ }
	112	};
	113
	114	static struct pci_driver sil_pci_driver = {
	115	.name = DRV_NAME,
	116	.id_table = sil_pci_tbl,
	117	.probe = sil_init_one,
	118	.remove = ata_pci_remove_one,
	119	};
	120
	121	static Scsi_Host_Template sil_sht = {
	122	.module = THIS_MODULE,
	123	.name = DRV_NAME,
	124	.ioctl = ata_scsi_ioctl,
	125	.queuecommand = ata_scsi_queuecmd,
	126	.eh_strategy_handler = ata_scsi_error,
	127	.can_queue = ATA_DEF_QUEUE,
	128	.this_id = ATA_SHT_THIS_ID,
	129	.sg_tablesize = LIBATA_MAX_PRD,
	130	.max_sectors = ATA_MAX_SECTORS,
	131	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	132	.emulated = ATA_SHT_EMULATED,
	133	.use_clustering = ATA_SHT_USE_CLUSTERING,
	134	.proc_name = DRV_NAME,
	135	.dma_boundary = ATA_DMA_BOUNDARY,
	136	.slave_configure = ata_scsi_slave_config,
	137	.bios_param = ata_std_bios_param,
	138	.ordered_flush = 1,
	139	};
	140
	141	static struct ata_port_operations sil_ops = {
	142	.port_disable = ata_port_disable,
	143	.dev_config = sil_dev_config,
	144	.tf_load = ata_tf_load,
	145	.tf_read = ata_tf_read,
	146	.check_status = ata_check_status,
	147	.exec_command = ata_exec_command,
	148	.dev_select = ata_std_dev_select,
	149	.phy_reset = sata_phy_reset,
150	.post_set_mode = sil_post_set_mode,
151	.bmdma_setup = ata_bmdma_setup,
152	.bmdma_start = ata_bmdma_start,
153	.bmdma_stop = ata_bmdma_stop,
154	.bmdma_status = ata_bmdma_status,
155	.qc_prep = ata_qc_prep,
156	.qc_issue = ata_qc_issue_prot,
157	.eng_timeout = ata_eng_timeout,
158	.irq_handler = ata_interrupt,
159	.irq_clear = ata_bmdma_irq_clear,
160	.scr_read = sil_scr_read,
161	.scr_write = sil_scr_write,
162	.port_start = ata_port_start,
163	.port_stop = ata_port_stop,
164	};
165
166	static struct ata_port_info sil_port_info[] = {
167	/* sil_3112 */
168	{
169	.sht = &sil_sht,
170	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
171	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
172	.pio_mask = 0x1f, /* pio0-4 */
173	.mwdma_mask = 0x07, /* mwdma0-2 */
174	.udma_mask = 0x3f, /* udma0-5 */
175	.port_ops = &sil_ops,
176	}, /* sil_3114 */
177	{
178	.sht = &sil_sht,
179	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
180	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
181	.pio_mask = 0x1f, /* pio0-4 */
182	.mwdma_mask = 0x07, /* mwdma0-2 */
183	.udma_mask = 0x3f, /* udma0-5 */
184	.port_ops = &sil_ops,
185	},
186	};
187
188	/* per-port register offsets */
189	/* TODO: we can probably calculate rather than use a table */
190	static const struct {
191	unsigned long tf; /* ATA taskfile register block */
192	unsigned long ctl; /* ATA control/altstatus register block */
193	unsigned long bmdma; /* DMA register block */
194	unsigned long scr; /* SATA control register block */
195	unsigned long sien; /* SATA Interrupt Enable register */
196	unsigned long xfer_mode;/* data transfer mode register */
197	} sil_port[] = {
198	/* port 0 ... */
199	{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
200	{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
201	{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
202	{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
203	/* ... port 3 */
204	};
205
206	MODULE_AUTHOR("Jeff Garzik");
207	MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
208	MODULE_LICENSE("GPL");
209	MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
210	MODULE_VERSION(DRV_VERSION);
211
212	static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
213	{
214	u8 cache_line = 0;
215	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
216	return cache_line;
217	}
218
219	static void sil_post_set_mode (struct ata_port *ap)
220	{
221	struct ata_host_set *host_set = ap->host_set;
222	struct ata_device *dev;
223	void *addr = host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
224	u32 tmp, dev_mode[2];
225	unsigned int i;
226
227	for (i = 0; i < 2; i++) {
228	dev = &ap->device[i];
229	if (!ata_dev_present(dev))
230	dev_mode[i] = 0; /* PIO0/1/2 */
231	else if (dev->flags & ATA_DFLAG_PIO)
232	dev_mode[i] = 1; /* PIO3/4 */
233	else
234	dev_mode[i] = 3; /* UDMA */
235	/* value 2 indicates MDMA */
236	}
237
238	tmp = readl(addr);
239	tmp &= ~((1<<5) \| (1<<4) \| (1<<1) \| (1<<0));
240	tmp \|= dev_mode[0];
241	tmp \|= (dev_mode[1] << 4);
242	writel(tmp, addr);
243	readl(addr); /* flush */
244	}
245
246	static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
247	{
248	unsigned long offset = ap->ioaddr.scr_addr;
249
250	switch (sc_reg) {
251	case SCR_STATUS:
252	return offset + 4;
253	case SCR_ERROR:
254	return offset + 8;
255	case SCR_CONTROL:
256	return offset;
257	default:
258	/* do nothing */
259	break;
260	}
261
262	return 0;
263	}
264
265	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
266	{
267	void mmio = (void ) sil_scr_addr(ap, sc_reg);
268	if (mmio)
269	return readl(mmio);
270	return 0xffffffffU;
271	}
272
273	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
274	{
275	void mmio = (void ) sil_scr_addr(ap, sc_reg);
276	if (mmio)
277	writel(val, mmio);
278	}
279
280	/**
281	* sil_dev_config - Apply device/host-specific errata fixups
282	* @ap: Port containing device to be examined
283	* @dev: Device to be examined
284	*
285	* After the IDENTIFY [PACKET] DEVICE step is complete, and a
286	* device is known to be present, this function is called.
287	* We apply two errata fixups which are specific to Silicon Image,
288	* a Seagate and a Maxtor fixup.
289	*
290	* For certain Seagate devices, we must limit the maximum sectors
291	* to under 8K.
292	*
293	* For certain Maxtor devices, we must not program the drive
294	* beyond udma5.
295	*
296	* Both fixups are unfairly pessimistic. As soon as I get more
297	* information on these errata, I will create a more exhaustive
298	* list, and apply the fixups to only the specific
299	* devices/hosts/firmwares that need it.
300	*
301	* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
302	* The Maxtor quirk is in the blacklist, but I'm keeping the original
303	* pessimistic fix for the following reasons...
304	* - There seems to be less info on it, only one device gleaned off the
305	* Windows driver, maybe only one is affected. More info would be greatly
306	* appreciated.
307	* - But then again UDMA5 is hardly anything to complain about
308	*/
309	static void sil_dev_config(struct ata_port ap, struct ata_device dev)
310	{
311	unsigned int n, quirks = 0;
312	unsigned char model_num[40];
313	const char *s;
314	unsigned int len;
315
316	ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
317	sizeof(model_num));
318	s = &model_num[0];
319	len = strnlen(s, sizeof(model_num));
320
321	/* ATAPI specifies that empty space is blank-filled; remove blanks */
322	while ((len > 0) && (s[len - 1] == ' '))
323	len--;
324
325	for (n = 0; sil_blacklist[n].product; n++)
326	if (!memcmp(sil_blacklist[n].product, s,
327	strlen(sil_blacklist[n].product))) {
328	quirks = sil_blacklist[n].quirk;
329	break;
330	}
331
332	/* limit requests to 15 sectors */
333	if (quirks & SIL_QUIRK_MOD15WRITE) {
334	printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
335	ap->id, dev->devno);
336	ap->host->max_sectors = 15;
337	ap->host->hostt->max_sectors = 15;
338	dev->flags \|= ATA_DFLAG_LOCK_SECTORS;
339	return;
340	}
341
342	/* limit to udma5 */
343	if (quirks & SIL_QUIRK_UDMA5MAX) {
344	printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
345	ap->id, dev->devno, s);
346	ap->udma_mask &= ATA_UDMA5;
347	return;
348	}
349	}
350
351	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent)
352	{
353	static int printed_version;
354	struct ata_probe_ent *probe_ent = NULL;
355	unsigned long base;
356	void *mmio_base;
357	int rc;
358	unsigned int i;
359	int pci_dev_busy = 0;
360	u32 tmp, irq_mask;
361	u8 cls;
362
363	if (!printed_version++)
364	printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
365
366	/*
367	* If this driver happens to only be useful on Apple's K2, then
368	* we should check that here as it has a normal Serverworks ID
369	*/
370	rc = pci_enable_device(pdev);
371	if (rc)
372	return rc;
373
374	rc = pci_request_regions(pdev, DRV_NAME);
375	if (rc) {
376	pci_dev_busy = 1;
377	goto err_out;
378	}
379
380	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
381	if (rc)
382	goto err_out_regions;
383	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
384	if (rc)
385	goto err_out_regions;
386
387	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
388	if (probe_ent == NULL) {
389	rc = -ENOMEM;
390	goto err_out_regions;
391	}
392
393	memset(probe_ent, 0, sizeof(*probe_ent));
394	INIT_LIST_HEAD(&probe_ent->node);
395	probe_ent->dev = pci_dev_to_dev(pdev);
396	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
397	probe_ent->sht = sil_port_info[ent->driver_data].sht;
398	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
399	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
400	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
401	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
402	probe_ent->irq = pdev->irq;
403	probe_ent->irq_flags = SA_SHIRQ;
404	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
405
406	mmio_base = ioremap(pci_resource_start(pdev, 5),
407	pci_resource_len(pdev, 5));
408	if (mmio_base == NULL) {
409	rc = -ENOMEM;
410	goto err_out_free_ent;
411	}
412
413	probe_ent->mmio_base = mmio_base;
414
415	base = (unsigned long) mmio_base;
416
417	for (i = 0; i < probe_ent->n_ports; i++) {
418	probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
419	probe_ent->port[i].altstatus_addr =
420	probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
421	probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
422	probe_ent->port[i].scr_addr = base + sil_port[i].scr;
423	ata_std_ports(&probe_ent->port[i]);
424	}
425
426	/* Initialize FIFO PCI bus arbitration */
427	cls = sil_get_device_cache_line(pdev);
428	if (cls) {
429	cls >>= 3;
430	cls++; /* cls = (line_size/8)+1 */
431	writeb(cls, mmio_base + SIL_FIFO_R0);
432	writeb(cls, mmio_base + SIL_FIFO_W0);
433	writeb(cls, mmio_base + SIL_FIFO_R1);
434	writeb(cls, mmio_base + SIL_FIFO_W2);
435	} else
436	printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n",
437	pci_name(pdev));
438
439	if (ent->driver_data == sil_3114) {
440	irq_mask = SIL_MASK_4PORT;
441
442	/* flip the magic "make 4 ports work" bit */
443	tmp = readl(mmio_base + SIL_IDE2_BMDMA);
444	if ((tmp & SIL_INTR_STEERING) == 0)
445	writel(tmp \| SIL_INTR_STEERING,
446	mmio_base + SIL_IDE2_BMDMA);
447
448	} else {
449	irq_mask = SIL_MASK_2PORT;
450	}
451
452	/* make sure IDE0/1/2/3 interrupts are not masked */
453	tmp = readl(mmio_base + SIL_SYSCFG);
454	if (tmp & irq_mask) {
455	tmp &= ~irq_mask;
456	writel(tmp, mmio_base + SIL_SYSCFG);
457	readl(mmio_base + SIL_SYSCFG); /* flush */
458	}
459
460	/* mask all SATA phy-related interrupts */
461	/* TODO: unmask bit 6 (SError N bit) for hotplug */
462	for (i = 0; i < probe_ent->n_ports; i++)
463	writel(0, mmio_base + sil_port[i].sien);
464
465	pci_set_master(pdev);
466
467	/* FIXME: check ata_device_add return value */
468	ata_device_add(probe_ent);
469	kfree(probe_ent);
470
471	return 0;
472
473	err_out_free_ent:
474	kfree(probe_ent);
475	err_out_regions:
476	pci_release_regions(pdev);
477	err_out:
478	if (!pci_dev_busy)
479	pci_disable_device(pdev);
480	return rc;
481	}
482
483	static int __init sil_init(void)
484	{
485	return pci_module_init(&sil_pci_driver);
486	}
487
488	static void __exit sil_exit(void)
489	{
490	pci_unregister_driver(&sil_pci_driver);
491	}
492
493
494	module_init(sil_init);
495	module_exit(sil_exit);