[deliverable/linux.git] / drivers / scsi / sata_vsc.c

/*
 *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
 *
 *  Maintained by:  Jeremy Higdon @ SGI
 * 		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 SGI
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Vitesse hardware documentation presumably available under NDA.
 *  Intel 31244 (same hardware interface) documentation presumably
 *  available from http://developer.intel.com/
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_vsc"
#define DRV_VERSION	"1.0"

/* Interrupt register offsets (from chip base address) */
#define VSC_SATA_INT_STAT_OFFSET	0x00
#define VSC_SATA_INT_MASK_OFFSET	0x04

/* Taskfile registers offsets */
#define VSC_SATA_TF_CMD_OFFSET		0x00
#define VSC_SATA_TF_DATA_OFFSET		0x00
#define VSC_SATA_TF_ERROR_OFFSET	0x04
#define VSC_SATA_TF_FEATURE_OFFSET	0x06
#define VSC_SATA_TF_NSECT_OFFSET	0x08
#define VSC_SATA_TF_LBAL_OFFSET		0x0c
#define VSC_SATA_TF_LBAM_OFFSET		0x10
#define VSC_SATA_TF_LBAH_OFFSET		0x14
#define VSC_SATA_TF_DEVICE_OFFSET	0x18
#define VSC_SATA_TF_STATUS_OFFSET	0x1c
#define VSC_SATA_TF_COMMAND_OFFSET	0x1d
#define VSC_SATA_TF_ALTSTATUS_OFFSET	0x28
#define VSC_SATA_TF_CTL_OFFSET		0x29

/* DMA base */
#define VSC_SATA_UP_DESCRIPTOR_OFFSET	0x64
#define VSC_SATA_UP_DATA_BUFFER_OFFSET	0x6C
#define VSC_SATA_DMA_CMD_OFFSET		0x70

/* SCRs base */
#define VSC_SATA_SCR_STATUS_OFFSET	0x100
#define VSC_SATA_SCR_ERROR_OFFSET	0x104
#define VSC_SATA_SCR_CONTROL_OFFSET	0x108

/* Port stride */
#define VSC_SATA_PORT_OFFSET		0x200


static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;
	return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
			       u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;
	writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
{
	unsigned long mask_addr;
	u8 mask;

	mask_addr = (unsigned long) ap->host_set->mmio_base +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	mask = readb(mask_addr);
	if (ctl & ATA_NIEN)
		mask |= 0x80;
	else
		mask &= 0x7F;
	writeb(mask, mask_addr);
}


static void vsc_sata_tf_load(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	/*
	 * The only thing the ctl register is used for is SRST.
	 * That is not enabled or disabled via tf_load.
	 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
	 */
	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
		ap->last_ctl = tf->ctl;
		vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah;

	nsect = tf->nsect = readw(ioaddr->nsect_addr);
	lbal = tf->lbal = readw(ioaddr->lbal_addr);
	lbam = tf->lbam = readw(ioaddr->lbam_addr);
	lbah = tf->lbah = readw(ioaddr->lbah_addr);
	tf->device = readw(ioaddr->device_addr);

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = readb(ioaddr->error_addr);
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
        }
}


/*
 * vsc_sata_interrupt
 *
 * Read the interrupt register and process for the devices that have them pending.
 */
static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
				       struct pt_regs *regs)
{
	struct ata_host_set *host_set = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	u32 int_status;

	spin_lock(&host_set->lock);

	int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);

	for (i = 0; i < host_set->n_ports; i++) {
		if (int_status & ((u32) 0xFF << (8 * i))) {
			struct ata_port *ap;

			ap = host_set->ports[i];
			if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
				struct ata_queued_cmd *qc;

				qc = ata_qc_from_tag(ap, ap->active_tag);
				if (qc && (!(qc->tf.ctl & ATA_NIEN)))
					handled += ata_host_intr(ap, qc);
			}
		}
	}

	spin_unlock(&host_set->lock);

	return IRQ_RETVAL(handled);
}


static Scsi_Host_Template vsc_sata_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
	.ordered_flush		= 1,
};


static struct ata_port_operations vsc_sata_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= vsc_sata_tf_load,
	.tf_read		= vsc_sata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= vsc_sata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= vsc_sata_scr_read,
	.scr_write		= vsc_sata_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_host_stop,
};

static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
{
	port->cmd_addr		= base + VSC_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + VSC_SATA_TF_DATA_OFFSET;
	port->error_addr	= base + VSC_SATA_TF_ERROR_OFFSET;
	port->feature_addr	= base + VSC_SATA_TF_FEATURE_OFFSET;
	port->nsect_addr	= base + VSC_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + VSC_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + VSC_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + VSC_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + VSC_SATA_TF_DEVICE_OFFSET;
	port->status_addr	= base + VSC_SATA_TF_STATUS_OFFSET;
	port->command_addr	= base + VSC_SATA_TF_COMMAND_OFFSET;
	port->altstatus_addr	= base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	port->ctl_addr		= base + VSC_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + VSC_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + VSC_SATA_SCR_STATUS_OFFSET;
	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
}


static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	int pci_dev_busy = 0;
	void *mmio_base;
	int rc;

	if (!printed_version++)
		printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");

	rc = pci_enable_device(pdev);
	if (rc)
		return rc;

	/*
	 * Check if we have needed resource mapped.
	 */
	if (pci_resource_len(pdev, 0) == 0) {
		rc = -ENODEV;
		goto err_out;
	}

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	/*
	 * Use 32 bit DMA mask, because 64 bit address support is poor.
	 */
	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}
	memset(probe_ent, 0, sizeof(*probe_ent));
	probe_ent->dev = pci_dev_to_dev(pdev);
	INIT_LIST_HEAD(&probe_ent->node);

	mmio_base = ioremap(pci_resource_start(pdev, 0),
		            pci_resource_len(pdev, 0));
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}
	base = (unsigned long) mmio_base;

	/*
	 * Due to a bug in the chip, the default cache line size can't be used
	 */
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);

	probe_ent->sht = &vsc_sata_sht;
	probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
	probe_ent->port_ops = &vsc_sata_ops;
	probe_ent->n_ports = 4;
	probe_ent->irq = pdev->irq;
	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->mmio_base = mmio_base;

	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	 * if we don't fill these
	 */
	probe_ent->pio_mask = 0x1f;
	probe_ent->mwdma_mask = 0x07;
	probe_ent->udma_mask = 0x7f;

	/* We have 4 ports per PCI function */
	vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
	vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
	vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
	vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);

	pci_set_master(pdev);

	/* 
	 * Config offset 0x98 is "Extended Control and Status Register 0"
	 * Default value is (1 << 28).  All bits except bit 28 are reserved in
	 * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
	 * If bit 28 is clear, each port has its own LED.
	 */
	pci_write_config_dword(pdev, 0x98, 0);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}


/*
 * 0x1725/0x7174 is the Vitesse VSC-7174
 * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
 * compatibility is untested as of yet
 */
static struct pci_device_id vsc_sata_pci_tbl[] = {
	{ 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
	{ 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
	{ }
};


static struct pci_driver vsc_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= vsc_sata_pci_tbl,
	.probe			= vsc_sata_init_one,
	.remove			= ata_pci_remove_one,
};


static int __init vsc_sata_init(void)
{
	return pci_module_init(&vsc_sata_pci_driver);
}


static void __exit vsc_sata_exit(void)
{
	pci_unregister_driver(&vsc_sata_pci_driver);
}


MODULE_AUTHOR("Jeremy Higdon");
MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(vsc_sata_init);
module_exit(vsc_sata_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
	3	*
	4	* Maintained by: Jeremy Higdon @ SGI
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 SGI
	9	*
	10	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	11	*
af36d7f0 JG	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2, or (at your option)
	16	* any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; see the file COPYING. If not, write to
	25	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*
	27	*
	28	* libata documentation is available via 'make {ps\|pdf}docs',
	29	* as Documentation/DocBook/libata.*
	30	*
	31	* Vitesse hardware documentation presumably available under NDA.
	32	* Intel 31244 (same hardware interface) documentation presumably
	33	* available from http://developer.intel.com/
	34	*
1da177e4 LT	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
	40	#include <linux/init.h>
	41	#include <linux/blkdev.h>
	42	#include <linux/delay.h>
	43	#include <linux/interrupt.h>
7003c05d	44	#include <linux/dma-mapping.h>
1da177e4 LT	45	#include "scsi.h"
	46	#include <scsi/scsi_host.h>
	47	#include <linux/libata.h>
	48
	49	#define DRV_NAME "sata_vsc"
	50	#define DRV_VERSION "1.0"
	51
	52	/* Interrupt register offsets (from chip base address) */
	53	#define VSC_SATA_INT_STAT_OFFSET 0x00
	54	#define VSC_SATA_INT_MASK_OFFSET 0x04
	55
	56	/* Taskfile registers offsets */
	57	#define VSC_SATA_TF_CMD_OFFSET 0x00
	58	#define VSC_SATA_TF_DATA_OFFSET 0x00
	59	#define VSC_SATA_TF_ERROR_OFFSET 0x04
	60	#define VSC_SATA_TF_FEATURE_OFFSET 0x06
	61	#define VSC_SATA_TF_NSECT_OFFSET 0x08
	62	#define VSC_SATA_TF_LBAL_OFFSET 0x0c
	63	#define VSC_SATA_TF_LBAM_OFFSET 0x10
	64	#define VSC_SATA_TF_LBAH_OFFSET 0x14
	65	#define VSC_SATA_TF_DEVICE_OFFSET 0x18
	66	#define VSC_SATA_TF_STATUS_OFFSET 0x1c
	67	#define VSC_SATA_TF_COMMAND_OFFSET 0x1d
	68	#define VSC_SATA_TF_ALTSTATUS_OFFSET 0x28
	69	#define VSC_SATA_TF_CTL_OFFSET 0x29
	70
	71	/* DMA base */
	72	#define VSC_SATA_UP_DESCRIPTOR_OFFSET 0x64
	73	#define VSC_SATA_UP_DATA_BUFFER_OFFSET 0x6C
	74	#define VSC_SATA_DMA_CMD_OFFSET 0x70
	75
	76	/* SCRs base */
	77	#define VSC_SATA_SCR_STATUS_OFFSET 0x100
	78	#define VSC_SATA_SCR_ERROR_OFFSET 0x104
	79	#define VSC_SATA_SCR_CONTROL_OFFSET 0x108
	80
	81	/* Port stride */
	82	#define VSC_SATA_PORT_OFFSET 0x200
	83
	84
	85	static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
	86	{
	87	if (sc_reg > SCR_CONTROL)
	88	return 0xffffffffU;
	89	return readl((void ) ap->ioaddr.scr_addr + (sc_reg 4));
	90	}
	91
	92
	93	static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
	94	u32 val)
	95	{
	96	if (sc_reg > SCR_CONTROL)
	97	return;
	98	writel(val, (void ) ap->ioaddr.scr_addr + (sc_reg 4));
	99	}
	100
	101
	102	static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
	103	{
	104	unsigned long mask_addr;
	105	u8 mask;
	106
	107	mask_addr = (unsigned long) ap->host_set->mmio_base +
	108	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
109	mask = readb(mask_addr);
110	if (ctl & ATA_NIEN)
111	mask \|= 0x80;
112	else
113	mask &= 0x7F;
114	writeb(mask, mask_addr);
115	}
116
117
118	static void vsc_sata_tf_load(struct ata_port ap, struct ata_taskfile tf)
119	{
120	struct ata_ioports *ioaddr = &ap->ioaddr;
121	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
122
123	/*
124	* The only thing the ctl register is used for is SRST.
125	* That is not enabled or disabled via tf_load.
126	* However, if ATA_NIEN is changed, then we need to change the interrupt register.
127	*/
128	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
129	ap->last_ctl = tf->ctl;
130	vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
131	}
132	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
133	writew(tf->feature \| (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
134	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
135	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
136	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
137	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
138	} else if (is_addr) {
139	writew(tf->feature, ioaddr->feature_addr);
140	writew(tf->nsect, ioaddr->nsect_addr);
141	writew(tf->lbal, ioaddr->lbal_addr);
142	writew(tf->lbam, ioaddr->lbam_addr);
143	writew(tf->lbah, ioaddr->lbah_addr);
144	}
145
146	if (tf->flags & ATA_TFLAG_DEVICE)
147	writeb(tf->device, ioaddr->device_addr);
148
149	ata_wait_idle(ap);
150	}
151
152
153	static void vsc_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
154	{
155	struct ata_ioports *ioaddr = &ap->ioaddr;
156	u16 nsect, lbal, lbam, lbah;
157
158	nsect = tf->nsect = readw(ioaddr->nsect_addr);
159	lbal = tf->lbal = readw(ioaddr->lbal_addr);
160	lbam = tf->lbam = readw(ioaddr->lbam_addr);
161	lbah = tf->lbah = readw(ioaddr->lbah_addr);
162	tf->device = readw(ioaddr->device_addr);
163
164	if (tf->flags & ATA_TFLAG_LBA48) {
165	tf->hob_feature = readb(ioaddr->error_addr);
166	tf->hob_nsect = nsect >> 8;
167	tf->hob_lbal = lbal >> 8;
168	tf->hob_lbam = lbam >> 8;
169	tf->hob_lbah = lbah >> 8;
170	}
171	}
172
173
174	/*
175	* vsc_sata_interrupt
176	*
177	* Read the interrupt register and process for the devices that have them pending.
178	*/
179	static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
180	struct pt_regs *regs)
181	{
182	struct ata_host_set *host_set = dev_instance;
183	unsigned int i;
184	unsigned int handled = 0;
185	u32 int_status;
186
187	spin_lock(&host_set->lock);
188
189	int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
190
191	for (i = 0; i < host_set->n_ports; i++) {
192	if (int_status & ((u32) 0xFF << (8 * i))) {
193	struct ata_port *ap;
194
195	ap = host_set->ports[i];
196	if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
197	struct ata_queued_cmd *qc;
198
199	qc = ata_qc_from_tag(ap, ap->active_tag);
200	if (qc && (!(qc->tf.ctl & ATA_NIEN)))
201	handled += ata_host_intr(ap, qc);
202	}
203	}
204	}
205
206	spin_unlock(&host_set->lock);
207
208	return IRQ_RETVAL(handled);
209	}
210
211
212	static Scsi_Host_Template vsc_sata_sht = {
213	.module = THIS_MODULE,
214	.name = DRV_NAME,
215	.ioctl = ata_scsi_ioctl,
216	.queuecommand = ata_scsi_queuecmd,
217	.eh_strategy_handler = ata_scsi_error,
218	.can_queue = ATA_DEF_QUEUE,
219	.this_id = ATA_SHT_THIS_ID,
220	.sg_tablesize = LIBATA_MAX_PRD,
221	.max_sectors = ATA_MAX_SECTORS,
222	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
223	.emulated = ATA_SHT_EMULATED,
224	.use_clustering = ATA_SHT_USE_CLUSTERING,
225	.proc_name = DRV_NAME,
226	.dma_boundary = ATA_DMA_BOUNDARY,
227	.slave_configure = ata_scsi_slave_config,
228	.bios_param = ata_std_bios_param,
229	.ordered_flush = 1,
230	};
231
232
233	static struct ata_port_operations vsc_sata_ops = {
234	.port_disable = ata_port_disable,
235	.tf_load = vsc_sata_tf_load,
236	.tf_read = vsc_sata_tf_read,
237	.exec_command = ata_exec_command,
238	.check_status = ata_check_status,
239	.dev_select = ata_std_dev_select,
240	.phy_reset = sata_phy_reset,
241	.bmdma_setup = ata_bmdma_setup,
242	.bmdma_start = ata_bmdma_start,
243	.bmdma_stop = ata_bmdma_stop,
244	.bmdma_status = ata_bmdma_status,
245	.qc_prep = ata_qc_prep,
246	.qc_issue = ata_qc_issue_prot,
247	.eng_timeout = ata_eng_timeout,
248	.irq_handler = vsc_sata_interrupt,
249	.irq_clear = ata_bmdma_irq_clear,
250	.scr_read = vsc_sata_scr_read,
251	.scr_write = vsc_sata_scr_write,
252	.port_start = ata_port_start,
253	.port_stop = ata_port_stop,
aa8f0dc6	254	.host_stop = ata_host_stop,
1da177e4 LT	255	};
	256
	257	static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
	258	{
	259	port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
	260	port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
	261	port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
	262	port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
	263	port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
	264	port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
	265	port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
	266	port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
	267	port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
	268	port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
	269	port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
	270	port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	271	port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
	272	port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
	273	port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
	274	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
	275	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
	276	}
	277
	278
	279	static int __devinit vsc_sata_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	280	{
	281	static int printed_version;
	282	struct ata_probe_ent *probe_ent = NULL;
	283	unsigned long base;
	284	int pci_dev_busy = 0;
	285	void *mmio_base;
	286	int rc;
	287
	288	if (!printed_version++)
	289	printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
	290
	291	rc = pci_enable_device(pdev);
	292	if (rc)
	293	return rc;
	294
	295	/*
	296	* Check if we have needed resource mapped.
	297	*/
	298	if (pci_resource_len(pdev, 0) == 0) {
	299	rc = -ENODEV;
	300	goto err_out;
	301	}
	302
	303	rc = pci_request_regions(pdev, DRV_NAME);
	304	if (rc) {
	305	pci_dev_busy = 1;
	306	goto err_out;
	307	}
	308
	309	/*
	310	* Use 32 bit DMA mask, because 64 bit address support is poor.
	311	*/
	312	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
	313	if (rc)
	314	goto err_out_regions;
	315	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
	316	if (rc)
	317	goto err_out_regions;
	318
319	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
320	if (probe_ent == NULL) {
321	rc = -ENOMEM;
322	goto err_out_regions;
323	}
324	memset(probe_ent, 0, sizeof(*probe_ent));
325	probe_ent->dev = pci_dev_to_dev(pdev);
326	INIT_LIST_HEAD(&probe_ent->node);
327
328	mmio_base = ioremap(pci_resource_start(pdev, 0),
329	pci_resource_len(pdev, 0));
330	if (mmio_base == NULL) {
331	rc = -ENOMEM;
332	goto err_out_free_ent;
333	}
334	base = (unsigned long) mmio_base;
335
336	/*
337	* Due to a bug in the chip, the default cache line size can't be used
338	*/
339	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
340
341	probe_ent->sht = &vsc_sata_sht;
342	probe_ent->host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
343	ATA_FLAG_MMIO \| ATA_FLAG_SATA_RESET;
344	probe_ent->port_ops = &vsc_sata_ops;
345	probe_ent->n_ports = 4;
346	probe_ent->irq = pdev->irq;
347	probe_ent->irq_flags = SA_SHIRQ;
348	probe_ent->mmio_base = mmio_base;
349
350	/* We don't care much about the PIO/UDMA masks, but the core won't like us
351	* if we don't fill these
352	*/
353	probe_ent->pio_mask = 0x1f;
354	probe_ent->mwdma_mask = 0x07;
355	probe_ent->udma_mask = 0x7f;
356
357	/* We have 4 ports per PCI function */
358	vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
359	vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
360	vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
361	vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
362
363	pci_set_master(pdev);
364
365	/*
366	* Config offset 0x98 is "Extended Control and Status Register 0"
367	* Default value is (1 << 28). All bits except bit 28 are reserved in
368	* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
369	* If bit 28 is clear, each port has its own LED.
370	*/
371	pci_write_config_dword(pdev, 0x98, 0);
372
373	/* FIXME: check ata_device_add return value */
374	ata_device_add(probe_ent);
375	kfree(probe_ent);
376
377	return 0;
378
379	err_out_free_ent:
380	kfree(probe_ent);
381	err_out_regions:
382	pci_release_regions(pdev);
383	err_out:
384	if (!pci_dev_busy)
385	pci_disable_device(pdev);
386	return rc;
387	}
388
389
390	/*
391	* 0x1725/0x7174 is the Vitesse VSC-7174
392	* 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
393	* compatibility is untested as of yet
394	*/
395	static struct pci_device_id vsc_sata_pci_tbl[] = {
396	{ 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
397	{ 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
398	{ }
399	};
400
401
402	static struct pci_driver vsc_sata_pci_driver = {
403	.name = DRV_NAME,
404	.id_table = vsc_sata_pci_tbl,
405	.probe = vsc_sata_init_one,
406	.remove = ata_pci_remove_one,
407	};
408
409
410	static int __init vsc_sata_init(void)
411	{
412	return pci_module_init(&vsc_sata_pci_driver);
413	}
414
415
416	static void __exit vsc_sata_exit(void)
417	{
418	pci_unregister_driver(&vsc_sata_pci_driver);
419	}
420
421
422	MODULE_AUTHOR("Jeremy Higdon");
423	MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
424	MODULE_LICENSE("GPL");
425	MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
426	MODULE_VERSION(DRV_VERSION);
427
428	module_init(vsc_sata_init);
429	module_exit(vsc_sata_exit);