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1da177e4 LT |
1 | /* |
2 | * Trantor T128/T128F/T228 defines | |
3 | * Note : architecturally, the T100 and T128 are different and won't work | |
4 | * | |
5 | * Copyright 1993, Drew Eckhardt | |
6 | * Visionary Computing | |
7 | * (Unix and Linux consulting and custom programming) | |
8 | * drew@colorado.edu | |
9 | * +1 (303) 440-4894 | |
10 | * | |
667c667f | 11 | * DISTRIBUTION RELEASE 3. |
1da177e4 | 12 | * |
667c667f | 13 | * For more information, please consult |
1da177e4 LT |
14 | * |
15 | * Trantor Systems, Ltd. | |
16 | * T128/T128F/T228 SCSI Host Adapter | |
17 | * Hardware Specifications | |
667c667f H |
18 | * |
19 | * Trantor Systems, Ltd. | |
1da177e4 LT |
20 | * 5415 Randall Place |
21 | * Fremont, CA 94538 | |
22 | * 1+ (415) 770-1400, FAX 1+ (415) 770-9910 | |
667c667f H |
23 | * |
24 | * and | |
1da177e4 LT |
25 | * |
26 | * NCR 5380 Family | |
27 | * SCSI Protocol Controller | |
28 | * Databook | |
29 | * | |
30 | * NCR Microelectronics | |
31 | * 1635 Aeroplaza Drive | |
32 | * Colorado Springs, CO 80916 | |
33 | * 1+ (719) 578-3400 | |
34 | * 1+ (800) 334-5454 | |
35 | */ | |
36 | ||
1da177e4 LT |
37 | #ifndef T128_H |
38 | #define T128_H | |
39 | ||
40 | #define T128_PUBLIC_RELEASE 3 | |
41 | ||
44456d37 | 42 | #define TDEBUG 0 |
1da177e4 LT |
43 | #define TDEBUG_INIT 0x1 |
44 | #define TDEBUG_TRANSFER 0x2 | |
45 | ||
46 | /* | |
667c667f | 47 | * The trantor boards are memory mapped. They use an NCR5380 or |
1da177e4 | 48 | * equivalent (my sample board had part second sourced from ZILOG). |
667c667f | 49 | * NCR's recommended "Pseudo-DMA" architecture is used, where |
1da177e4 | 50 | * a PAL drives the DMA signals on the 5380 allowing fast, blind |
667c667f | 51 | * transfers with proper handshaking. |
1da177e4 LT |
52 | */ |
53 | ||
54 | /* | |
667c667f | 55 | * Note : a boot switch is provided for the purpose of informing the |
1da177e4 LT |
56 | * firmware to boot or not boot from attached SCSI devices. So, I imagine |
57 | * there are fewer people who've yanked the ROM like they do on the Seagate | |
58 | * to make bootup faster, and I'll probably use this for autodetection. | |
59 | */ | |
60 | #define T_ROM_OFFSET 0 | |
61 | ||
62 | /* | |
63 | * Note : my sample board *WAS NOT* populated with the SRAM, so this | |
64 | * can't be used for autodetection without a ROM present. | |
65 | */ | |
66 | #define T_RAM_OFFSET 0x1800 | |
67 | ||
68 | /* | |
69 | * All of the registers are allocated 32 bytes of address space, except | |
70 | * for the data register (read/write to/from the 5380 in pseudo-DMA mode) | |
71 | */ | |
72 | #define T_CONTROL_REG_OFFSET 0x1c00 /* rw */ | |
73 | #define T_CR_INT 0x10 /* Enable interrupts */ | |
74 | #define T_CR_CT 0x02 /* Reset watchdog timer */ | |
75 | ||
76 | #define T_STATUS_REG_OFFSET 0x1c20 /* ro */ | |
77 | #define T_ST_BOOT 0x80 /* Boot switch */ | |
78 | #define T_ST_S3 0x40 /* User settable switches, */ | |
79 | #define T_ST_S2 0x20 /* read 0 when switch is on, 1 off */ | |
80 | #define T_ST_S1 0x10 | |
81 | #define T_ST_PS2 0x08 /* Set for Microchannel 228 */ | |
82 | #define T_ST_RDY 0x04 /* 5380 DRQ */ | |
83 | #define T_ST_TIM 0x02 /* indicates 40us watchdog timer fired */ | |
84 | #define T_ST_ZERO 0x01 /* Always zero */ | |
85 | ||
86 | #define T_5380_OFFSET 0x1d00 /* 8 registers here, see NCR5380.h */ | |
87 | ||
88 | #define T_DATA_REG_OFFSET 0x1e00 /* rw 512 bytes long */ | |
89 | ||
90 | #ifndef ASM | |
667c667f | 91 | static int t128_abort(struct scsi_cmnd *); |
1da177e4 LT |
92 | static int t128_biosparam(struct scsi_device *, struct block_device *, |
93 | sector_t, int*); | |
d0be4a7d | 94 | static int t128_detect(struct scsi_host_template *); |
f281233d | 95 | static int t128_queue_command(struct Scsi_Host *, struct scsi_cmnd *); |
667c667f | 96 | static int t128_bus_reset(struct scsi_cmnd *); |
1da177e4 LT |
97 | |
98 | #ifndef CMD_PER_LUN | |
99 | #define CMD_PER_LUN 2 | |
100 | #endif | |
101 | ||
102 | #ifndef CAN_QUEUE | |
667c667f | 103 | #define CAN_QUEUE 32 |
1da177e4 LT |
104 | #endif |
105 | ||
1da177e4 LT |
106 | #define NCR5380_implementation_fields \ |
107 | void __iomem *base | |
108 | ||
109 | #define NCR5380_local_declare() \ | |
110 | void __iomem *base | |
111 | ||
112 | #define NCR5380_setup(instance) \ | |
113 | base = ((struct NCR5380_hostdata *)(instance->hostdata))->base | |
114 | ||
115 | #define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20)) | |
116 | ||
667c667f | 117 | #if !(TDEBUG & TDEBUG_TRANSFER) |
1da177e4 LT |
118 | #define NCR5380_read(reg) readb(T128_address(reg)) |
119 | #define NCR5380_write(reg, value) writeb((value),(T128_address(reg))) | |
120 | #else | |
121 | #define NCR5380_read(reg) \ | |
122 | (((unsigned char) printk("scsi%d : read register %d at address %08x\n"\ | |
123 | , instance->hostno, (reg), T128_address(reg))), readb(T128_address(reg))) | |
124 | ||
125 | #define NCR5380_write(reg, value) { \ | |
667c667f | 126 | printk("scsi%d : write %02x to register %d at address %08x\n", \ |
1da177e4 LT |
127 | instance->hostno, (value), (reg), T128_address(reg)); \ |
128 | writeb((value), (T128_address(reg))); \ | |
129 | } | |
130 | #endif | |
131 | ||
132 | #define NCR5380_intr t128_intr | |
133 | #define do_NCR5380_intr do_t128_intr | |
134 | #define NCR5380_queue_command t128_queue_command | |
135 | #define NCR5380_abort t128_abort | |
1da177e4 | 136 | #define NCR5380_bus_reset t128_bus_reset |
dd7ab71b AV |
137 | #define NCR5380_show_info t128_show_info |
138 | #define NCR5380_write_info t128_write_info | |
1da177e4 | 139 | |
667c667f | 140 | /* 15 14 12 10 7 5 3 |
1da177e4 | 141 | 1101 0100 1010 1000 */ |
667c667f H |
142 | |
143 | #define T128_IRQS 0xc4a8 | |
1da177e4 | 144 | |
1da177e4 LT |
145 | #endif /* ndef ASM */ |
146 | #endif /* T128_H */ |