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Merge remote-tracking branch 'scsi/for-next'
[deliverable/linux.git] / drivers / scsi / ufs / tc-dwc-g210.c
CommitLineData
947e7013
JP		 1/*
2 * Synopsys G210 Test Chip driver
3 *
4 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
5 *
6 * Authors: Joao Pinto <jpinto@synopsys.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include "ufshcd.h"
14#include "unipro.h"
15
16#include "ufshcd-dwc.h"
17#include "ufshci-dwc.h"
15177052 18#include "tc-dwc-g210.h"
947e7013
JP		 19
20/**
21 * tc_dwc_g210_setup_40bit_rmmi()
22 * This function configures Synopsys TC specific atributes (40-bit RMMI)
23 * @hba: Pointer to drivers structure
24 *
25 * Returns 0 on success or non-zero value on failure
26 */
27static int tc_dwc_g210_setup_40bit_rmmi(struct ufs_hba *hba)
28{
29 const struct ufshcd_dme_attr_val setup_attrs[] = {
30 { UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },
31 { UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },
32 { UIC_ARG_MIB(CDIRECTCTRL6), 0x80, DME_LOCAL },
33 { UIC_ARG_MIB(CBDIVFACTOR), 0x08, DME_LOCAL },
34 { UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },
35 { UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },
36 { UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },
37 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,
38 DME_LOCAL },
39 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,
40 DME_LOCAL },
41 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14,
42 DME_LOCAL },
43 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
44 DME_LOCAL },
45 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,
46 DME_LOCAL },
47 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,
48 DME_LOCAL },
49 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4,
50 DME_LOCAL },
51 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
52 DME_LOCAL },
53 { UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },
54 { UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },
55 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
56 DME_LOCAL },
57 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,
58 DME_LOCAL },
59 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,
60 DME_LOCAL },
61 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,
62 DME_LOCAL },
63 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,
64 DME_LOCAL },
65 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,
66 DME_LOCAL },
67 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,
68 DME_LOCAL },
69 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,
70 DME_LOCAL },
71 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,
72 DME_LOCAL },
73 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
74 DME_LOCAL },
75 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
76 DME_LOCAL },
77 { UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },
78 };
79
80 return ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
81 ARRAY_SIZE(setup_attrs));
82}
83
84/**
85 * tc_dwc_g210_setup_20bit_rmmi_lane0()
86 * This function configures Synopsys TC 20-bit RMMI Lane 0
87 * @hba: Pointer to drivers structure
88 *
89 * Returns 0 on success or non-zero value on failure
90 */
91static int tc_dwc_g210_setup_20bit_rmmi_lane0(struct ufs_hba *hba)
92{
93 const struct ufshcd_dme_attr_val setup_attrs[] = {
94 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,
95 DME_LOCAL },
96 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,
97 DME_LOCAL },
98 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,
99 DME_LOCAL },
100 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x12,
101 DME_LOCAL },
102 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
103 DME_LOCAL },
104 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,
105 DME_LOCAL },
106 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 2,
107 DME_LOCAL },
108 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
109 DME_LOCAL },
110 { UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },
111 { UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },
112 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,
113 DME_LOCAL },
114 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,
115 DME_LOCAL },
116 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,
117 DME_LOCAL },
118 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,
119 DME_LOCAL },
120 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,
121 DME_LOCAL },
122 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,
123 DME_LOCAL },
124 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,
125 DME_LOCAL },
126 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,
127 DME_LOCAL },
128 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
129 DME_LOCAL },
130 { UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },
131 };
132
133 return ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
134 ARRAY_SIZE(setup_attrs));
135}
136
137/**
138 * tc_dwc_g210_setup_20bit_rmmi_lane1()
139 * This function configures Synopsys TC 20-bit RMMI Lane 1
140 * @hba: Pointer to drivers structure
141 *
142 * Returns 0 on success or non-zero value on failure
143 */
144static int tc_dwc_g210_setup_20bit_rmmi_lane1(struct ufs_hba *hba)
145{
146 int connected_rx_lanes = 0;
147 int connected_tx_lanes = 0;
148 int ret = 0;
149
150 const struct ufshcd_dme_attr_val setup_tx_attrs[] = {
151 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN1_TX), 0x0d,
152 DME_LOCAL },
153 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN1_TX), 0x19,
154 DME_LOCAL },
155 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN1_TX), 0x12,
156 DME_LOCAL },
157 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
158 DME_LOCAL },
159 };
160
161 const struct ufshcd_dme_attr_val setup_rx_attrs[] = {
162 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01,
163 DME_LOCAL },
164 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19,
165 DME_LOCAL },
166 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN1_RX), 2,
167 DME_LOCAL },
168 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80,
169 DME_LOCAL },
170 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03,
171 DME_LOCAL },
172 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16,
173 DME_LOCAL },
174 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42,
175 DME_LOCAL },
176 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4,
177 DME_LOCAL },
178 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01,
179 DME_LOCAL },
180 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01,
181 DME_LOCAL },
182 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28,
183 DME_LOCAL },
184 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E,
185 DME_LOCAL },
186 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f,
187 DME_LOCAL },
188 };
189
190 /* Get the available lane count */
757f9d7a 191 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
947e7013 192 &connected_rx_lanes);
757f9d7a 193 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
947e7013
JP		 194 &connected_tx_lanes);
195
196 if (connected_tx_lanes == 2) {
197
198 ret = ufshcd_dwc_dme_set_attrs(hba, setup_tx_attrs,
199 ARRAY_SIZE(setup_tx_attrs));
200
201 if (ret)
202 goto out;
203 }
204
205 if (connected_rx_lanes == 2) {
206 ret = ufshcd_dwc_dme_set_attrs(hba, setup_rx_attrs,
207 ARRAY_SIZE(setup_rx_attrs));
208 }
209
210out:
211 return ret;
212}
213
214/**
215 * tc_dwc_g210_setup_20bit_rmmi()
216 * This function configures Synopsys TC specific atributes (20-bit RMMI)
217 * @hba: Pointer to drivers structure
218 *
219 * Returns 0 on success or non-zero value on failure
220 */
221static int tc_dwc_g210_setup_20bit_rmmi(struct ufs_hba *hba)
222{
223 int ret = 0;
224
225 const struct ufshcd_dme_attr_val setup_attrs[] = {
226 { UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },
227 { UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },
228 { UIC_ARG_MIB(CDIRECTCTRL6), 0xc0, DME_LOCAL },
229 { UIC_ARG_MIB(CBDIVFACTOR), 0x44, DME_LOCAL },
230 { UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },
231 { UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },
232 { UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },
233 };
234
235 ret = ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
236 ARRAY_SIZE(setup_attrs));
237 if (ret)
238 goto out;
239
240 /* Lane 0 configuration*/
241 ret = tc_dwc_g210_setup_20bit_rmmi_lane0(hba);
242 if (ret)
243 goto out;
244
245 /* Lane 1 configuration*/
246 ret = tc_dwc_g210_setup_20bit_rmmi_lane1(hba);
247 if (ret)
248 goto out;
249
250out:
251 return ret;
252}
253
254/**
255 * tc_dwc_g210_config_40_bit()
256 * This function configures Local (host) Synopsys 40-bit TC specific attributes
257 *
258 * @hba: Pointer to drivers structure
259 *
260 * Returns 0 on success non-zero value on failure
261 */
262int tc_dwc_g210_config_40_bit(struct ufs_hba *hba)
263{
264 int ret = 0;
265
266 dev_info(hba->dev, "Configuring Test Chip 40-bit RMMI\n");
267 ret = tc_dwc_g210_setup_40bit_rmmi(hba);
268 if (ret) {
269 dev_err(hba->dev, "Configuration failed\n");
270 goto out;
271 }
272
273 /* To write Shadow register bank to effective configuration block */
274 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
275 if (ret)
276 goto out;
277
278 /* To configure Debug OMC */
279 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);
280
281out:
282 return ret;
283}
284EXPORT_SYMBOL(tc_dwc_g210_config_40_bit);
285
286/**
287 * tc_dwc_g210_config_20_bit()
288 * This function configures Local (host) Synopsys 20-bit TC specific attributes
289 *
290 * @hba: Pointer to drivers structure
291 *
292 * Returns 0 on success non-zero value on failure
293 */
294int tc_dwc_g210_config_20_bit(struct ufs_hba *hba)
295{
296 int ret = 0;
297
298 dev_info(hba->dev, "Configuring Test Chip 20-bit RMMI\n");
299 ret = tc_dwc_g210_setup_20bit_rmmi(hba);
300 if (ret) {
301 dev_err(hba->dev, "Configuration failed\n");
302 goto out;
303 }
304
305 /* To write Shadow register bank to effective configuration block */
306 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
307 if (ret)
308 goto out;
309
310 /* To configure Debug OMC */
311 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);
312
313out:
314 return ret;
315}
316EXPORT_SYMBOL(tc_dwc_g210_config_20_bit);
87ee3ab9
JP		 317
318MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
319MODULE_DESCRIPTION("Synopsys G210 Test Chip driver");
320MODULE_LICENSE("Dual BSD/GPL");
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