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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/8250.c | |
3 | * | |
4 | * Driver for 8250/16550-type serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright (C) 2001 Russell King. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $ | |
16 | * | |
17 | * A note about mapbase / membase | |
18 | * | |
19 | * mapbase is the physical address of the IO port. | |
20 | * membase is an 'ioremapped' cookie. | |
21 | */ | |
22 | #include <linux/config.h> | |
23 | ||
24 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
25 | #define SUPPORT_SYSRQ | |
26 | #endif | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/moduleparam.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/console.h> | |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/mca.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/device.h> | |
37 | #include <linux/tty.h> | |
38 | #include <linux/tty_flip.h> | |
39 | #include <linux/serial_reg.h> | |
40 | #include <linux/serial_core.h> | |
41 | #include <linux/serial.h> | |
42 | #include <linux/serial_8250.h> | |
43 | ||
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
46 | ||
47 | #include "8250.h" | |
48 | ||
49 | /* | |
50 | * Configuration: | |
51 | * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option | |
52 | * is unsafe when used on edge-triggered interrupts. | |
53 | */ | |
408b664a | 54 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
1da177e4 LT |
55 | |
56 | /* | |
57 | * Debugging. | |
58 | */ | |
59 | #if 0 | |
60 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
61 | #else | |
62 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
63 | #endif | |
64 | ||
65 | #if 0 | |
66 | #define DEBUG_INTR(fmt...) printk(fmt) | |
67 | #else | |
68 | #define DEBUG_INTR(fmt...) do { } while (0) | |
69 | #endif | |
70 | ||
71 | #define PASS_LIMIT 256 | |
72 | ||
73 | /* | |
74 | * We default to IRQ0 for the "no irq" hack. Some | |
75 | * machine types want others as well - they're free | |
76 | * to redefine this in their header file. | |
77 | */ | |
78 | #define is_real_interrupt(irq) ((irq) != 0) | |
79 | ||
1da177e4 LT |
80 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
81 | #define CONFIG_SERIAL_DETECT_IRQ 1 | |
82 | #endif | |
1da177e4 LT |
83 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
84 | #define CONFIG_SERIAL_MANY_PORTS 1 | |
85 | #endif | |
86 | ||
87 | /* | |
88 | * HUB6 is always on. This will be removed once the header | |
89 | * files have been cleaned. | |
90 | */ | |
91 | #define CONFIG_HUB6 1 | |
92 | ||
93 | #include <asm/serial.h> | |
94 | ||
95 | /* | |
96 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
97 | * standard enumeration mechanism. Platforms that can find all | |
98 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
99 | */ | |
100 | #ifndef SERIAL_PORT_DFNS | |
101 | #define SERIAL_PORT_DFNS | |
102 | #endif | |
103 | ||
104 | static struct old_serial_port old_serial_port[] = { | |
105 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ | |
106 | }; | |
107 | ||
026d02a2 | 108 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
1da177e4 LT |
109 | |
110 | #ifdef CONFIG_SERIAL_8250_RSA | |
111 | ||
112 | #define PORT_RSA_MAX 4 | |
113 | static unsigned long probe_rsa[PORT_RSA_MAX]; | |
114 | static unsigned int probe_rsa_count; | |
115 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
116 | ||
117 | struct uart_8250_port { | |
118 | struct uart_port port; | |
119 | struct timer_list timer; /* "no irq" timer */ | |
120 | struct list_head list; /* ports on this IRQ */ | |
4ba5e35d RK |
121 | unsigned short capabilities; /* port capabilities */ |
122 | unsigned short bugs; /* port bugs */ | |
1da177e4 | 123 | unsigned int tx_loadsz; /* transmit fifo load size */ |
1da177e4 LT |
124 | unsigned char acr; |
125 | unsigned char ier; | |
126 | unsigned char lcr; | |
127 | unsigned char mcr; | |
128 | unsigned char mcr_mask; /* mask of user bits */ | |
129 | unsigned char mcr_force; /* mask of forced bits */ | |
130 | unsigned char lsr_break_flag; | |
131 | ||
132 | /* | |
133 | * We provide a per-port pm hook. | |
134 | */ | |
135 | void (*pm)(struct uart_port *port, | |
136 | unsigned int state, unsigned int old); | |
137 | }; | |
138 | ||
139 | struct irq_info { | |
140 | spinlock_t lock; | |
141 | struct list_head *head; | |
142 | }; | |
143 | ||
144 | static struct irq_info irq_lists[NR_IRQS]; | |
145 | ||
146 | /* | |
147 | * Here we define the default xmit fifo size used for each type of UART. | |
148 | */ | |
149 | static const struct serial8250_config uart_config[] = { | |
150 | [PORT_UNKNOWN] = { | |
151 | .name = "unknown", | |
152 | .fifo_size = 1, | |
153 | .tx_loadsz = 1, | |
154 | }, | |
155 | [PORT_8250] = { | |
156 | .name = "8250", | |
157 | .fifo_size = 1, | |
158 | .tx_loadsz = 1, | |
159 | }, | |
160 | [PORT_16450] = { | |
161 | .name = "16450", | |
162 | .fifo_size = 1, | |
163 | .tx_loadsz = 1, | |
164 | }, | |
165 | [PORT_16550] = { | |
166 | .name = "16550", | |
167 | .fifo_size = 1, | |
168 | .tx_loadsz = 1, | |
169 | }, | |
170 | [PORT_16550A] = { | |
171 | .name = "16550A", | |
172 | .fifo_size = 16, | |
173 | .tx_loadsz = 16, | |
174 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
175 | .flags = UART_CAP_FIFO, | |
176 | }, | |
177 | [PORT_CIRRUS] = { | |
178 | .name = "Cirrus", | |
179 | .fifo_size = 1, | |
180 | .tx_loadsz = 1, | |
181 | }, | |
182 | [PORT_16650] = { | |
183 | .name = "ST16650", | |
184 | .fifo_size = 1, | |
185 | .tx_loadsz = 1, | |
186 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
187 | }, | |
188 | [PORT_16650V2] = { | |
189 | .name = "ST16650V2", | |
190 | .fifo_size = 32, | |
191 | .tx_loadsz = 16, | |
192 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
193 | UART_FCR_T_TRIG_00, | |
194 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
195 | }, | |
196 | [PORT_16750] = { | |
197 | .name = "TI16750", | |
198 | .fifo_size = 64, | |
199 | .tx_loadsz = 64, | |
200 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
201 | UART_FCR7_64BYTE, | |
202 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, | |
203 | }, | |
204 | [PORT_STARTECH] = { | |
205 | .name = "Startech", | |
206 | .fifo_size = 1, | |
207 | .tx_loadsz = 1, | |
208 | }, | |
209 | [PORT_16C950] = { | |
210 | .name = "16C950/954", | |
211 | .fifo_size = 128, | |
212 | .tx_loadsz = 128, | |
213 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
214 | .flags = UART_CAP_FIFO, | |
215 | }, | |
216 | [PORT_16654] = { | |
217 | .name = "ST16654", | |
218 | .fifo_size = 64, | |
219 | .tx_loadsz = 32, | |
220 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
221 | UART_FCR_T_TRIG_10, | |
222 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
223 | }, | |
224 | [PORT_16850] = { | |
225 | .name = "XR16850", | |
226 | .fifo_size = 128, | |
227 | .tx_loadsz = 128, | |
228 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
229 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
230 | }, | |
231 | [PORT_RSA] = { | |
232 | .name = "RSA", | |
233 | .fifo_size = 2048, | |
234 | .tx_loadsz = 2048, | |
235 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |
236 | .flags = UART_CAP_FIFO, | |
237 | }, | |
238 | [PORT_NS16550A] = { | |
239 | .name = "NS16550A", | |
240 | .fifo_size = 16, | |
241 | .tx_loadsz = 16, | |
242 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
243 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |
244 | }, | |
245 | [PORT_XSCALE] = { | |
246 | .name = "XScale", | |
247 | .fifo_size = 32, | |
248 | .tx_loadsz = 32, | |
249 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
250 | .flags = UART_CAP_FIFO | UART_CAP_UUE, | |
251 | }, | |
252 | }; | |
253 | ||
254 | static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset) | |
255 | { | |
256 | offset <<= up->port.regshift; | |
257 | ||
258 | switch (up->port.iotype) { | |
259 | case UPIO_HUB6: | |
260 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |
261 | return inb(up->port.iobase + 1); | |
262 | ||
263 | case UPIO_MEM: | |
264 | return readb(up->port.membase + offset); | |
265 | ||
266 | case UPIO_MEM32: | |
267 | return readl(up->port.membase + offset); | |
268 | ||
269 | default: | |
270 | return inb(up->port.iobase + offset); | |
271 | } | |
272 | } | |
273 | ||
274 | static _INLINE_ void | |
275 | serial_out(struct uart_8250_port *up, int offset, int value) | |
276 | { | |
277 | offset <<= up->port.regshift; | |
278 | ||
279 | switch (up->port.iotype) { | |
280 | case UPIO_HUB6: | |
281 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |
282 | outb(value, up->port.iobase + 1); | |
283 | break; | |
284 | ||
285 | case UPIO_MEM: | |
286 | writeb(value, up->port.membase + offset); | |
287 | break; | |
288 | ||
289 | case UPIO_MEM32: | |
290 | writel(value, up->port.membase + offset); | |
291 | break; | |
292 | ||
293 | default: | |
294 | outb(value, up->port.iobase + offset); | |
295 | } | |
296 | } | |
297 | ||
298 | /* | |
299 | * We used to support using pause I/O for certain machines. We | |
300 | * haven't supported this for a while, but just in case it's badly | |
301 | * needed for certain old 386 machines, I've left these #define's | |
302 | * in.... | |
303 | */ | |
304 | #define serial_inp(up, offset) serial_in(up, offset) | |
305 | #define serial_outp(up, offset, value) serial_out(up, offset, value) | |
306 | ||
307 | ||
308 | /* | |
309 | * For the 16C950 | |
310 | */ | |
311 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) | |
312 | { | |
313 | serial_out(up, UART_SCR, offset); | |
314 | serial_out(up, UART_ICR, value); | |
315 | } | |
316 | ||
317 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) | |
318 | { | |
319 | unsigned int value; | |
320 | ||
321 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
322 | serial_out(up, UART_SCR, offset); | |
323 | value = serial_in(up, UART_ICR); | |
324 | serial_icr_write(up, UART_ACR, up->acr); | |
325 | ||
326 | return value; | |
327 | } | |
328 | ||
329 | /* | |
330 | * FIFO support. | |
331 | */ | |
332 | static inline void serial8250_clear_fifos(struct uart_8250_port *p) | |
333 | { | |
334 | if (p->capabilities & UART_CAP_FIFO) { | |
335 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); | |
336 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |
337 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
338 | serial_outp(p, UART_FCR, 0); | |
339 | } | |
340 | } | |
341 | ||
342 | /* | |
343 | * IER sleep support. UARTs which have EFRs need the "extended | |
344 | * capability" bit enabled. Note that on XR16C850s, we need to | |
345 | * reset LCR to write to IER. | |
346 | */ | |
347 | static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep) | |
348 | { | |
349 | if (p->capabilities & UART_CAP_SLEEP) { | |
350 | if (p->capabilities & UART_CAP_EFR) { | |
351 | serial_outp(p, UART_LCR, 0xBF); | |
352 | serial_outp(p, UART_EFR, UART_EFR_ECB); | |
353 | serial_outp(p, UART_LCR, 0); | |
354 | } | |
355 | serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); | |
356 | if (p->capabilities & UART_CAP_EFR) { | |
357 | serial_outp(p, UART_LCR, 0xBF); | |
358 | serial_outp(p, UART_EFR, 0); | |
359 | serial_outp(p, UART_LCR, 0); | |
360 | } | |
361 | } | |
362 | } | |
363 | ||
364 | #ifdef CONFIG_SERIAL_8250_RSA | |
365 | /* | |
366 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
367 | * We set the port uart clock rate if we succeed. | |
368 | */ | |
369 | static int __enable_rsa(struct uart_8250_port *up) | |
370 | { | |
371 | unsigned char mode; | |
372 | int result; | |
373 | ||
374 | mode = serial_inp(up, UART_RSA_MSR); | |
375 | result = mode & UART_RSA_MSR_FIFO; | |
376 | ||
377 | if (!result) { | |
378 | serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); | |
379 | mode = serial_inp(up, UART_RSA_MSR); | |
380 | result = mode & UART_RSA_MSR_FIFO; | |
381 | } | |
382 | ||
383 | if (result) | |
384 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
385 | ||
386 | return result; | |
387 | } | |
388 | ||
389 | static void enable_rsa(struct uart_8250_port *up) | |
390 | { | |
391 | if (up->port.type == PORT_RSA) { | |
392 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
393 | spin_lock_irq(&up->port.lock); | |
394 | __enable_rsa(up); | |
395 | spin_unlock_irq(&up->port.lock); | |
396 | } | |
397 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
398 | serial_outp(up, UART_RSA_FRR, 0); | |
399 | } | |
400 | } | |
401 | ||
402 | /* | |
403 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
404 | * It is unknown why interrupts were disabled in here. However, | |
405 | * the caller is expected to preserve this behaviour by grabbing | |
406 | * the spinlock before calling this function. | |
407 | */ | |
408 | static void disable_rsa(struct uart_8250_port *up) | |
409 | { | |
410 | unsigned char mode; | |
411 | int result; | |
412 | ||
413 | if (up->port.type == PORT_RSA && | |
414 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
415 | spin_lock_irq(&up->port.lock); | |
416 | ||
417 | mode = serial_inp(up, UART_RSA_MSR); | |
418 | result = !(mode & UART_RSA_MSR_FIFO); | |
419 | ||
420 | if (!result) { | |
421 | serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); | |
422 | mode = serial_inp(up, UART_RSA_MSR); | |
423 | result = !(mode & UART_RSA_MSR_FIFO); | |
424 | } | |
425 | ||
426 | if (result) | |
427 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
428 | spin_unlock_irq(&up->port.lock); | |
429 | } | |
430 | } | |
431 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
432 | ||
433 | /* | |
434 | * This is a quickie test to see how big the FIFO is. | |
435 | * It doesn't work at all the time, more's the pity. | |
436 | */ | |
437 | static int size_fifo(struct uart_8250_port *up) | |
438 | { | |
439 | unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr; | |
440 | int count; | |
441 | ||
442 | old_lcr = serial_inp(up, UART_LCR); | |
443 | serial_outp(up, UART_LCR, 0); | |
444 | old_fcr = serial_inp(up, UART_FCR); | |
445 | old_mcr = serial_inp(up, UART_MCR); | |
446 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
447 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
448 | serial_outp(up, UART_MCR, UART_MCR_LOOP); | |
449 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
450 | old_dll = serial_inp(up, UART_DLL); | |
451 | old_dlm = serial_inp(up, UART_DLM); | |
452 | serial_outp(up, UART_DLL, 0x01); | |
453 | serial_outp(up, UART_DLM, 0x00); | |
454 | serial_outp(up, UART_LCR, 0x03); | |
455 | for (count = 0; count < 256; count++) | |
456 | serial_outp(up, UART_TX, count); | |
457 | mdelay(20);/* FIXME - schedule_timeout */ | |
458 | for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && | |
459 | (count < 256); count++) | |
460 | serial_inp(up, UART_RX); | |
461 | serial_outp(up, UART_FCR, old_fcr); | |
462 | serial_outp(up, UART_MCR, old_mcr); | |
463 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
464 | serial_outp(up, UART_DLL, old_dll); | |
465 | serial_outp(up, UART_DLM, old_dlm); | |
466 | serial_outp(up, UART_LCR, old_lcr); | |
467 | ||
468 | return count; | |
469 | } | |
470 | ||
471 | /* | |
472 | * Read UART ID using the divisor method - set DLL and DLM to zero | |
473 | * and the revision will be in DLL and device type in DLM. We | |
474 | * preserve the device state across this. | |
475 | */ | |
476 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) | |
477 | { | |
478 | unsigned char old_dll, old_dlm, old_lcr; | |
479 | unsigned int id; | |
480 | ||
481 | old_lcr = serial_inp(p, UART_LCR); | |
482 | serial_outp(p, UART_LCR, UART_LCR_DLAB); | |
483 | ||
484 | old_dll = serial_inp(p, UART_DLL); | |
485 | old_dlm = serial_inp(p, UART_DLM); | |
486 | ||
487 | serial_outp(p, UART_DLL, 0); | |
488 | serial_outp(p, UART_DLM, 0); | |
489 | ||
490 | id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; | |
491 | ||
492 | serial_outp(p, UART_DLL, old_dll); | |
493 | serial_outp(p, UART_DLM, old_dlm); | |
494 | serial_outp(p, UART_LCR, old_lcr); | |
495 | ||
496 | return id; | |
497 | } | |
498 | ||
499 | /* | |
500 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |
501 | * When this function is called we know it is at least a StarTech | |
502 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |
503 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |
504 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |
505 | * existence.) | |
506 | * | |
507 | * What evil have men's minds wrought... | |
508 | */ | |
509 | static void autoconfig_has_efr(struct uart_8250_port *up) | |
510 | { | |
511 | unsigned int id1, id2, id3, rev; | |
512 | ||
513 | /* | |
514 | * Everything with an EFR has SLEEP | |
515 | */ | |
516 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
517 | ||
518 | /* | |
519 | * First we check to see if it's an Oxford Semiconductor UART. | |
520 | * | |
521 | * If we have to do this here because some non-National | |
522 | * Semiconductor clone chips lock up if you try writing to the | |
523 | * LSR register (which serial_icr_read does) | |
524 | */ | |
525 | ||
526 | /* | |
527 | * Check for Oxford Semiconductor 16C950. | |
528 | * | |
529 | * EFR [4] must be set else this test fails. | |
530 | * | |
531 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |
532 | * claims that it's needed for 952 dual UART's (which are not | |
533 | * recommended for new designs). | |
534 | */ | |
535 | up->acr = 0; | |
536 | serial_out(up, UART_LCR, 0xBF); | |
537 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
538 | serial_out(up, UART_LCR, 0x00); | |
539 | id1 = serial_icr_read(up, UART_ID1); | |
540 | id2 = serial_icr_read(up, UART_ID2); | |
541 | id3 = serial_icr_read(up, UART_ID3); | |
542 | rev = serial_icr_read(up, UART_REV); | |
543 | ||
544 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); | |
545 | ||
546 | if (id1 == 0x16 && id2 == 0xC9 && | |
547 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { | |
548 | up->port.type = PORT_16C950; | |
4ba5e35d RK |
549 | |
550 | /* | |
551 | * Enable work around for the Oxford Semiconductor 952 rev B | |
552 | * chip which causes it to seriously miscalculate baud rates | |
553 | * when DLL is 0. | |
554 | */ | |
555 | if (id3 == 0x52 && rev == 0x01) | |
556 | up->bugs |= UART_BUG_QUOT; | |
1da177e4 LT |
557 | return; |
558 | } | |
559 | ||
560 | /* | |
561 | * We check for a XR16C850 by setting DLL and DLM to 0, and then | |
562 | * reading back DLL and DLM. The chip type depends on the DLM | |
563 | * value read back: | |
564 | * 0x10 - XR16C850 and the DLL contains the chip revision. | |
565 | * 0x12 - XR16C2850. | |
566 | * 0x14 - XR16C854. | |
567 | */ | |
568 | id1 = autoconfig_read_divisor_id(up); | |
569 | DEBUG_AUTOCONF("850id=%04x ", id1); | |
570 | ||
571 | id2 = id1 >> 8; | |
572 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { | |
1da177e4 LT |
573 | up->port.type = PORT_16850; |
574 | return; | |
575 | } | |
576 | ||
577 | /* | |
578 | * It wasn't an XR16C850. | |
579 | * | |
580 | * We distinguish between the '654 and the '650 by counting | |
581 | * how many bytes are in the FIFO. I'm using this for now, | |
582 | * since that's the technique that was sent to me in the | |
583 | * serial driver update, but I'm not convinced this works. | |
584 | * I've had problems doing this in the past. -TYT | |
585 | */ | |
586 | if (size_fifo(up) == 64) | |
587 | up->port.type = PORT_16654; | |
588 | else | |
589 | up->port.type = PORT_16650V2; | |
590 | } | |
591 | ||
592 | /* | |
593 | * We detected a chip without a FIFO. Only two fall into | |
594 | * this category - the original 8250 and the 16450. The | |
595 | * 16450 has a scratch register (accessible with LCR=0) | |
596 | */ | |
597 | static void autoconfig_8250(struct uart_8250_port *up) | |
598 | { | |
599 | unsigned char scratch, status1, status2; | |
600 | ||
601 | up->port.type = PORT_8250; | |
602 | ||
603 | scratch = serial_in(up, UART_SCR); | |
604 | serial_outp(up, UART_SCR, 0xa5); | |
605 | status1 = serial_in(up, UART_SCR); | |
606 | serial_outp(up, UART_SCR, 0x5a); | |
607 | status2 = serial_in(up, UART_SCR); | |
608 | serial_outp(up, UART_SCR, scratch); | |
609 | ||
610 | if (status1 == 0xa5 && status2 == 0x5a) | |
611 | up->port.type = PORT_16450; | |
612 | } | |
613 | ||
614 | static int broken_efr(struct uart_8250_port *up) | |
615 | { | |
616 | /* | |
617 | * Exar ST16C2550 "A2" devices incorrectly detect as | |
618 | * having an EFR, and report an ID of 0x0201. See | |
619 | * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf | |
620 | */ | |
621 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | |
622 | return 1; | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | /* | |
628 | * We know that the chip has FIFOs. Does it have an EFR? The | |
629 | * EFR is located in the same register position as the IIR and | |
630 | * we know the top two bits of the IIR are currently set. The | |
631 | * EFR should contain zero. Try to read the EFR. | |
632 | */ | |
633 | static void autoconfig_16550a(struct uart_8250_port *up) | |
634 | { | |
635 | unsigned char status1, status2; | |
636 | unsigned int iersave; | |
637 | ||
638 | up->port.type = PORT_16550A; | |
639 | up->capabilities |= UART_CAP_FIFO; | |
640 | ||
641 | /* | |
642 | * Check for presence of the EFR when DLAB is set. | |
643 | * Only ST16C650V1 UARTs pass this test. | |
644 | */ | |
645 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
646 | if (serial_in(up, UART_EFR) == 0) { | |
647 | serial_outp(up, UART_EFR, 0xA8); | |
648 | if (serial_in(up, UART_EFR) != 0) { | |
649 | DEBUG_AUTOCONF("EFRv1 "); | |
650 | up->port.type = PORT_16650; | |
651 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
652 | } else { | |
653 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); | |
654 | } | |
655 | serial_outp(up, UART_EFR, 0); | |
656 | return; | |
657 | } | |
658 | ||
659 | /* | |
660 | * Maybe it requires 0xbf to be written to the LCR. | |
661 | * (other ST16C650V2 UARTs, TI16C752A, etc) | |
662 | */ | |
663 | serial_outp(up, UART_LCR, 0xBF); | |
664 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { | |
665 | DEBUG_AUTOCONF("EFRv2 "); | |
666 | autoconfig_has_efr(up); | |
667 | return; | |
668 | } | |
669 | ||
670 | /* | |
671 | * Check for a National Semiconductor SuperIO chip. | |
672 | * Attempt to switch to bank 2, read the value of the LOOP bit | |
673 | * from EXCR1. Switch back to bank 0, change it in MCR. Then | |
674 | * switch back to bank 2, read it from EXCR1 again and check | |
675 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 | |
1da177e4 LT |
676 | */ |
677 | serial_outp(up, UART_LCR, 0); | |
678 | status1 = serial_in(up, UART_MCR); | |
679 | serial_outp(up, UART_LCR, 0xE0); | |
680 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
681 | ||
682 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { | |
683 | serial_outp(up, UART_LCR, 0); | |
684 | serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP); | |
685 | serial_outp(up, UART_LCR, 0xE0); | |
686 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
687 | serial_outp(up, UART_LCR, 0); | |
688 | serial_outp(up, UART_MCR, status1); | |
689 | ||
690 | if ((status2 ^ status1) & UART_MCR_LOOP) { | |
857dde2e DW |
691 | unsigned short quot; |
692 | ||
1da177e4 | 693 | serial_outp(up, UART_LCR, 0xE0); |
857dde2e DW |
694 | |
695 | quot = serial_inp(up, UART_DLM) << 8; | |
696 | quot += serial_inp(up, UART_DLL); | |
697 | quot <<= 3; | |
698 | ||
1da177e4 LT |
699 | status1 = serial_in(up, 0x04); /* EXCR1 */ |
700 | status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | |
701 | status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
702 | serial_outp(up, 0x04, status1); | |
857dde2e DW |
703 | |
704 | serial_outp(up, UART_DLL, quot & 0xff); | |
705 | serial_outp(up, UART_DLM, quot >> 8); | |
706 | ||
1da177e4 | 707 | serial_outp(up, UART_LCR, 0); |
1da177e4 | 708 | |
857dde2e | 709 | up->port.uartclk = 921600*16; |
1da177e4 LT |
710 | up->port.type = PORT_NS16550A; |
711 | up->capabilities |= UART_NATSEMI; | |
712 | return; | |
713 | } | |
714 | } | |
715 | ||
716 | /* | |
717 | * No EFR. Try to detect a TI16750, which only sets bit 5 of | |
718 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. | |
719 | * Try setting it with and without DLAB set. Cheap clones | |
720 | * set bit 5 without DLAB set. | |
721 | */ | |
722 | serial_outp(up, UART_LCR, 0); | |
723 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
724 | status1 = serial_in(up, UART_IIR) >> 5; | |
725 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
726 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
727 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
728 | status2 = serial_in(up, UART_IIR) >> 5; | |
729 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
730 | serial_outp(up, UART_LCR, 0); | |
731 | ||
732 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); | |
733 | ||
734 | if (status1 == 6 && status2 == 7) { | |
735 | up->port.type = PORT_16750; | |
736 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; | |
737 | return; | |
738 | } | |
739 | ||
740 | /* | |
741 | * Try writing and reading the UART_IER_UUE bit (b6). | |
742 | * If it works, this is probably one of the Xscale platform's | |
743 | * internal UARTs. | |
744 | * We're going to explicitly set the UUE bit to 0 before | |
745 | * trying to write and read a 1 just to make sure it's not | |
746 | * already a 1 and maybe locked there before we even start start. | |
747 | */ | |
748 | iersave = serial_in(up, UART_IER); | |
749 | serial_outp(up, UART_IER, iersave & ~UART_IER_UUE); | |
750 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { | |
751 | /* | |
752 | * OK it's in a known zero state, try writing and reading | |
753 | * without disturbing the current state of the other bits. | |
754 | */ | |
755 | serial_outp(up, UART_IER, iersave | UART_IER_UUE); | |
756 | if (serial_in(up, UART_IER) & UART_IER_UUE) { | |
757 | /* | |
758 | * It's an Xscale. | |
759 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). | |
760 | */ | |
761 | DEBUG_AUTOCONF("Xscale "); | |
762 | up->port.type = PORT_XSCALE; | |
763 | up->capabilities |= UART_CAP_UUE; | |
764 | return; | |
765 | } | |
766 | } else { | |
767 | /* | |
768 | * If we got here we couldn't force the IER_UUE bit to 0. | |
769 | * Log it and continue. | |
770 | */ | |
771 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); | |
772 | } | |
773 | serial_outp(up, UART_IER, iersave); | |
774 | } | |
775 | ||
776 | /* | |
777 | * This routine is called by rs_init() to initialize a specific serial | |
778 | * port. It determines what type of UART chip this serial port is | |
779 | * using: 8250, 16450, 16550, 16550A. The important question is | |
780 | * whether or not this UART is a 16550A or not, since this will | |
781 | * determine whether or not we can use its FIFO features or not. | |
782 | */ | |
783 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | |
784 | { | |
785 | unsigned char status1, scratch, scratch2, scratch3; | |
786 | unsigned char save_lcr, save_mcr; | |
787 | unsigned long flags; | |
788 | ||
789 | if (!up->port.iobase && !up->port.mapbase && !up->port.membase) | |
790 | return; | |
791 | ||
792 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ", | |
793 | up->port.line, up->port.iobase, up->port.membase); | |
794 | ||
795 | /* | |
796 | * We really do need global IRQs disabled here - we're going to | |
797 | * be frobbing the chips IRQ enable register to see if it exists. | |
798 | */ | |
799 | spin_lock_irqsave(&up->port.lock, flags); | |
800 | // save_flags(flags); cli(); | |
801 | ||
802 | up->capabilities = 0; | |
4ba5e35d | 803 | up->bugs = 0; |
1da177e4 LT |
804 | |
805 | if (!(up->port.flags & UPF_BUGGY_UART)) { | |
806 | /* | |
807 | * Do a simple existence test first; if we fail this, | |
808 | * there's no point trying anything else. | |
809 | * | |
810 | * 0x80 is used as a nonsense port to prevent against | |
811 | * false positives due to ISA bus float. The | |
812 | * assumption is that 0x80 is a non-existent port; | |
813 | * which should be safe since include/asm/io.h also | |
814 | * makes this assumption. | |
815 | * | |
816 | * Note: this is safe as long as MCR bit 4 is clear | |
817 | * and the device is in "PC" mode. | |
818 | */ | |
819 | scratch = serial_inp(up, UART_IER); | |
820 | serial_outp(up, UART_IER, 0); | |
821 | #ifdef __i386__ | |
822 | outb(0xff, 0x080); | |
823 | #endif | |
824 | scratch2 = serial_inp(up, UART_IER); | |
825 | serial_outp(up, UART_IER, 0x0F); | |
826 | #ifdef __i386__ | |
827 | outb(0, 0x080); | |
828 | #endif | |
829 | scratch3 = serial_inp(up, UART_IER); | |
830 | serial_outp(up, UART_IER, scratch); | |
831 | if (scratch2 != 0 || scratch3 != 0x0F) { | |
832 | /* | |
833 | * We failed; there's nothing here | |
834 | */ | |
835 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", | |
836 | scratch2, scratch3); | |
837 | goto out; | |
838 | } | |
839 | } | |
840 | ||
841 | save_mcr = serial_in(up, UART_MCR); | |
842 | save_lcr = serial_in(up, UART_LCR); | |
843 | ||
844 | /* | |
845 | * Check to see if a UART is really there. Certain broken | |
846 | * internal modems based on the Rockwell chipset fail this | |
847 | * test, because they apparently don't implement the loopback | |
848 | * test mode. So this test is skipped on the COM 1 through | |
849 | * COM 4 ports. This *should* be safe, since no board | |
850 | * manufacturer would be stupid enough to design a board | |
851 | * that conflicts with COM 1-4 --- we hope! | |
852 | */ | |
853 | if (!(up->port.flags & UPF_SKIP_TEST)) { | |
854 | serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); | |
855 | status1 = serial_inp(up, UART_MSR) & 0xF0; | |
856 | serial_outp(up, UART_MCR, save_mcr); | |
857 | if (status1 != 0x90) { | |
858 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", | |
859 | status1); | |
860 | goto out; | |
861 | } | |
862 | } | |
863 | ||
864 | /* | |
865 | * We're pretty sure there's a port here. Lets find out what | |
866 | * type of port it is. The IIR top two bits allows us to find | |
6f0d618f | 867 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1da177e4 LT |
868 | * determines what we test for next. |
869 | * | |
870 | * We also initialise the EFR (if any) to zero for later. The | |
871 | * EFR occupies the same register location as the FCR and IIR. | |
872 | */ | |
873 | serial_outp(up, UART_LCR, 0xBF); | |
874 | serial_outp(up, UART_EFR, 0); | |
875 | serial_outp(up, UART_LCR, 0); | |
876 | ||
877 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
878 | scratch = serial_in(up, UART_IIR) >> 6; | |
879 | ||
880 | DEBUG_AUTOCONF("iir=%d ", scratch); | |
881 | ||
882 | switch (scratch) { | |
883 | case 0: | |
884 | autoconfig_8250(up); | |
885 | break; | |
886 | case 1: | |
887 | up->port.type = PORT_UNKNOWN; | |
888 | break; | |
889 | case 2: | |
890 | up->port.type = PORT_16550; | |
891 | break; | |
892 | case 3: | |
893 | autoconfig_16550a(up); | |
894 | break; | |
895 | } | |
896 | ||
897 | #ifdef CONFIG_SERIAL_8250_RSA | |
898 | /* | |
899 | * Only probe for RSA ports if we got the region. | |
900 | */ | |
901 | if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) { | |
902 | int i; | |
903 | ||
904 | for (i = 0 ; i < probe_rsa_count; ++i) { | |
905 | if (probe_rsa[i] == up->port.iobase && | |
906 | __enable_rsa(up)) { | |
907 | up->port.type = PORT_RSA; | |
908 | break; | |
909 | } | |
910 | } | |
911 | } | |
912 | #endif | |
913 | serial_outp(up, UART_LCR, save_lcr); | |
914 | ||
915 | if (up->capabilities != uart_config[up->port.type].flags) { | |
916 | printk(KERN_WARNING | |
917 | "ttyS%d: detected caps %08x should be %08x\n", | |
918 | up->port.line, up->capabilities, | |
919 | uart_config[up->port.type].flags); | |
920 | } | |
921 | ||
922 | up->port.fifosize = uart_config[up->port.type].fifo_size; | |
923 | up->capabilities = uart_config[up->port.type].flags; | |
924 | up->tx_loadsz = uart_config[up->port.type].tx_loadsz; | |
925 | ||
926 | if (up->port.type == PORT_UNKNOWN) | |
927 | goto out; | |
928 | ||
929 | /* | |
930 | * Reset the UART. | |
931 | */ | |
932 | #ifdef CONFIG_SERIAL_8250_RSA | |
933 | if (up->port.type == PORT_RSA) | |
934 | serial_outp(up, UART_RSA_FRR, 0); | |
935 | #endif | |
936 | serial_outp(up, UART_MCR, save_mcr); | |
937 | serial8250_clear_fifos(up); | |
938 | (void)serial_in(up, UART_RX); | |
939 | serial_outp(up, UART_IER, 0); | |
940 | ||
941 | out: | |
942 | spin_unlock_irqrestore(&up->port.lock, flags); | |
943 | // restore_flags(flags); | |
944 | DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name); | |
945 | } | |
946 | ||
947 | static void autoconfig_irq(struct uart_8250_port *up) | |
948 | { | |
949 | unsigned char save_mcr, save_ier; | |
950 | unsigned char save_ICP = 0; | |
951 | unsigned int ICP = 0; | |
952 | unsigned long irqs; | |
953 | int irq; | |
954 | ||
955 | if (up->port.flags & UPF_FOURPORT) { | |
956 | ICP = (up->port.iobase & 0xfe0) | 0x1f; | |
957 | save_ICP = inb_p(ICP); | |
958 | outb_p(0x80, ICP); | |
959 | (void) inb_p(ICP); | |
960 | } | |
961 | ||
962 | /* forget possible initially masked and pending IRQ */ | |
963 | probe_irq_off(probe_irq_on()); | |
964 | save_mcr = serial_inp(up, UART_MCR); | |
965 | save_ier = serial_inp(up, UART_IER); | |
966 | serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); | |
967 | ||
968 | irqs = probe_irq_on(); | |
969 | serial_outp(up, UART_MCR, 0); | |
970 | udelay (10); | |
971 | if (up->port.flags & UPF_FOURPORT) { | |
972 | serial_outp(up, UART_MCR, | |
973 | UART_MCR_DTR | UART_MCR_RTS); | |
974 | } else { | |
975 | serial_outp(up, UART_MCR, | |
976 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); | |
977 | } | |
978 | serial_outp(up, UART_IER, 0x0f); /* enable all intrs */ | |
979 | (void)serial_inp(up, UART_LSR); | |
980 | (void)serial_inp(up, UART_RX); | |
981 | (void)serial_inp(up, UART_IIR); | |
982 | (void)serial_inp(up, UART_MSR); | |
983 | serial_outp(up, UART_TX, 0xFF); | |
984 | udelay (20); | |
985 | irq = probe_irq_off(irqs); | |
986 | ||
987 | serial_outp(up, UART_MCR, save_mcr); | |
988 | serial_outp(up, UART_IER, save_ier); | |
989 | ||
990 | if (up->port.flags & UPF_FOURPORT) | |
991 | outb_p(save_ICP, ICP); | |
992 | ||
993 | up->port.irq = (irq > 0) ? irq : 0; | |
994 | } | |
995 | ||
e763b90c RK |
996 | static inline void __stop_tx(struct uart_8250_port *p) |
997 | { | |
998 | if (p->ier & UART_IER_THRI) { | |
999 | p->ier &= ~UART_IER_THRI; | |
1000 | serial_out(p, UART_IER, p->ier); | |
1001 | } | |
1002 | } | |
1003 | ||
b129a8cc | 1004 | static void serial8250_stop_tx(struct uart_port *port) |
1da177e4 LT |
1005 | { |
1006 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1007 | ||
e763b90c | 1008 | __stop_tx(up); |
1da177e4 LT |
1009 | |
1010 | /* | |
e763b90c | 1011 | * We really want to stop the transmitter from sending. |
1da177e4 | 1012 | */ |
e763b90c | 1013 | if (up->port.type == PORT_16C950) { |
1da177e4 LT |
1014 | up->acr |= UART_ACR_TXDIS; |
1015 | serial_icr_write(up, UART_ACR, up->acr); | |
1016 | } | |
1017 | } | |
1018 | ||
55d3b282 RK |
1019 | static void transmit_chars(struct uart_8250_port *up); |
1020 | ||
b129a8cc | 1021 | static void serial8250_start_tx(struct uart_port *port) |
1da177e4 LT |
1022 | { |
1023 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1024 | ||
1025 | if (!(up->ier & UART_IER_THRI)) { | |
1026 | up->ier |= UART_IER_THRI; | |
1027 | serial_out(up, UART_IER, up->ier); | |
55d3b282 | 1028 | |
67f7654e | 1029 | if (up->bugs & UART_BUG_TXEN) { |
55d3b282 RK |
1030 | unsigned char lsr, iir; |
1031 | lsr = serial_in(up, UART_LSR); | |
1032 | iir = serial_in(up, UART_IIR); | |
1033 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) | |
1034 | transmit_chars(up); | |
1035 | } | |
1da177e4 | 1036 | } |
e763b90c | 1037 | |
1da177e4 | 1038 | /* |
e763b90c | 1039 | * Re-enable the transmitter if we disabled it. |
1da177e4 | 1040 | */ |
e763b90c | 1041 | if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1da177e4 LT |
1042 | up->acr &= ~UART_ACR_TXDIS; |
1043 | serial_icr_write(up, UART_ACR, up->acr); | |
1044 | } | |
1045 | } | |
1046 | ||
1047 | static void serial8250_stop_rx(struct uart_port *port) | |
1048 | { | |
1049 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1050 | ||
1051 | up->ier &= ~UART_IER_RLSI; | |
1052 | up->port.read_status_mask &= ~UART_LSR_DR; | |
1053 | serial_out(up, UART_IER, up->ier); | |
1054 | } | |
1055 | ||
1056 | static void serial8250_enable_ms(struct uart_port *port) | |
1057 | { | |
1058 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1059 | ||
1060 | up->ier |= UART_IER_MSI; | |
1061 | serial_out(up, UART_IER, up->ier); | |
1062 | } | |
1063 | ||
1064 | static _INLINE_ void | |
1065 | receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs) | |
1066 | { | |
1067 | struct tty_struct *tty = up->port.info->tty; | |
1068 | unsigned char ch, lsr = *status; | |
1069 | int max_count = 256; | |
1070 | char flag; | |
1071 | ||
1072 | do { | |
1073 | /* The following is not allowed by the tty layer and | |
1074 | unsafe. It should be fixed ASAP */ | |
1075 | if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) { | |
1076 | if (tty->low_latency) { | |
1077 | spin_unlock(&up->port.lock); | |
1078 | tty_flip_buffer_push(tty); | |
1079 | spin_lock(&up->port.lock); | |
1080 | } | |
23907eb8 RK |
1081 | /* |
1082 | * If this failed then we will throw away the | |
1083 | * bytes but must do so to clear interrupts | |
1084 | */ | |
1da177e4 LT |
1085 | } |
1086 | ch = serial_inp(up, UART_RX); | |
1087 | flag = TTY_NORMAL; | |
1088 | up->port.icount.rx++; | |
1089 | ||
1090 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
1091 | /* | |
1092 | * Recover the break flag from console xmit | |
1093 | */ | |
1094 | if (up->port.line == up->port.cons->index) { | |
1095 | lsr |= up->lsr_break_flag; | |
1096 | up->lsr_break_flag = 0; | |
1097 | } | |
1098 | #endif | |
1099 | ||
1100 | if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | | |
1101 | UART_LSR_FE | UART_LSR_OE))) { | |
1102 | /* | |
1103 | * For statistics only | |
1104 | */ | |
1105 | if (lsr & UART_LSR_BI) { | |
1106 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
1107 | up->port.icount.brk++; | |
1108 | /* | |
1109 | * We do the SysRQ and SAK checking | |
1110 | * here because otherwise the break | |
1111 | * may get masked by ignore_status_mask | |
1112 | * or read_status_mask. | |
1113 | */ | |
1114 | if (uart_handle_break(&up->port)) | |
1115 | goto ignore_char; | |
1116 | } else if (lsr & UART_LSR_PE) | |
1117 | up->port.icount.parity++; | |
1118 | else if (lsr & UART_LSR_FE) | |
1119 | up->port.icount.frame++; | |
1120 | if (lsr & UART_LSR_OE) | |
1121 | up->port.icount.overrun++; | |
1122 | ||
1123 | /* | |
23907eb8 | 1124 | * Mask off conditions which should be ignored. |
1da177e4 LT |
1125 | */ |
1126 | lsr &= up->port.read_status_mask; | |
1127 | ||
1128 | if (lsr & UART_LSR_BI) { | |
1129 | DEBUG_INTR("handling break...."); | |
1130 | flag = TTY_BREAK; | |
1131 | } else if (lsr & UART_LSR_PE) | |
1132 | flag = TTY_PARITY; | |
1133 | else if (lsr & UART_LSR_FE) | |
1134 | flag = TTY_FRAME; | |
1135 | } | |
1136 | if (uart_handle_sysrq_char(&up->port, ch, regs)) | |
1137 | goto ignore_char; | |
05ab3014 RK |
1138 | |
1139 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
1140 | ||
1da177e4 LT |
1141 | ignore_char: |
1142 | lsr = serial_inp(up, UART_LSR); | |
1143 | } while ((lsr & UART_LSR_DR) && (max_count-- > 0)); | |
1144 | spin_unlock(&up->port.lock); | |
1145 | tty_flip_buffer_push(tty); | |
1146 | spin_lock(&up->port.lock); | |
1147 | *status = lsr; | |
1148 | } | |
1149 | ||
1150 | static _INLINE_ void transmit_chars(struct uart_8250_port *up) | |
1151 | { | |
1152 | struct circ_buf *xmit = &up->port.info->xmit; | |
1153 | int count; | |
1154 | ||
1155 | if (up->port.x_char) { | |
1156 | serial_outp(up, UART_TX, up->port.x_char); | |
1157 | up->port.icount.tx++; | |
1158 | up->port.x_char = 0; | |
1159 | return; | |
1160 | } | |
b129a8cc RK |
1161 | if (uart_tx_stopped(&up->port)) { |
1162 | serial8250_stop_tx(&up->port); | |
1163 | return; | |
1164 | } | |
1165 | if (uart_circ_empty(xmit)) { | |
e763b90c | 1166 | __stop_tx(up); |
1da177e4 LT |
1167 | return; |
1168 | } | |
1169 | ||
1170 | count = up->tx_loadsz; | |
1171 | do { | |
1172 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
1173 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1174 | up->port.icount.tx++; | |
1175 | if (uart_circ_empty(xmit)) | |
1176 | break; | |
1177 | } while (--count > 0); | |
1178 | ||
1179 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1180 | uart_write_wakeup(&up->port); | |
1181 | ||
1182 | DEBUG_INTR("THRE..."); | |
1183 | ||
1184 | if (uart_circ_empty(xmit)) | |
e763b90c | 1185 | __stop_tx(up); |
1da177e4 LT |
1186 | } |
1187 | ||
1188 | static _INLINE_ void check_modem_status(struct uart_8250_port *up) | |
1189 | { | |
1190 | int status; | |
1191 | ||
1192 | status = serial_in(up, UART_MSR); | |
1193 | ||
1194 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
1195 | return; | |
1196 | ||
1197 | if (status & UART_MSR_TERI) | |
1198 | up->port.icount.rng++; | |
1199 | if (status & UART_MSR_DDSR) | |
1200 | up->port.icount.dsr++; | |
1201 | if (status & UART_MSR_DDCD) | |
1202 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
1203 | if (status & UART_MSR_DCTS) | |
1204 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
1205 | ||
1206 | wake_up_interruptible(&up->port.info->delta_msr_wait); | |
1207 | } | |
1208 | ||
1209 | /* | |
1210 | * This handles the interrupt from one port. | |
1211 | */ | |
1212 | static inline void | |
1213 | serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs) | |
1214 | { | |
1215 | unsigned int status = serial_inp(up, UART_LSR); | |
1216 | ||
1217 | DEBUG_INTR("status = %x...", status); | |
1218 | ||
1219 | if (status & UART_LSR_DR) | |
1220 | receive_chars(up, &status, regs); | |
1221 | check_modem_status(up); | |
1222 | if (status & UART_LSR_THRE) | |
1223 | transmit_chars(up); | |
1224 | } | |
1225 | ||
1226 | /* | |
1227 | * This is the serial driver's interrupt routine. | |
1228 | * | |
1229 | * Arjan thinks the old way was overly complex, so it got simplified. | |
1230 | * Alan disagrees, saying that need the complexity to handle the weird | |
1231 | * nature of ISA shared interrupts. (This is a special exception.) | |
1232 | * | |
1233 | * In order to handle ISA shared interrupts properly, we need to check | |
1234 | * that all ports have been serviced, and therefore the ISA interrupt | |
1235 | * line has been de-asserted. | |
1236 | * | |
1237 | * This means we need to loop through all ports. checking that they | |
1238 | * don't have an interrupt pending. | |
1239 | */ | |
1240 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
1241 | { | |
1242 | struct irq_info *i = dev_id; | |
1243 | struct list_head *l, *end = NULL; | |
1244 | int pass_counter = 0, handled = 0; | |
1245 | ||
1246 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); | |
1247 | ||
1248 | spin_lock(&i->lock); | |
1249 | ||
1250 | l = i->head; | |
1251 | do { | |
1252 | struct uart_8250_port *up; | |
1253 | unsigned int iir; | |
1254 | ||
1255 | up = list_entry(l, struct uart_8250_port, list); | |
1256 | ||
1257 | iir = serial_in(up, UART_IIR); | |
1258 | if (!(iir & UART_IIR_NO_INT)) { | |
1259 | spin_lock(&up->port.lock); | |
1260 | serial8250_handle_port(up, regs); | |
1261 | spin_unlock(&up->port.lock); | |
1262 | ||
1263 | handled = 1; | |
1264 | ||
1265 | end = NULL; | |
1266 | } else if (end == NULL) | |
1267 | end = l; | |
1268 | ||
1269 | l = l->next; | |
1270 | ||
1271 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
1272 | /* If we hit this, we're dead. */ | |
1273 | printk(KERN_ERR "serial8250: too much work for " | |
1274 | "irq%d\n", irq); | |
1275 | break; | |
1276 | } | |
1277 | } while (l != end); | |
1278 | ||
1279 | spin_unlock(&i->lock); | |
1280 | ||
1281 | DEBUG_INTR("end.\n"); | |
1282 | ||
1283 | return IRQ_RETVAL(handled); | |
1284 | } | |
1285 | ||
1286 | /* | |
1287 | * To support ISA shared interrupts, we need to have one interrupt | |
1288 | * handler that ensures that the IRQ line has been deasserted | |
1289 | * before returning. Failing to do this will result in the IRQ | |
1290 | * line being stuck active, and, since ISA irqs are edge triggered, | |
1291 | * no more IRQs will be seen. | |
1292 | */ | |
1293 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) | |
1294 | { | |
1295 | spin_lock_irq(&i->lock); | |
1296 | ||
1297 | if (!list_empty(i->head)) { | |
1298 | if (i->head == &up->list) | |
1299 | i->head = i->head->next; | |
1300 | list_del(&up->list); | |
1301 | } else { | |
1302 | BUG_ON(i->head != &up->list); | |
1303 | i->head = NULL; | |
1304 | } | |
1305 | ||
1306 | spin_unlock_irq(&i->lock); | |
1307 | } | |
1308 | ||
1309 | static int serial_link_irq_chain(struct uart_8250_port *up) | |
1310 | { | |
1311 | struct irq_info *i = irq_lists + up->port.irq; | |
1312 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0; | |
1313 | ||
1314 | spin_lock_irq(&i->lock); | |
1315 | ||
1316 | if (i->head) { | |
1317 | list_add(&up->list, i->head); | |
1318 | spin_unlock_irq(&i->lock); | |
1319 | ||
1320 | ret = 0; | |
1321 | } else { | |
1322 | INIT_LIST_HEAD(&up->list); | |
1323 | i->head = &up->list; | |
1324 | spin_unlock_irq(&i->lock); | |
1325 | ||
1326 | ret = request_irq(up->port.irq, serial8250_interrupt, | |
1327 | irq_flags, "serial", i); | |
1328 | if (ret < 0) | |
1329 | serial_do_unlink(i, up); | |
1330 | } | |
1331 | ||
1332 | return ret; | |
1333 | } | |
1334 | ||
1335 | static void serial_unlink_irq_chain(struct uart_8250_port *up) | |
1336 | { | |
1337 | struct irq_info *i = irq_lists + up->port.irq; | |
1338 | ||
1339 | BUG_ON(i->head == NULL); | |
1340 | ||
1341 | if (list_empty(i->head)) | |
1342 | free_irq(up->port.irq, i); | |
1343 | ||
1344 | serial_do_unlink(i, up); | |
1345 | } | |
1346 | ||
1347 | /* | |
1348 | * This function is used to handle ports that do not have an | |
1349 | * interrupt. This doesn't work very well for 16450's, but gives | |
1350 | * barely passable results for a 16550A. (Although at the expense | |
1351 | * of much CPU overhead). | |
1352 | */ | |
1353 | static void serial8250_timeout(unsigned long data) | |
1354 | { | |
1355 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
1356 | unsigned int timeout; | |
1357 | unsigned int iir; | |
1358 | ||
1359 | iir = serial_in(up, UART_IIR); | |
1360 | if (!(iir & UART_IIR_NO_INT)) { | |
1361 | spin_lock(&up->port.lock); | |
1362 | serial8250_handle_port(up, NULL); | |
1363 | spin_unlock(&up->port.lock); | |
1364 | } | |
1365 | ||
1366 | timeout = up->port.timeout; | |
1367 | timeout = timeout > 6 ? (timeout / 2 - 2) : 1; | |
1368 | mod_timer(&up->timer, jiffies + timeout); | |
1369 | } | |
1370 | ||
1371 | static unsigned int serial8250_tx_empty(struct uart_port *port) | |
1372 | { | |
1373 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1374 | unsigned long flags; | |
1375 | unsigned int ret; | |
1376 | ||
1377 | spin_lock_irqsave(&up->port.lock, flags); | |
1378 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
1379 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1380 | ||
1381 | return ret; | |
1382 | } | |
1383 | ||
1384 | static unsigned int serial8250_get_mctrl(struct uart_port *port) | |
1385 | { | |
1386 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1da177e4 LT |
1387 | unsigned char status; |
1388 | unsigned int ret; | |
1389 | ||
1da177e4 | 1390 | status = serial_in(up, UART_MSR); |
1da177e4 LT |
1391 | |
1392 | ret = 0; | |
1393 | if (status & UART_MSR_DCD) | |
1394 | ret |= TIOCM_CAR; | |
1395 | if (status & UART_MSR_RI) | |
1396 | ret |= TIOCM_RNG; | |
1397 | if (status & UART_MSR_DSR) | |
1398 | ret |= TIOCM_DSR; | |
1399 | if (status & UART_MSR_CTS) | |
1400 | ret |= TIOCM_CTS; | |
1401 | return ret; | |
1402 | } | |
1403 | ||
1404 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1405 | { | |
1406 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1407 | unsigned char mcr = 0; | |
1408 | ||
1409 | if (mctrl & TIOCM_RTS) | |
1410 | mcr |= UART_MCR_RTS; | |
1411 | if (mctrl & TIOCM_DTR) | |
1412 | mcr |= UART_MCR_DTR; | |
1413 | if (mctrl & TIOCM_OUT1) | |
1414 | mcr |= UART_MCR_OUT1; | |
1415 | if (mctrl & TIOCM_OUT2) | |
1416 | mcr |= UART_MCR_OUT2; | |
1417 | if (mctrl & TIOCM_LOOP) | |
1418 | mcr |= UART_MCR_LOOP; | |
1419 | ||
1420 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; | |
1421 | ||
1422 | serial_out(up, UART_MCR, mcr); | |
1423 | } | |
1424 | ||
1425 | static void serial8250_break_ctl(struct uart_port *port, int break_state) | |
1426 | { | |
1427 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1428 | unsigned long flags; | |
1429 | ||
1430 | spin_lock_irqsave(&up->port.lock, flags); | |
1431 | if (break_state == -1) | |
1432 | up->lcr |= UART_LCR_SBC; | |
1433 | else | |
1434 | up->lcr &= ~UART_LCR_SBC; | |
1435 | serial_out(up, UART_LCR, up->lcr); | |
1436 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1437 | } | |
1438 | ||
1439 | static int serial8250_startup(struct uart_port *port) | |
1440 | { | |
1441 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1442 | unsigned long flags; | |
55d3b282 | 1443 | unsigned char lsr, iir; |
1da177e4 LT |
1444 | int retval; |
1445 | ||
1446 | up->capabilities = uart_config[up->port.type].flags; | |
1447 | up->mcr = 0; | |
1448 | ||
1449 | if (up->port.type == PORT_16C950) { | |
1450 | /* Wake up and initialize UART */ | |
1451 | up->acr = 0; | |
1452 | serial_outp(up, UART_LCR, 0xBF); | |
1453 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
1454 | serial_outp(up, UART_IER, 0); | |
1455 | serial_outp(up, UART_LCR, 0); | |
1456 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ | |
1457 | serial_outp(up, UART_LCR, 0xBF); | |
1458 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
1459 | serial_outp(up, UART_LCR, 0); | |
1460 | } | |
1461 | ||
1462 | #ifdef CONFIG_SERIAL_8250_RSA | |
1463 | /* | |
1464 | * If this is an RSA port, see if we can kick it up to the | |
1465 | * higher speed clock. | |
1466 | */ | |
1467 | enable_rsa(up); | |
1468 | #endif | |
1469 | ||
1470 | /* | |
1471 | * Clear the FIFO buffers and disable them. | |
1472 | * (they will be reeanbled in set_termios()) | |
1473 | */ | |
1474 | serial8250_clear_fifos(up); | |
1475 | ||
1476 | /* | |
1477 | * Clear the interrupt registers. | |
1478 | */ | |
1479 | (void) serial_inp(up, UART_LSR); | |
1480 | (void) serial_inp(up, UART_RX); | |
1481 | (void) serial_inp(up, UART_IIR); | |
1482 | (void) serial_inp(up, UART_MSR); | |
1483 | ||
1484 | /* | |
1485 | * At this point, there's no way the LSR could still be 0xff; | |
1486 | * if it is, then bail out, because there's likely no UART | |
1487 | * here. | |
1488 | */ | |
1489 | if (!(up->port.flags & UPF_BUGGY_UART) && | |
1490 | (serial_inp(up, UART_LSR) == 0xff)) { | |
1491 | printk("ttyS%d: LSR safety check engaged!\n", up->port.line); | |
1492 | return -ENODEV; | |
1493 | } | |
1494 | ||
1495 | /* | |
1496 | * For a XR16C850, we need to set the trigger levels | |
1497 | */ | |
1498 | if (up->port.type == PORT_16850) { | |
1499 | unsigned char fctr; | |
1500 | ||
1501 | serial_outp(up, UART_LCR, 0xbf); | |
1502 | ||
1503 | fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); | |
1504 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); | |
1505 | serial_outp(up, UART_TRG, UART_TRG_96); | |
1506 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX); | |
1507 | serial_outp(up, UART_TRG, UART_TRG_96); | |
1508 | ||
1509 | serial_outp(up, UART_LCR, 0); | |
1510 | } | |
1511 | ||
1512 | /* | |
1513 | * If the "interrupt" for this port doesn't correspond with any | |
1514 | * hardware interrupt, we use a timer-based system. The original | |
1515 | * driver used to do this with IRQ0. | |
1516 | */ | |
1517 | if (!is_real_interrupt(up->port.irq)) { | |
1518 | unsigned int timeout = up->port.timeout; | |
1519 | ||
1520 | timeout = timeout > 6 ? (timeout / 2 - 2) : 1; | |
1521 | ||
1522 | up->timer.data = (unsigned long)up; | |
1523 | mod_timer(&up->timer, jiffies + timeout); | |
1524 | } else { | |
1525 | retval = serial_link_irq_chain(up); | |
1526 | if (retval) | |
1527 | return retval; | |
1528 | } | |
1529 | ||
1530 | /* | |
1531 | * Now, initialize the UART | |
1532 | */ | |
1533 | serial_outp(up, UART_LCR, UART_LCR_WLEN8); | |
1534 | ||
1535 | spin_lock_irqsave(&up->port.lock, flags); | |
1536 | if (up->port.flags & UPF_FOURPORT) { | |
1537 | if (!is_real_interrupt(up->port.irq)) | |
1538 | up->port.mctrl |= TIOCM_OUT1; | |
1539 | } else | |
1540 | /* | |
1541 | * Most PC uarts need OUT2 raised to enable interrupts. | |
1542 | */ | |
1543 | if (is_real_interrupt(up->port.irq)) | |
1544 | up->port.mctrl |= TIOCM_OUT2; | |
1545 | ||
1546 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
55d3b282 RK |
1547 | |
1548 | /* | |
1549 | * Do a quick test to see if we receive an | |
1550 | * interrupt when we enable the TX irq. | |
1551 | */ | |
1552 | serial_outp(up, UART_IER, UART_IER_THRI); | |
1553 | lsr = serial_in(up, UART_LSR); | |
1554 | iir = serial_in(up, UART_IIR); | |
1555 | serial_outp(up, UART_IER, 0); | |
1556 | ||
1557 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { | |
67f7654e RK |
1558 | if (!(up->bugs & UART_BUG_TXEN)) { |
1559 | up->bugs |= UART_BUG_TXEN; | |
55d3b282 RK |
1560 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
1561 | port->line); | |
1562 | } | |
1563 | } else { | |
67f7654e | 1564 | up->bugs &= ~UART_BUG_TXEN; |
55d3b282 RK |
1565 | } |
1566 | ||
1da177e4 LT |
1567 | spin_unlock_irqrestore(&up->port.lock, flags); |
1568 | ||
1569 | /* | |
1570 | * Finally, enable interrupts. Note: Modem status interrupts | |
1571 | * are set via set_termios(), which will be occurring imminently | |
1572 | * anyway, so we don't enable them here. | |
1573 | */ | |
1574 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
1575 | serial_outp(up, UART_IER, up->ier); | |
1576 | ||
1577 | if (up->port.flags & UPF_FOURPORT) { | |
1578 | unsigned int icp; | |
1579 | /* | |
1580 | * Enable interrupts on the AST Fourport board | |
1581 | */ | |
1582 | icp = (up->port.iobase & 0xfe0) | 0x01f; | |
1583 | outb_p(0x80, icp); | |
1584 | (void) inb_p(icp); | |
1585 | } | |
1586 | ||
1587 | /* | |
1588 | * And clear the interrupt registers again for luck. | |
1589 | */ | |
1590 | (void) serial_inp(up, UART_LSR); | |
1591 | (void) serial_inp(up, UART_RX); | |
1592 | (void) serial_inp(up, UART_IIR); | |
1593 | (void) serial_inp(up, UART_MSR); | |
1594 | ||
1595 | return 0; | |
1596 | } | |
1597 | ||
1598 | static void serial8250_shutdown(struct uart_port *port) | |
1599 | { | |
1600 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1601 | unsigned long flags; | |
1602 | ||
1603 | /* | |
1604 | * Disable interrupts from this port | |
1605 | */ | |
1606 | up->ier = 0; | |
1607 | serial_outp(up, UART_IER, 0); | |
1608 | ||
1609 | spin_lock_irqsave(&up->port.lock, flags); | |
1610 | if (up->port.flags & UPF_FOURPORT) { | |
1611 | /* reset interrupts on the AST Fourport board */ | |
1612 | inb((up->port.iobase & 0xfe0) | 0x1f); | |
1613 | up->port.mctrl |= TIOCM_OUT1; | |
1614 | } else | |
1615 | up->port.mctrl &= ~TIOCM_OUT2; | |
1616 | ||
1617 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
1618 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1619 | ||
1620 | /* | |
1621 | * Disable break condition and FIFOs | |
1622 | */ | |
1623 | serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); | |
1624 | serial8250_clear_fifos(up); | |
1625 | ||
1626 | #ifdef CONFIG_SERIAL_8250_RSA | |
1627 | /* | |
1628 | * Reset the RSA board back to 115kbps compat mode. | |
1629 | */ | |
1630 | disable_rsa(up); | |
1631 | #endif | |
1632 | ||
1633 | /* | |
1634 | * Read data port to reset things, and then unlink from | |
1635 | * the IRQ chain. | |
1636 | */ | |
1637 | (void) serial_in(up, UART_RX); | |
1638 | ||
1639 | if (!is_real_interrupt(up->port.irq)) | |
1640 | del_timer_sync(&up->timer); | |
1641 | else | |
1642 | serial_unlink_irq_chain(up); | |
1643 | } | |
1644 | ||
1645 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) | |
1646 | { | |
1647 | unsigned int quot; | |
1648 | ||
1649 | /* | |
1650 | * Handle magic divisors for baud rates above baud_base on | |
1651 | * SMSC SuperIO chips. | |
1652 | */ | |
1653 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
1654 | baud == (port->uartclk/4)) | |
1655 | quot = 0x8001; | |
1656 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
1657 | baud == (port->uartclk/8)) | |
1658 | quot = 0x8002; | |
1659 | else | |
1660 | quot = uart_get_divisor(port, baud); | |
1661 | ||
1662 | return quot; | |
1663 | } | |
1664 | ||
1665 | static void | |
1666 | serial8250_set_termios(struct uart_port *port, struct termios *termios, | |
1667 | struct termios *old) | |
1668 | { | |
1669 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1670 | unsigned char cval, fcr = 0; | |
1671 | unsigned long flags; | |
1672 | unsigned int baud, quot; | |
1673 | ||
1674 | switch (termios->c_cflag & CSIZE) { | |
1675 | case CS5: | |
0a8b80c5 | 1676 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
1677 | break; |
1678 | case CS6: | |
0a8b80c5 | 1679 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
1680 | break; |
1681 | case CS7: | |
0a8b80c5 | 1682 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
1683 | break; |
1684 | default: | |
1685 | case CS8: | |
0a8b80c5 | 1686 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
1687 | break; |
1688 | } | |
1689 | ||
1690 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 1691 | cval |= UART_LCR_STOP; |
1da177e4 LT |
1692 | if (termios->c_cflag & PARENB) |
1693 | cval |= UART_LCR_PARITY; | |
1694 | if (!(termios->c_cflag & PARODD)) | |
1695 | cval |= UART_LCR_EPAR; | |
1696 | #ifdef CMSPAR | |
1697 | if (termios->c_cflag & CMSPAR) | |
1698 | cval |= UART_LCR_SPAR; | |
1699 | #endif | |
1700 | ||
1701 | /* | |
1702 | * Ask the core to calculate the divisor for us. | |
1703 | */ | |
1704 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
1705 | quot = serial8250_get_divisor(port, baud); | |
1706 | ||
1707 | /* | |
4ba5e35d | 1708 | * Oxford Semi 952 rev B workaround |
1da177e4 | 1709 | */ |
4ba5e35d | 1710 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
1da177e4 LT |
1711 | quot ++; |
1712 | ||
1713 | if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) { | |
1714 | if (baud < 2400) | |
1715 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; | |
1716 | else | |
1717 | fcr = uart_config[up->port.type].fcr; | |
1718 | } | |
1719 | ||
1720 | /* | |
1721 | * MCR-based auto flow control. When AFE is enabled, RTS will be | |
1722 | * deasserted when the receive FIFO contains more characters than | |
1723 | * the trigger, or the MCR RTS bit is cleared. In the case where | |
1724 | * the remote UART is not using CTS auto flow control, we must | |
1725 | * have sufficient FIFO entries for the latency of the remote | |
1726 | * UART to respond. IOW, at least 32 bytes of FIFO. | |
1727 | */ | |
1728 | if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { | |
1729 | up->mcr &= ~UART_MCR_AFE; | |
1730 | if (termios->c_cflag & CRTSCTS) | |
1731 | up->mcr |= UART_MCR_AFE; | |
1732 | } | |
1733 | ||
1734 | /* | |
1735 | * Ok, we're now changing the port state. Do it with | |
1736 | * interrupts disabled. | |
1737 | */ | |
1738 | spin_lock_irqsave(&up->port.lock, flags); | |
1739 | ||
1740 | /* | |
1741 | * Update the per-port timeout. | |
1742 | */ | |
1743 | uart_update_timeout(port, termios->c_cflag, baud); | |
1744 | ||
1745 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
1746 | if (termios->c_iflag & INPCK) | |
1747 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
1748 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
1749 | up->port.read_status_mask |= UART_LSR_BI; | |
1750 | ||
1751 | /* | |
1752 | * Characteres to ignore | |
1753 | */ | |
1754 | up->port.ignore_status_mask = 0; | |
1755 | if (termios->c_iflag & IGNPAR) | |
1756 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
1757 | if (termios->c_iflag & IGNBRK) { | |
1758 | up->port.ignore_status_mask |= UART_LSR_BI; | |
1759 | /* | |
1760 | * If we're ignoring parity and break indicators, | |
1761 | * ignore overruns too (for real raw support). | |
1762 | */ | |
1763 | if (termios->c_iflag & IGNPAR) | |
1764 | up->port.ignore_status_mask |= UART_LSR_OE; | |
1765 | } | |
1766 | ||
1767 | /* | |
1768 | * ignore all characters if CREAD is not set | |
1769 | */ | |
1770 | if ((termios->c_cflag & CREAD) == 0) | |
1771 | up->port.ignore_status_mask |= UART_LSR_DR; | |
1772 | ||
1773 | /* | |
1774 | * CTS flow control flag and modem status interrupts | |
1775 | */ | |
1776 | up->ier &= ~UART_IER_MSI; | |
1777 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
1778 | up->ier |= UART_IER_MSI; | |
1779 | if (up->capabilities & UART_CAP_UUE) | |
1780 | up->ier |= UART_IER_UUE | UART_IER_RTOIE; | |
1781 | ||
1782 | serial_out(up, UART_IER, up->ier); | |
1783 | ||
1784 | if (up->capabilities & UART_CAP_EFR) { | |
1785 | unsigned char efr = 0; | |
1786 | /* | |
1787 | * TI16C752/Startech hardware flow control. FIXME: | |
1788 | * - TI16C752 requires control thresholds to be set. | |
1789 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. | |
1790 | */ | |
1791 | if (termios->c_cflag & CRTSCTS) | |
1792 | efr |= UART_EFR_CTS; | |
1793 | ||
1794 | serial_outp(up, UART_LCR, 0xBF); | |
1795 | serial_outp(up, UART_EFR, efr); | |
1796 | } | |
1797 | ||
1798 | if (up->capabilities & UART_NATSEMI) { | |
1799 | /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ | |
1800 | serial_outp(up, UART_LCR, 0xe0); | |
1801 | } else { | |
1802 | serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ | |
1803 | } | |
1804 | ||
1805 | serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */ | |
1806 | serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */ | |
1807 | ||
1808 | /* | |
1809 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR | |
1810 | * is written without DLAB set, this mode will be disabled. | |
1811 | */ | |
1812 | if (up->port.type == PORT_16750) | |
1813 | serial_outp(up, UART_FCR, fcr); | |
1814 | ||
1815 | serial_outp(up, UART_LCR, cval); /* reset DLAB */ | |
1816 | up->lcr = cval; /* Save LCR */ | |
1817 | if (up->port.type != PORT_16750) { | |
1818 | if (fcr & UART_FCR_ENABLE_FIFO) { | |
1819 | /* emulated UARTs (Lucent Venus 167x) need two steps */ | |
1820 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1821 | } | |
1822 | serial_outp(up, UART_FCR, fcr); /* set fcr */ | |
1823 | } | |
1824 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
1825 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1826 | } | |
1827 | ||
1828 | static void | |
1829 | serial8250_pm(struct uart_port *port, unsigned int state, | |
1830 | unsigned int oldstate) | |
1831 | { | |
1832 | struct uart_8250_port *p = (struct uart_8250_port *)port; | |
1833 | ||
1834 | serial8250_set_sleep(p, state != 0); | |
1835 | ||
1836 | if (p->pm) | |
1837 | p->pm(port, state, oldstate); | |
1838 | } | |
1839 | ||
1840 | /* | |
1841 | * Resource handling. | |
1842 | */ | |
1843 | static int serial8250_request_std_resource(struct uart_8250_port *up) | |
1844 | { | |
1845 | unsigned int size = 8 << up->port.regshift; | |
1846 | int ret = 0; | |
1847 | ||
1848 | switch (up->port.iotype) { | |
1849 | case UPIO_MEM: | |
1850 | if (!up->port.mapbase) | |
1851 | break; | |
1852 | ||
1853 | if (!request_mem_region(up->port.mapbase, size, "serial")) { | |
1854 | ret = -EBUSY; | |
1855 | break; | |
1856 | } | |
1857 | ||
1858 | if (up->port.flags & UPF_IOREMAP) { | |
1859 | up->port.membase = ioremap(up->port.mapbase, size); | |
1860 | if (!up->port.membase) { | |
1861 | release_mem_region(up->port.mapbase, size); | |
1862 | ret = -ENOMEM; | |
1863 | } | |
1864 | } | |
1865 | break; | |
1866 | ||
1867 | case UPIO_HUB6: | |
1868 | case UPIO_PORT: | |
1869 | if (!request_region(up->port.iobase, size, "serial")) | |
1870 | ret = -EBUSY; | |
1871 | break; | |
1872 | } | |
1873 | return ret; | |
1874 | } | |
1875 | ||
1876 | static void serial8250_release_std_resource(struct uart_8250_port *up) | |
1877 | { | |
1878 | unsigned int size = 8 << up->port.regshift; | |
1879 | ||
1880 | switch (up->port.iotype) { | |
1881 | case UPIO_MEM: | |
1882 | if (!up->port.mapbase) | |
1883 | break; | |
1884 | ||
1885 | if (up->port.flags & UPF_IOREMAP) { | |
1886 | iounmap(up->port.membase); | |
1887 | up->port.membase = NULL; | |
1888 | } | |
1889 | ||
1890 | release_mem_region(up->port.mapbase, size); | |
1891 | break; | |
1892 | ||
1893 | case UPIO_HUB6: | |
1894 | case UPIO_PORT: | |
1895 | release_region(up->port.iobase, size); | |
1896 | break; | |
1897 | } | |
1898 | } | |
1899 | ||
1900 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) | |
1901 | { | |
1902 | unsigned long start = UART_RSA_BASE << up->port.regshift; | |
1903 | unsigned int size = 8 << up->port.regshift; | |
1904 | int ret = 0; | |
1905 | ||
1906 | switch (up->port.iotype) { | |
1907 | case UPIO_MEM: | |
1908 | ret = -EINVAL; | |
1909 | break; | |
1910 | ||
1911 | case UPIO_HUB6: | |
1912 | case UPIO_PORT: | |
1913 | start += up->port.iobase; | |
1914 | if (!request_region(start, size, "serial-rsa")) | |
1915 | ret = -EBUSY; | |
1916 | break; | |
1917 | } | |
1918 | ||
1919 | return ret; | |
1920 | } | |
1921 | ||
1922 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) | |
1923 | { | |
1924 | unsigned long offset = UART_RSA_BASE << up->port.regshift; | |
1925 | unsigned int size = 8 << up->port.regshift; | |
1926 | ||
1927 | switch (up->port.iotype) { | |
1928 | case UPIO_MEM: | |
1929 | break; | |
1930 | ||
1931 | case UPIO_HUB6: | |
1932 | case UPIO_PORT: | |
1933 | release_region(up->port.iobase + offset, size); | |
1934 | break; | |
1935 | } | |
1936 | } | |
1937 | ||
1938 | static void serial8250_release_port(struct uart_port *port) | |
1939 | { | |
1940 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1941 | ||
1942 | serial8250_release_std_resource(up); | |
1943 | if (up->port.type == PORT_RSA) | |
1944 | serial8250_release_rsa_resource(up); | |
1945 | } | |
1946 | ||
1947 | static int serial8250_request_port(struct uart_port *port) | |
1948 | { | |
1949 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1950 | int ret = 0; | |
1951 | ||
1952 | ret = serial8250_request_std_resource(up); | |
1953 | if (ret == 0 && up->port.type == PORT_RSA) { | |
1954 | ret = serial8250_request_rsa_resource(up); | |
1955 | if (ret < 0) | |
1956 | serial8250_release_std_resource(up); | |
1957 | } | |
1958 | ||
1959 | return ret; | |
1960 | } | |
1961 | ||
1962 | static void serial8250_config_port(struct uart_port *port, int flags) | |
1963 | { | |
1964 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1965 | int probeflags = PROBE_ANY; | |
1966 | int ret; | |
1967 | ||
1968 | /* | |
1969 | * Don't probe for MCA ports on non-MCA machines. | |
1970 | */ | |
1971 | if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus) | |
1972 | return; | |
1973 | ||
1974 | /* | |
1975 | * Find the region that we can probe for. This in turn | |
1976 | * tells us whether we can probe for the type of port. | |
1977 | */ | |
1978 | ret = serial8250_request_std_resource(up); | |
1979 | if (ret < 0) | |
1980 | return; | |
1981 | ||
1982 | ret = serial8250_request_rsa_resource(up); | |
1983 | if (ret < 0) | |
1984 | probeflags &= ~PROBE_RSA; | |
1985 | ||
1986 | if (flags & UART_CONFIG_TYPE) | |
1987 | autoconfig(up, probeflags); | |
1988 | if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) | |
1989 | autoconfig_irq(up); | |
1990 | ||
1991 | if (up->port.type != PORT_RSA && probeflags & PROBE_RSA) | |
1992 | serial8250_release_rsa_resource(up); | |
1993 | if (up->port.type == PORT_UNKNOWN) | |
1994 | serial8250_release_std_resource(up); | |
1995 | } | |
1996 | ||
1997 | static int | |
1998 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1999 | { | |
2000 | if (ser->irq >= NR_IRQS || ser->irq < 0 || | |
2001 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || | |
2002 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || | |
2003 | ser->type == PORT_STARTECH) | |
2004 | return -EINVAL; | |
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | static const char * | |
2009 | serial8250_type(struct uart_port *port) | |
2010 | { | |
2011 | int type = port->type; | |
2012 | ||
2013 | if (type >= ARRAY_SIZE(uart_config)) | |
2014 | type = 0; | |
2015 | return uart_config[type].name; | |
2016 | } | |
2017 | ||
2018 | static struct uart_ops serial8250_pops = { | |
2019 | .tx_empty = serial8250_tx_empty, | |
2020 | .set_mctrl = serial8250_set_mctrl, | |
2021 | .get_mctrl = serial8250_get_mctrl, | |
2022 | .stop_tx = serial8250_stop_tx, | |
2023 | .start_tx = serial8250_start_tx, | |
2024 | .stop_rx = serial8250_stop_rx, | |
2025 | .enable_ms = serial8250_enable_ms, | |
2026 | .break_ctl = serial8250_break_ctl, | |
2027 | .startup = serial8250_startup, | |
2028 | .shutdown = serial8250_shutdown, | |
2029 | .set_termios = serial8250_set_termios, | |
2030 | .pm = serial8250_pm, | |
2031 | .type = serial8250_type, | |
2032 | .release_port = serial8250_release_port, | |
2033 | .request_port = serial8250_request_port, | |
2034 | .config_port = serial8250_config_port, | |
2035 | .verify_port = serial8250_verify_port, | |
2036 | }; | |
2037 | ||
2038 | static struct uart_8250_port serial8250_ports[UART_NR]; | |
2039 | ||
2040 | static void __init serial8250_isa_init_ports(void) | |
2041 | { | |
2042 | struct uart_8250_port *up; | |
2043 | static int first = 1; | |
2044 | int i; | |
2045 | ||
2046 | if (!first) | |
2047 | return; | |
2048 | first = 0; | |
2049 | ||
2050 | for (i = 0; i < UART_NR; i++) { | |
2051 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2052 | ||
2053 | up->port.line = i; | |
2054 | spin_lock_init(&up->port.lock); | |
2055 | ||
2056 | init_timer(&up->timer); | |
2057 | up->timer.function = serial8250_timeout; | |
2058 | ||
2059 | /* | |
2060 | * ALPHA_KLUDGE_MCR needs to be killed. | |
2061 | */ | |
2062 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | |
2063 | up->mcr_force = ALPHA_KLUDGE_MCR; | |
2064 | ||
2065 | up->port.ops = &serial8250_pops; | |
2066 | } | |
2067 | ||
44454bcd RK |
2068 | for (i = 0, up = serial8250_ports; |
2069 | i < ARRAY_SIZE(old_serial_port) && i < UART_NR; | |
1da177e4 LT |
2070 | i++, up++) { |
2071 | up->port.iobase = old_serial_port[i].port; | |
2072 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); | |
2073 | up->port.uartclk = old_serial_port[i].baud_base * 16; | |
2074 | up->port.flags = old_serial_port[i].flags; | |
2075 | up->port.hub6 = old_serial_port[i].hub6; | |
2076 | up->port.membase = old_serial_port[i].iomem_base; | |
2077 | up->port.iotype = old_serial_port[i].io_type; | |
2078 | up->port.regshift = old_serial_port[i].iomem_reg_shift; | |
2079 | if (share_irqs) | |
2080 | up->port.flags |= UPF_SHARE_IRQ; | |
2081 | } | |
2082 | } | |
2083 | ||
2084 | static void __init | |
2085 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) | |
2086 | { | |
2087 | int i; | |
2088 | ||
2089 | serial8250_isa_init_ports(); | |
2090 | ||
2091 | for (i = 0; i < UART_NR; i++) { | |
2092 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2093 | ||
2094 | up->port.dev = dev; | |
2095 | uart_add_one_port(drv, &up->port); | |
2096 | } | |
2097 | } | |
2098 | ||
2099 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
2100 | ||
2101 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) | |
2102 | ||
2103 | /* | |
2104 | * Wait for transmitter & holding register to empty | |
2105 | */ | |
2106 | static inline void wait_for_xmitr(struct uart_8250_port *up) | |
2107 | { | |
2108 | unsigned int status, tmout = 10000; | |
2109 | ||
2110 | /* Wait up to 10ms for the character(s) to be sent. */ | |
2111 | do { | |
2112 | status = serial_in(up, UART_LSR); | |
2113 | ||
2114 | if (status & UART_LSR_BI) | |
2115 | up->lsr_break_flag = UART_LSR_BI; | |
2116 | ||
2117 | if (--tmout == 0) | |
2118 | break; | |
2119 | udelay(1); | |
2120 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
2121 | ||
2122 | /* Wait up to 1s for flow control if necessary */ | |
2123 | if (up->port.flags & UPF_CONS_FLOW) { | |
2124 | tmout = 1000000; | |
2125 | while (--tmout && | |
2126 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | |
2127 | udelay(1); | |
2128 | } | |
2129 | } | |
2130 | ||
2131 | /* | |
2132 | * Print a string to the serial port trying not to disturb | |
2133 | * any possible real use of the port... | |
2134 | * | |
2135 | * The console_lock must be held when we get here. | |
2136 | */ | |
2137 | static void | |
2138 | serial8250_console_write(struct console *co, const char *s, unsigned int count) | |
2139 | { | |
2140 | struct uart_8250_port *up = &serial8250_ports[co->index]; | |
2141 | unsigned int ier; | |
2142 | int i; | |
2143 | ||
2144 | /* | |
2145 | * First save the UER then disable the interrupts | |
2146 | */ | |
2147 | ier = serial_in(up, UART_IER); | |
2148 | ||
2149 | if (up->capabilities & UART_CAP_UUE) | |
2150 | serial_out(up, UART_IER, UART_IER_UUE); | |
2151 | else | |
2152 | serial_out(up, UART_IER, 0); | |
2153 | ||
2154 | /* | |
2155 | * Now, do each character | |
2156 | */ | |
2157 | for (i = 0; i < count; i++, s++) { | |
2158 | wait_for_xmitr(up); | |
2159 | ||
2160 | /* | |
2161 | * Send the character out. | |
2162 | * If a LF, also do CR... | |
2163 | */ | |
2164 | serial_out(up, UART_TX, *s); | |
2165 | if (*s == 10) { | |
2166 | wait_for_xmitr(up); | |
2167 | serial_out(up, UART_TX, 13); | |
2168 | } | |
2169 | } | |
2170 | ||
2171 | /* | |
2172 | * Finally, wait for transmitter to become empty | |
2173 | * and restore the IER | |
2174 | */ | |
2175 | wait_for_xmitr(up); | |
2176 | serial_out(up, UART_IER, ier); | |
2177 | } | |
2178 | ||
2179 | static int serial8250_console_setup(struct console *co, char *options) | |
2180 | { | |
2181 | struct uart_port *port; | |
2182 | int baud = 9600; | |
2183 | int bits = 8; | |
2184 | int parity = 'n'; | |
2185 | int flow = 'n'; | |
2186 | ||
2187 | /* | |
2188 | * Check whether an invalid uart number has been specified, and | |
2189 | * if so, search for the first available port that does have | |
2190 | * console support. | |
2191 | */ | |
2192 | if (co->index >= UART_NR) | |
2193 | co->index = 0; | |
2194 | port = &serial8250_ports[co->index].port; | |
2195 | if (!port->iobase && !port->membase) | |
2196 | return -ENODEV; | |
2197 | ||
2198 | if (options) | |
2199 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2200 | ||
2201 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2202 | } | |
2203 | ||
2204 | static struct uart_driver serial8250_reg; | |
2205 | static struct console serial8250_console = { | |
2206 | .name = "ttyS", | |
2207 | .write = serial8250_console_write, | |
2208 | .device = uart_console_device, | |
2209 | .setup = serial8250_console_setup, | |
2210 | .flags = CON_PRINTBUFFER, | |
2211 | .index = -1, | |
2212 | .data = &serial8250_reg, | |
2213 | }; | |
2214 | ||
2215 | static int __init serial8250_console_init(void) | |
2216 | { | |
2217 | serial8250_isa_init_ports(); | |
2218 | register_console(&serial8250_console); | |
2219 | return 0; | |
2220 | } | |
2221 | console_initcall(serial8250_console_init); | |
2222 | ||
2223 | static int __init find_port(struct uart_port *p) | |
2224 | { | |
2225 | int line; | |
2226 | struct uart_port *port; | |
2227 | ||
2228 | for (line = 0; line < UART_NR; line++) { | |
2229 | port = &serial8250_ports[line].port; | |
2230 | if (p->iotype == port->iotype && | |
2231 | p->iobase == port->iobase && | |
2232 | p->membase == port->membase) | |
2233 | return line; | |
2234 | } | |
2235 | return -ENODEV; | |
2236 | } | |
2237 | ||
2238 | int __init serial8250_start_console(struct uart_port *port, char *options) | |
2239 | { | |
2240 | int line; | |
2241 | ||
2242 | line = find_port(port); | |
2243 | if (line < 0) | |
2244 | return -ENODEV; | |
2245 | ||
2246 | add_preferred_console("ttyS", line, options); | |
2247 | printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n", | |
2248 | line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port", | |
2249 | port->iotype == UPIO_MEM ? (unsigned long) port->mapbase : | |
2250 | (unsigned long) port->iobase, options); | |
2251 | if (!(serial8250_console.flags & CON_ENABLED)) { | |
2252 | serial8250_console.flags &= ~CON_PRINTBUFFER; | |
2253 | register_console(&serial8250_console); | |
2254 | } | |
2255 | return line; | |
2256 | } | |
2257 | ||
2258 | #define SERIAL8250_CONSOLE &serial8250_console | |
2259 | #else | |
2260 | #define SERIAL8250_CONSOLE NULL | |
2261 | #endif | |
2262 | ||
2263 | static struct uart_driver serial8250_reg = { | |
2264 | .owner = THIS_MODULE, | |
2265 | .driver_name = "serial", | |
2266 | .devfs_name = "tts/", | |
2267 | .dev_name = "ttyS", | |
2268 | .major = TTY_MAJOR, | |
2269 | .minor = 64, | |
2270 | .nr = UART_NR, | |
2271 | .cons = SERIAL8250_CONSOLE, | |
2272 | }; | |
2273 | ||
2274 | int __init early_serial_setup(struct uart_port *port) | |
2275 | { | |
2276 | if (port->line >= ARRAY_SIZE(serial8250_ports)) | |
2277 | return -ENODEV; | |
2278 | ||
2279 | serial8250_isa_init_ports(); | |
2280 | serial8250_ports[port->line].port = *port; | |
2281 | serial8250_ports[port->line].port.ops = &serial8250_pops; | |
2282 | return 0; | |
2283 | } | |
2284 | ||
2285 | /** | |
2286 | * serial8250_suspend_port - suspend one serial port | |
2287 | * @line: serial line number | |
2288 | * @level: the level of port suspension, as per uart_suspend_port | |
2289 | * | |
2290 | * Suspend one serial port. | |
2291 | */ | |
2292 | void serial8250_suspend_port(int line) | |
2293 | { | |
2294 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); | |
2295 | } | |
2296 | ||
2297 | /** | |
2298 | * serial8250_resume_port - resume one serial port | |
2299 | * @line: serial line number | |
2300 | * @level: the level of port resumption, as per uart_resume_port | |
2301 | * | |
2302 | * Resume one serial port. | |
2303 | */ | |
2304 | void serial8250_resume_port(int line) | |
2305 | { | |
2306 | uart_resume_port(&serial8250_reg, &serial8250_ports[line].port); | |
2307 | } | |
2308 | ||
2309 | /* | |
2310 | * Register a set of serial devices attached to a platform device. The | |
2311 | * list is terminated with a zero flags entry, which means we expect | |
2312 | * all entries to have at least UPF_BOOT_AUTOCONF set. | |
2313 | */ | |
2314 | static int __devinit serial8250_probe(struct device *dev) | |
2315 | { | |
2316 | struct plat_serial8250_port *p = dev->platform_data; | |
2317 | struct uart_port port; | |
ec9f47cd | 2318 | int ret, i; |
1da177e4 LT |
2319 | |
2320 | memset(&port, 0, sizeof(struct uart_port)); | |
2321 | ||
ec9f47cd | 2322 | for (i = 0; p && p->flags != 0; p++, i++) { |
1da177e4 LT |
2323 | port.iobase = p->iobase; |
2324 | port.membase = p->membase; | |
2325 | port.irq = p->irq; | |
2326 | port.uartclk = p->uartclk; | |
2327 | port.regshift = p->regshift; | |
2328 | port.iotype = p->iotype; | |
2329 | port.flags = p->flags; | |
2330 | port.mapbase = p->mapbase; | |
ec9f47cd | 2331 | port.hub6 = p->hub6; |
1da177e4 LT |
2332 | port.dev = dev; |
2333 | if (share_irqs) | |
2334 | port.flags |= UPF_SHARE_IRQ; | |
ec9f47cd RK |
2335 | ret = serial8250_register_port(&port); |
2336 | if (ret < 0) { | |
2337 | dev_err(dev, "unable to register port at index %d " | |
2338 | "(IO%lx MEM%lx IRQ%d): %d\n", i, | |
2339 | p->iobase, p->mapbase, p->irq, ret); | |
2340 | } | |
1da177e4 LT |
2341 | } |
2342 | return 0; | |
2343 | } | |
2344 | ||
2345 | /* | |
2346 | * Remove serial ports registered against a platform device. | |
2347 | */ | |
2348 | static int __devexit serial8250_remove(struct device *dev) | |
2349 | { | |
2350 | int i; | |
2351 | ||
2352 | for (i = 0; i < UART_NR; i++) { | |
2353 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2354 | ||
2355 | if (up->port.dev == dev) | |
2356 | serial8250_unregister_port(i); | |
2357 | } | |
2358 | return 0; | |
2359 | } | |
2360 | ||
9480e307 | 2361 | static int serial8250_suspend(struct device *dev, pm_message_t state) |
1da177e4 LT |
2362 | { |
2363 | int i; | |
2364 | ||
1da177e4 LT |
2365 | for (i = 0; i < UART_NR; i++) { |
2366 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2367 | ||
2368 | if (up->port.type != PORT_UNKNOWN && up->port.dev == dev) | |
2369 | uart_suspend_port(&serial8250_reg, &up->port); | |
2370 | } | |
2371 | ||
2372 | return 0; | |
2373 | } | |
2374 | ||
9480e307 | 2375 | static int serial8250_resume(struct device *dev) |
1da177e4 LT |
2376 | { |
2377 | int i; | |
2378 | ||
1da177e4 LT |
2379 | for (i = 0; i < UART_NR; i++) { |
2380 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2381 | ||
2382 | if (up->port.type != PORT_UNKNOWN && up->port.dev == dev) | |
2383 | uart_resume_port(&serial8250_reg, &up->port); | |
2384 | } | |
2385 | ||
2386 | return 0; | |
2387 | } | |
2388 | ||
2389 | static struct device_driver serial8250_isa_driver = { | |
2390 | .name = "serial8250", | |
2391 | .bus = &platform_bus_type, | |
2392 | .probe = serial8250_probe, | |
2393 | .remove = __devexit_p(serial8250_remove), | |
2394 | .suspend = serial8250_suspend, | |
2395 | .resume = serial8250_resume, | |
2396 | }; | |
2397 | ||
2398 | /* | |
2399 | * This "device" covers _all_ ISA 8250-compatible serial devices listed | |
2400 | * in the table in include/asm/serial.h | |
2401 | */ | |
2402 | static struct platform_device *serial8250_isa_devs; | |
2403 | ||
2404 | /* | |
2405 | * serial8250_register_port and serial8250_unregister_port allows for | |
2406 | * 16x50 serial ports to be configured at run-time, to support PCMCIA | |
2407 | * modems and PCI multiport cards. | |
2408 | */ | |
2409 | static DECLARE_MUTEX(serial_sem); | |
2410 | ||
2411 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) | |
2412 | { | |
2413 | int i; | |
2414 | ||
2415 | /* | |
2416 | * First, find a port entry which matches. | |
2417 | */ | |
2418 | for (i = 0; i < UART_NR; i++) | |
2419 | if (uart_match_port(&serial8250_ports[i].port, port)) | |
2420 | return &serial8250_ports[i]; | |
2421 | ||
2422 | /* | |
2423 | * We didn't find a matching entry, so look for the first | |
2424 | * free entry. We look for one which hasn't been previously | |
2425 | * used (indicated by zero iobase). | |
2426 | */ | |
2427 | for (i = 0; i < UART_NR; i++) | |
2428 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && | |
2429 | serial8250_ports[i].port.iobase == 0) | |
2430 | return &serial8250_ports[i]; | |
2431 | ||
2432 | /* | |
2433 | * That also failed. Last resort is to find any entry which | |
2434 | * doesn't have a real port associated with it. | |
2435 | */ | |
2436 | for (i = 0; i < UART_NR; i++) | |
2437 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) | |
2438 | return &serial8250_ports[i]; | |
2439 | ||
2440 | return NULL; | |
2441 | } | |
2442 | ||
2443 | /** | |
2444 | * serial8250_register_port - register a serial port | |
2445 | * @port: serial port template | |
2446 | * | |
2447 | * Configure the serial port specified by the request. If the | |
2448 | * port exists and is in use, it is hung up and unregistered | |
2449 | * first. | |
2450 | * | |
2451 | * The port is then probed and if necessary the IRQ is autodetected | |
2452 | * If this fails an error is returned. | |
2453 | * | |
2454 | * On success the port is ready to use and the line number is returned. | |
2455 | */ | |
2456 | int serial8250_register_port(struct uart_port *port) | |
2457 | { | |
2458 | struct uart_8250_port *uart; | |
2459 | int ret = -ENOSPC; | |
2460 | ||
2461 | if (port->uartclk == 0) | |
2462 | return -EINVAL; | |
2463 | ||
2464 | down(&serial_sem); | |
2465 | ||
2466 | uart = serial8250_find_match_or_unused(port); | |
2467 | if (uart) { | |
2468 | uart_remove_one_port(&serial8250_reg, &uart->port); | |
2469 | ||
2470 | uart->port.iobase = port->iobase; | |
2471 | uart->port.membase = port->membase; | |
2472 | uart->port.irq = port->irq; | |
2473 | uart->port.uartclk = port->uartclk; | |
2474 | uart->port.fifosize = port->fifosize; | |
2475 | uart->port.regshift = port->regshift; | |
2476 | uart->port.iotype = port->iotype; | |
2477 | uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; | |
2478 | uart->port.mapbase = port->mapbase; | |
2479 | if (port->dev) | |
2480 | uart->port.dev = port->dev; | |
2481 | ||
2482 | ret = uart_add_one_port(&serial8250_reg, &uart->port); | |
2483 | if (ret == 0) | |
2484 | ret = uart->port.line; | |
2485 | } | |
2486 | up(&serial_sem); | |
2487 | ||
2488 | return ret; | |
2489 | } | |
2490 | EXPORT_SYMBOL(serial8250_register_port); | |
2491 | ||
2492 | /** | |
2493 | * serial8250_unregister_port - remove a 16x50 serial port at runtime | |
2494 | * @line: serial line number | |
2495 | * | |
2496 | * Remove one serial port. This may not be called from interrupt | |
2497 | * context. We hand the port back to the our control. | |
2498 | */ | |
2499 | void serial8250_unregister_port(int line) | |
2500 | { | |
2501 | struct uart_8250_port *uart = &serial8250_ports[line]; | |
2502 | ||
2503 | down(&serial_sem); | |
2504 | uart_remove_one_port(&serial8250_reg, &uart->port); | |
2505 | if (serial8250_isa_devs) { | |
2506 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; | |
2507 | uart->port.type = PORT_UNKNOWN; | |
2508 | uart->port.dev = &serial8250_isa_devs->dev; | |
2509 | uart_add_one_port(&serial8250_reg, &uart->port); | |
2510 | } else { | |
2511 | uart->port.dev = NULL; | |
2512 | } | |
2513 | up(&serial_sem); | |
2514 | } | |
2515 | EXPORT_SYMBOL(serial8250_unregister_port); | |
2516 | ||
2517 | static int __init serial8250_init(void) | |
2518 | { | |
2519 | int ret, i; | |
2520 | ||
2521 | printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ " | |
2522 | "%d ports, IRQ sharing %sabled\n", (int) UART_NR, | |
2523 | share_irqs ? "en" : "dis"); | |
2524 | ||
2525 | for (i = 0; i < NR_IRQS; i++) | |
2526 | spin_lock_init(&irq_lists[i].lock); | |
2527 | ||
2528 | ret = uart_register_driver(&serial8250_reg); | |
2529 | if (ret) | |
2530 | goto out; | |
2531 | ||
2532 | serial8250_isa_devs = platform_device_register_simple("serial8250", | |
6df29deb | 2533 | PLAT8250_DEV_LEGACY, NULL, 0); |
1da177e4 LT |
2534 | if (IS_ERR(serial8250_isa_devs)) { |
2535 | ret = PTR_ERR(serial8250_isa_devs); | |
2536 | goto unreg; | |
2537 | } | |
2538 | ||
2539 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); | |
2540 | ||
2541 | ret = driver_register(&serial8250_isa_driver); | |
2542 | if (ret == 0) | |
2543 | goto out; | |
2544 | ||
2545 | platform_device_unregister(serial8250_isa_devs); | |
2546 | unreg: | |
2547 | uart_unregister_driver(&serial8250_reg); | |
2548 | out: | |
2549 | return ret; | |
2550 | } | |
2551 | ||
2552 | static void __exit serial8250_exit(void) | |
2553 | { | |
2554 | struct platform_device *isa_dev = serial8250_isa_devs; | |
2555 | ||
2556 | /* | |
2557 | * This tells serial8250_unregister_port() not to re-register | |
2558 | * the ports (thereby making serial8250_isa_driver permanently | |
2559 | * in use.) | |
2560 | */ | |
2561 | serial8250_isa_devs = NULL; | |
2562 | ||
2563 | driver_unregister(&serial8250_isa_driver); | |
2564 | platform_device_unregister(isa_dev); | |
2565 | ||
2566 | uart_unregister_driver(&serial8250_reg); | |
2567 | } | |
2568 | ||
2569 | module_init(serial8250_init); | |
2570 | module_exit(serial8250_exit); | |
2571 | ||
2572 | EXPORT_SYMBOL(serial8250_suspend_port); | |
2573 | EXPORT_SYMBOL(serial8250_resume_port); | |
2574 | ||
2575 | MODULE_LICENSE("GPL"); | |
2576 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $"); | |
2577 | ||
2578 | module_param(share_irqs, uint, 0644); | |
2579 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" | |
2580 | " (unsafe)"); | |
2581 | ||
2582 | #ifdef CONFIG_SERIAL_8250_RSA | |
2583 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); | |
2584 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); | |
2585 | #endif | |
2586 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); |