Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/8250.c | |
3 | * | |
4 | * Driver for 8250/16550-type serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright (C) 2001 Russell King. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
1da177e4 LT |
15 | * A note about mapbase / membase |
16 | * | |
17 | * mapbase is the physical address of the IO port. | |
18 | * membase is an 'ioremapped' cookie. | |
19 | */ | |
1da177e4 LT |
20 | |
21 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
22 | #define SUPPORT_SYSRQ | |
23 | #endif | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/console.h> | |
30 | #include <linux/sysrq.h> | |
1da177e4 | 31 | #include <linux/delay.h> |
d052d1be | 32 | #include <linux/platform_device.h> |
1da177e4 LT |
33 | #include <linux/tty.h> |
34 | #include <linux/tty_flip.h> | |
35 | #include <linux/serial_reg.h> | |
36 | #include <linux/serial_core.h> | |
37 | #include <linux/serial.h> | |
38 | #include <linux/serial_8250.h> | |
78512ece | 39 | #include <linux/nmi.h> |
f392ecfa | 40 | #include <linux/mutex.h> |
1da177e4 LT |
41 | |
42 | #include <asm/io.h> | |
43 | #include <asm/irq.h> | |
44 | ||
45 | #include "8250.h" | |
46 | ||
b70ac771 DM |
47 | #ifdef CONFIG_SPARC |
48 | #include "suncore.h" | |
49 | #endif | |
50 | ||
1da177e4 LT |
51 | /* |
52 | * Configuration: | |
40663cc7 | 53 | * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option |
1da177e4 LT |
54 | * is unsafe when used on edge-triggered interrupts. |
55 | */ | |
408b664a | 56 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
1da177e4 | 57 | |
a61c2d78 DJ |
58 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; |
59 | ||
8440838b DM |
60 | static struct uart_driver serial8250_reg; |
61 | ||
62 | static int serial_index(struct uart_port *port) | |
63 | { | |
64 | return (serial8250_reg.minor - 64) + port->line; | |
65 | } | |
66 | ||
1da177e4 LT |
67 | /* |
68 | * Debugging. | |
69 | */ | |
70 | #if 0 | |
71 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
72 | #else | |
73 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
74 | #endif | |
75 | ||
76 | #if 0 | |
77 | #define DEBUG_INTR(fmt...) printk(fmt) | |
78 | #else | |
79 | #define DEBUG_INTR(fmt...) do { } while (0) | |
80 | #endif | |
81 | ||
82 | #define PASS_LIMIT 256 | |
83 | ||
84 | /* | |
85 | * We default to IRQ0 for the "no irq" hack. Some | |
86 | * machine types want others as well - they're free | |
87 | * to redefine this in their header file. | |
88 | */ | |
89 | #define is_real_interrupt(irq) ((irq) != 0) | |
90 | ||
1da177e4 LT |
91 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
92 | #define CONFIG_SERIAL_DETECT_IRQ 1 | |
93 | #endif | |
1da177e4 LT |
94 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
95 | #define CONFIG_SERIAL_MANY_PORTS 1 | |
96 | #endif | |
97 | ||
98 | /* | |
99 | * HUB6 is always on. This will be removed once the header | |
100 | * files have been cleaned. | |
101 | */ | |
102 | #define CONFIG_HUB6 1 | |
103 | ||
a4ed1e41 | 104 | #include <asm/serial.h> |
1da177e4 LT |
105 | /* |
106 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
107 | * standard enumeration mechanism. Platforms that can find all | |
108 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
109 | */ | |
110 | #ifndef SERIAL_PORT_DFNS | |
111 | #define SERIAL_PORT_DFNS | |
112 | #endif | |
113 | ||
cb3592be | 114 | static const struct old_serial_port old_serial_port[] = { |
1da177e4 LT |
115 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ |
116 | }; | |
117 | ||
026d02a2 | 118 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
1da177e4 LT |
119 | |
120 | #ifdef CONFIG_SERIAL_8250_RSA | |
121 | ||
122 | #define PORT_RSA_MAX 4 | |
123 | static unsigned long probe_rsa[PORT_RSA_MAX]; | |
124 | static unsigned int probe_rsa_count; | |
125 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
126 | ||
127 | struct uart_8250_port { | |
128 | struct uart_port port; | |
129 | struct timer_list timer; /* "no irq" timer */ | |
130 | struct list_head list; /* ports on this IRQ */ | |
4ba5e35d RK |
131 | unsigned short capabilities; /* port capabilities */ |
132 | unsigned short bugs; /* port bugs */ | |
1da177e4 | 133 | unsigned int tx_loadsz; /* transmit fifo load size */ |
1da177e4 LT |
134 | unsigned char acr; |
135 | unsigned char ier; | |
136 | unsigned char lcr; | |
137 | unsigned char mcr; | |
138 | unsigned char mcr_mask; /* mask of user bits */ | |
139 | unsigned char mcr_force; /* mask of forced bits */ | |
ad4c2aa6 CM |
140 | |
141 | /* | |
142 | * Some bits in registers are cleared on a read, so they must | |
143 | * be saved whenever the register is read but the bits will not | |
144 | * be immediately processed. | |
145 | */ | |
146 | #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS | |
147 | unsigned char lsr_saved_flags; | |
148 | #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA | |
149 | unsigned char msr_saved_flags; | |
1da177e4 LT |
150 | |
151 | /* | |
152 | * We provide a per-port pm hook. | |
153 | */ | |
154 | void (*pm)(struct uart_port *port, | |
155 | unsigned int state, unsigned int old); | |
156 | }; | |
157 | ||
158 | struct irq_info { | |
159 | spinlock_t lock; | |
160 | struct list_head *head; | |
161 | }; | |
162 | ||
163 | static struct irq_info irq_lists[NR_IRQS]; | |
164 | ||
165 | /* | |
166 | * Here we define the default xmit fifo size used for each type of UART. | |
167 | */ | |
168 | static const struct serial8250_config uart_config[] = { | |
169 | [PORT_UNKNOWN] = { | |
170 | .name = "unknown", | |
171 | .fifo_size = 1, | |
172 | .tx_loadsz = 1, | |
173 | }, | |
174 | [PORT_8250] = { | |
175 | .name = "8250", | |
176 | .fifo_size = 1, | |
177 | .tx_loadsz = 1, | |
178 | }, | |
179 | [PORT_16450] = { | |
180 | .name = "16450", | |
181 | .fifo_size = 1, | |
182 | .tx_loadsz = 1, | |
183 | }, | |
184 | [PORT_16550] = { | |
185 | .name = "16550", | |
186 | .fifo_size = 1, | |
187 | .tx_loadsz = 1, | |
188 | }, | |
189 | [PORT_16550A] = { | |
190 | .name = "16550A", | |
191 | .fifo_size = 16, | |
192 | .tx_loadsz = 16, | |
193 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
194 | .flags = UART_CAP_FIFO, | |
195 | }, | |
196 | [PORT_CIRRUS] = { | |
197 | .name = "Cirrus", | |
198 | .fifo_size = 1, | |
199 | .tx_loadsz = 1, | |
200 | }, | |
201 | [PORT_16650] = { | |
202 | .name = "ST16650", | |
203 | .fifo_size = 1, | |
204 | .tx_loadsz = 1, | |
205 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
206 | }, | |
207 | [PORT_16650V2] = { | |
208 | .name = "ST16650V2", | |
209 | .fifo_size = 32, | |
210 | .tx_loadsz = 16, | |
211 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
212 | UART_FCR_T_TRIG_00, | |
213 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
214 | }, | |
215 | [PORT_16750] = { | |
216 | .name = "TI16750", | |
217 | .fifo_size = 64, | |
218 | .tx_loadsz = 64, | |
219 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
220 | UART_FCR7_64BYTE, | |
221 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, | |
222 | }, | |
223 | [PORT_STARTECH] = { | |
224 | .name = "Startech", | |
225 | .fifo_size = 1, | |
226 | .tx_loadsz = 1, | |
227 | }, | |
228 | [PORT_16C950] = { | |
229 | .name = "16C950/954", | |
230 | .fifo_size = 128, | |
231 | .tx_loadsz = 128, | |
232 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
233 | .flags = UART_CAP_FIFO, | |
234 | }, | |
235 | [PORT_16654] = { | |
236 | .name = "ST16654", | |
237 | .fifo_size = 64, | |
238 | .tx_loadsz = 32, | |
239 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
240 | UART_FCR_T_TRIG_10, | |
241 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
242 | }, | |
243 | [PORT_16850] = { | |
244 | .name = "XR16850", | |
245 | .fifo_size = 128, | |
246 | .tx_loadsz = 128, | |
247 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
248 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
249 | }, | |
250 | [PORT_RSA] = { | |
251 | .name = "RSA", | |
252 | .fifo_size = 2048, | |
253 | .tx_loadsz = 2048, | |
254 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |
255 | .flags = UART_CAP_FIFO, | |
256 | }, | |
257 | [PORT_NS16550A] = { | |
258 | .name = "NS16550A", | |
259 | .fifo_size = 16, | |
260 | .tx_loadsz = 16, | |
261 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
262 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |
263 | }, | |
264 | [PORT_XSCALE] = { | |
265 | .name = "XScale", | |
266 | .fifo_size = 32, | |
267 | .tx_loadsz = 32, | |
268 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
269 | .flags = UART_CAP_FIFO | UART_CAP_UUE, | |
270 | }, | |
bd71c182 TK |
271 | [PORT_RM9000] = { |
272 | .name = "RM9000", | |
273 | .fifo_size = 16, | |
274 | .tx_loadsz = 16, | |
275 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
276 | .flags = UART_CAP_FIFO, | |
277 | }, | |
1da177e4 LT |
278 | }; |
279 | ||
bd71c182 | 280 | #if defined (CONFIG_SERIAL_8250_AU1X00) |
21c614a7 PA |
281 | |
282 | /* Au1x00 UART hardware has a weird register layout */ | |
283 | static const u8 au_io_in_map[] = { | |
284 | [UART_RX] = 0, | |
285 | [UART_IER] = 2, | |
286 | [UART_IIR] = 3, | |
287 | [UART_LCR] = 5, | |
288 | [UART_MCR] = 6, | |
289 | [UART_LSR] = 7, | |
290 | [UART_MSR] = 8, | |
291 | }; | |
292 | ||
293 | static const u8 au_io_out_map[] = { | |
294 | [UART_TX] = 1, | |
295 | [UART_IER] = 2, | |
296 | [UART_FCR] = 4, | |
297 | [UART_LCR] = 5, | |
298 | [UART_MCR] = 6, | |
299 | }; | |
300 | ||
301 | /* sane hardware needs no mapping */ | |
302 | static inline int map_8250_in_reg(struct uart_8250_port *up, int offset) | |
303 | { | |
304 | if (up->port.iotype != UPIO_AU) | |
305 | return offset; | |
306 | return au_io_in_map[offset]; | |
307 | } | |
308 | ||
309 | static inline int map_8250_out_reg(struct uart_8250_port *up, int offset) | |
310 | { | |
311 | if (up->port.iotype != UPIO_AU) | |
312 | return offset; | |
313 | return au_io_out_map[offset]; | |
314 | } | |
315 | ||
6f803cd0 | 316 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
bd71c182 TK |
317 | |
318 | static const u8 | |
319 | regmap_in[8] = { | |
320 | [UART_RX] = 0x00, | |
321 | [UART_IER] = 0x0c, | |
322 | [UART_IIR] = 0x14, | |
323 | [UART_LCR] = 0x1c, | |
324 | [UART_MCR] = 0x20, | |
325 | [UART_LSR] = 0x24, | |
326 | [UART_MSR] = 0x28, | |
327 | [UART_SCR] = 0x2c | |
328 | }, | |
329 | regmap_out[8] = { | |
330 | [UART_TX] = 0x04, | |
331 | [UART_IER] = 0x0c, | |
332 | [UART_FCR] = 0x18, | |
333 | [UART_LCR] = 0x1c, | |
334 | [UART_MCR] = 0x20, | |
335 | [UART_LSR] = 0x24, | |
336 | [UART_MSR] = 0x28, | |
337 | [UART_SCR] = 0x2c | |
338 | }; | |
339 | ||
340 | static inline int map_8250_in_reg(struct uart_8250_port *up, int offset) | |
341 | { | |
342 | if (up->port.iotype != UPIO_RM9000) | |
343 | return offset; | |
344 | return regmap_in[offset]; | |
345 | } | |
346 | ||
347 | static inline int map_8250_out_reg(struct uart_8250_port *up, int offset) | |
348 | { | |
349 | if (up->port.iotype != UPIO_RM9000) | |
350 | return offset; | |
351 | return regmap_out[offset]; | |
352 | } | |
353 | ||
21c614a7 PA |
354 | #else |
355 | ||
356 | /* sane hardware needs no mapping */ | |
357 | #define map_8250_in_reg(up, offset) (offset) | |
358 | #define map_8250_out_reg(up, offset) (offset) | |
359 | ||
360 | #endif | |
361 | ||
ea8874dc | 362 | static unsigned int serial_in(struct uart_8250_port *up, int offset) |
1da177e4 | 363 | { |
3be91ec7 | 364 | unsigned int tmp; |
21c614a7 | 365 | offset = map_8250_in_reg(up, offset) << up->port.regshift; |
1da177e4 LT |
366 | |
367 | switch (up->port.iotype) { | |
368 | case UPIO_HUB6: | |
369 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |
370 | return inb(up->port.iobase + 1); | |
371 | ||
372 | case UPIO_MEM: | |
beab697a | 373 | case UPIO_DWAPB: |
1da177e4 LT |
374 | return readb(up->port.membase + offset); |
375 | ||
bd71c182 | 376 | case UPIO_RM9000: |
1da177e4 LT |
377 | case UPIO_MEM32: |
378 | return readl(up->port.membase + offset); | |
379 | ||
21c614a7 PA |
380 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
381 | case UPIO_AU: | |
382 | return __raw_readl(up->port.membase + offset); | |
383 | #endif | |
384 | ||
3be91ec7 ZR |
385 | case UPIO_TSI: |
386 | if (offset == UART_IIR) { | |
9e84b60e AV |
387 | tmp = readl(up->port.membase + (UART_IIR & ~3)); |
388 | return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */ | |
3be91ec7 ZR |
389 | } else |
390 | return readb(up->port.membase + offset); | |
391 | ||
1da177e4 LT |
392 | default: |
393 | return inb(up->port.iobase + offset); | |
394 | } | |
395 | } | |
396 | ||
ea8874dc | 397 | static void |
1da177e4 LT |
398 | serial_out(struct uart_8250_port *up, int offset, int value) |
399 | { | |
beab697a MSJ |
400 | /* Save the offset before it's remapped */ |
401 | int save_offset = offset; | |
21c614a7 | 402 | offset = map_8250_out_reg(up, offset) << up->port.regshift; |
1da177e4 LT |
403 | |
404 | switch (up->port.iotype) { | |
405 | case UPIO_HUB6: | |
406 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |
407 | outb(value, up->port.iobase + 1); | |
408 | break; | |
409 | ||
410 | case UPIO_MEM: | |
411 | writeb(value, up->port.membase + offset); | |
412 | break; | |
413 | ||
bd71c182 | 414 | case UPIO_RM9000: |
1da177e4 LT |
415 | case UPIO_MEM32: |
416 | writel(value, up->port.membase + offset); | |
417 | break; | |
418 | ||
21c614a7 PA |
419 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
420 | case UPIO_AU: | |
421 | __raw_writel(value, up->port.membase + offset); | |
422 | break; | |
423 | #endif | |
3be91ec7 ZR |
424 | case UPIO_TSI: |
425 | if (!((offset == UART_IER) && (value & UART_IER_UUE))) | |
426 | writeb(value, up->port.membase + offset); | |
427 | break; | |
21c614a7 | 428 | |
beab697a MSJ |
429 | case UPIO_DWAPB: |
430 | /* Save the LCR value so it can be re-written when a | |
431 | * Busy Detect interrupt occurs. */ | |
432 | if (save_offset == UART_LCR) | |
433 | up->lcr = value; | |
434 | writeb(value, up->port.membase + offset); | |
435 | /* Read the IER to ensure any interrupt is cleared before | |
436 | * returning from ISR. */ | |
437 | if (save_offset == UART_TX || save_offset == UART_IER) | |
438 | value = serial_in(up, UART_IER); | |
439 | break; | |
440 | ||
1da177e4 LT |
441 | default: |
442 | outb(value, up->port.iobase + offset); | |
443 | } | |
444 | } | |
445 | ||
40b36daa AW |
446 | static void |
447 | serial_out_sync(struct uart_8250_port *up, int offset, int value) | |
448 | { | |
449 | switch (up->port.iotype) { | |
450 | case UPIO_MEM: | |
451 | case UPIO_MEM32: | |
452 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |
453 | case UPIO_AU: | |
454 | #endif | |
beab697a | 455 | case UPIO_DWAPB: |
40b36daa AW |
456 | serial_out(up, offset, value); |
457 | serial_in(up, UART_LCR); /* safe, no side-effects */ | |
458 | break; | |
459 | default: | |
460 | serial_out(up, offset, value); | |
461 | } | |
462 | } | |
463 | ||
1da177e4 LT |
464 | /* |
465 | * We used to support using pause I/O for certain machines. We | |
466 | * haven't supported this for a while, but just in case it's badly | |
467 | * needed for certain old 386 machines, I've left these #define's | |
468 | * in.... | |
469 | */ | |
470 | #define serial_inp(up, offset) serial_in(up, offset) | |
471 | #define serial_outp(up, offset, value) serial_out(up, offset, value) | |
472 | ||
b32b19b8 JAH |
473 | /* Uart divisor latch read */ |
474 | static inline int _serial_dl_read(struct uart_8250_port *up) | |
475 | { | |
476 | return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; | |
477 | } | |
478 | ||
479 | /* Uart divisor latch write */ | |
480 | static inline void _serial_dl_write(struct uart_8250_port *up, int value) | |
481 | { | |
482 | serial_outp(up, UART_DLL, value & 0xff); | |
483 | serial_outp(up, UART_DLM, value >> 8 & 0xff); | |
484 | } | |
485 | ||
6f803cd0 | 486 | #if defined(CONFIG_SERIAL_8250_AU1X00) |
b32b19b8 JAH |
487 | /* Au1x00 haven't got a standard divisor latch */ |
488 | static int serial_dl_read(struct uart_8250_port *up) | |
489 | { | |
490 | if (up->port.iotype == UPIO_AU) | |
491 | return __raw_readl(up->port.membase + 0x28); | |
492 | else | |
493 | return _serial_dl_read(up); | |
494 | } | |
495 | ||
496 | static void serial_dl_write(struct uart_8250_port *up, int value) | |
497 | { | |
498 | if (up->port.iotype == UPIO_AU) | |
499 | __raw_writel(value, up->port.membase + 0x28); | |
500 | else | |
501 | _serial_dl_write(up, value); | |
502 | } | |
6f803cd0 | 503 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
bd71c182 TK |
504 | static int serial_dl_read(struct uart_8250_port *up) |
505 | { | |
506 | return (up->port.iotype == UPIO_RM9000) ? | |
507 | (((__raw_readl(up->port.membase + 0x10) << 8) | | |
508 | (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) : | |
509 | _serial_dl_read(up); | |
510 | } | |
511 | ||
512 | static void serial_dl_write(struct uart_8250_port *up, int value) | |
513 | { | |
514 | if (up->port.iotype == UPIO_RM9000) { | |
515 | __raw_writel(value, up->port.membase + 0x08); | |
516 | __raw_writel(value >> 8, up->port.membase + 0x10); | |
517 | } else { | |
518 | _serial_dl_write(up, value); | |
519 | } | |
520 | } | |
b32b19b8 JAH |
521 | #else |
522 | #define serial_dl_read(up) _serial_dl_read(up) | |
523 | #define serial_dl_write(up, value) _serial_dl_write(up, value) | |
524 | #endif | |
1da177e4 LT |
525 | |
526 | /* | |
527 | * For the 16C950 | |
528 | */ | |
529 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) | |
530 | { | |
531 | serial_out(up, UART_SCR, offset); | |
532 | serial_out(up, UART_ICR, value); | |
533 | } | |
534 | ||
535 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) | |
536 | { | |
537 | unsigned int value; | |
538 | ||
539 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
540 | serial_out(up, UART_SCR, offset); | |
541 | value = serial_in(up, UART_ICR); | |
542 | serial_icr_write(up, UART_ACR, up->acr); | |
543 | ||
544 | return value; | |
545 | } | |
546 | ||
547 | /* | |
548 | * FIFO support. | |
549 | */ | |
b5d674ab | 550 | static void serial8250_clear_fifos(struct uart_8250_port *p) |
1da177e4 LT |
551 | { |
552 | if (p->capabilities & UART_CAP_FIFO) { | |
553 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); | |
554 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |
555 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
556 | serial_outp(p, UART_FCR, 0); | |
557 | } | |
558 | } | |
559 | ||
560 | /* | |
561 | * IER sleep support. UARTs which have EFRs need the "extended | |
562 | * capability" bit enabled. Note that on XR16C850s, we need to | |
563 | * reset LCR to write to IER. | |
564 | */ | |
b5d674ab | 565 | static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) |
1da177e4 LT |
566 | { |
567 | if (p->capabilities & UART_CAP_SLEEP) { | |
568 | if (p->capabilities & UART_CAP_EFR) { | |
569 | serial_outp(p, UART_LCR, 0xBF); | |
570 | serial_outp(p, UART_EFR, UART_EFR_ECB); | |
571 | serial_outp(p, UART_LCR, 0); | |
572 | } | |
573 | serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); | |
574 | if (p->capabilities & UART_CAP_EFR) { | |
575 | serial_outp(p, UART_LCR, 0xBF); | |
576 | serial_outp(p, UART_EFR, 0); | |
577 | serial_outp(p, UART_LCR, 0); | |
578 | } | |
579 | } | |
580 | } | |
581 | ||
582 | #ifdef CONFIG_SERIAL_8250_RSA | |
583 | /* | |
584 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
585 | * We set the port uart clock rate if we succeed. | |
586 | */ | |
587 | static int __enable_rsa(struct uart_8250_port *up) | |
588 | { | |
589 | unsigned char mode; | |
590 | int result; | |
591 | ||
592 | mode = serial_inp(up, UART_RSA_MSR); | |
593 | result = mode & UART_RSA_MSR_FIFO; | |
594 | ||
595 | if (!result) { | |
596 | serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); | |
597 | mode = serial_inp(up, UART_RSA_MSR); | |
598 | result = mode & UART_RSA_MSR_FIFO; | |
599 | } | |
600 | ||
601 | if (result) | |
602 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
603 | ||
604 | return result; | |
605 | } | |
606 | ||
607 | static void enable_rsa(struct uart_8250_port *up) | |
608 | { | |
609 | if (up->port.type == PORT_RSA) { | |
610 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
611 | spin_lock_irq(&up->port.lock); | |
612 | __enable_rsa(up); | |
613 | spin_unlock_irq(&up->port.lock); | |
614 | } | |
615 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
616 | serial_outp(up, UART_RSA_FRR, 0); | |
617 | } | |
618 | } | |
619 | ||
620 | /* | |
621 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
622 | * It is unknown why interrupts were disabled in here. However, | |
623 | * the caller is expected to preserve this behaviour by grabbing | |
624 | * the spinlock before calling this function. | |
625 | */ | |
626 | static void disable_rsa(struct uart_8250_port *up) | |
627 | { | |
628 | unsigned char mode; | |
629 | int result; | |
630 | ||
631 | if (up->port.type == PORT_RSA && | |
632 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
633 | spin_lock_irq(&up->port.lock); | |
634 | ||
635 | mode = serial_inp(up, UART_RSA_MSR); | |
636 | result = !(mode & UART_RSA_MSR_FIFO); | |
637 | ||
638 | if (!result) { | |
639 | serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); | |
640 | mode = serial_inp(up, UART_RSA_MSR); | |
641 | result = !(mode & UART_RSA_MSR_FIFO); | |
642 | } | |
643 | ||
644 | if (result) | |
645 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
646 | spin_unlock_irq(&up->port.lock); | |
647 | } | |
648 | } | |
649 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
650 | ||
651 | /* | |
652 | * This is a quickie test to see how big the FIFO is. | |
653 | * It doesn't work at all the time, more's the pity. | |
654 | */ | |
655 | static int size_fifo(struct uart_8250_port *up) | |
656 | { | |
b32b19b8 JAH |
657 | unsigned char old_fcr, old_mcr, old_lcr; |
658 | unsigned short old_dl; | |
1da177e4 LT |
659 | int count; |
660 | ||
661 | old_lcr = serial_inp(up, UART_LCR); | |
662 | serial_outp(up, UART_LCR, 0); | |
663 | old_fcr = serial_inp(up, UART_FCR); | |
664 | old_mcr = serial_inp(up, UART_MCR); | |
665 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
666 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
667 | serial_outp(up, UART_MCR, UART_MCR_LOOP); | |
668 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
b32b19b8 JAH |
669 | old_dl = serial_dl_read(up); |
670 | serial_dl_write(up, 0x0001); | |
1da177e4 LT |
671 | serial_outp(up, UART_LCR, 0x03); |
672 | for (count = 0; count < 256; count++) | |
673 | serial_outp(up, UART_TX, count); | |
674 | mdelay(20);/* FIXME - schedule_timeout */ | |
675 | for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && | |
676 | (count < 256); count++) | |
677 | serial_inp(up, UART_RX); | |
678 | serial_outp(up, UART_FCR, old_fcr); | |
679 | serial_outp(up, UART_MCR, old_mcr); | |
680 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
b32b19b8 | 681 | serial_dl_write(up, old_dl); |
1da177e4 LT |
682 | serial_outp(up, UART_LCR, old_lcr); |
683 | ||
684 | return count; | |
685 | } | |
686 | ||
687 | /* | |
688 | * Read UART ID using the divisor method - set DLL and DLM to zero | |
689 | * and the revision will be in DLL and device type in DLM. We | |
690 | * preserve the device state across this. | |
691 | */ | |
692 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) | |
693 | { | |
694 | unsigned char old_dll, old_dlm, old_lcr; | |
695 | unsigned int id; | |
696 | ||
697 | old_lcr = serial_inp(p, UART_LCR); | |
698 | serial_outp(p, UART_LCR, UART_LCR_DLAB); | |
699 | ||
700 | old_dll = serial_inp(p, UART_DLL); | |
701 | old_dlm = serial_inp(p, UART_DLM); | |
702 | ||
703 | serial_outp(p, UART_DLL, 0); | |
704 | serial_outp(p, UART_DLM, 0); | |
705 | ||
706 | id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; | |
707 | ||
708 | serial_outp(p, UART_DLL, old_dll); | |
709 | serial_outp(p, UART_DLM, old_dlm); | |
710 | serial_outp(p, UART_LCR, old_lcr); | |
711 | ||
712 | return id; | |
713 | } | |
714 | ||
715 | /* | |
716 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |
717 | * When this function is called we know it is at least a StarTech | |
718 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |
719 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |
720 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |
721 | * existence.) | |
bd71c182 | 722 | * |
1da177e4 LT |
723 | * What evil have men's minds wrought... |
724 | */ | |
725 | static void autoconfig_has_efr(struct uart_8250_port *up) | |
726 | { | |
727 | unsigned int id1, id2, id3, rev; | |
728 | ||
729 | /* | |
730 | * Everything with an EFR has SLEEP | |
731 | */ | |
732 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
733 | ||
734 | /* | |
735 | * First we check to see if it's an Oxford Semiconductor UART. | |
736 | * | |
737 | * If we have to do this here because some non-National | |
738 | * Semiconductor clone chips lock up if you try writing to the | |
739 | * LSR register (which serial_icr_read does) | |
740 | */ | |
741 | ||
742 | /* | |
743 | * Check for Oxford Semiconductor 16C950. | |
744 | * | |
745 | * EFR [4] must be set else this test fails. | |
746 | * | |
747 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |
748 | * claims that it's needed for 952 dual UART's (which are not | |
749 | * recommended for new designs). | |
750 | */ | |
751 | up->acr = 0; | |
752 | serial_out(up, UART_LCR, 0xBF); | |
753 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
754 | serial_out(up, UART_LCR, 0x00); | |
755 | id1 = serial_icr_read(up, UART_ID1); | |
756 | id2 = serial_icr_read(up, UART_ID2); | |
757 | id3 = serial_icr_read(up, UART_ID3); | |
758 | rev = serial_icr_read(up, UART_REV); | |
759 | ||
760 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); | |
761 | ||
762 | if (id1 == 0x16 && id2 == 0xC9 && | |
763 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { | |
764 | up->port.type = PORT_16C950; | |
4ba5e35d RK |
765 | |
766 | /* | |
767 | * Enable work around for the Oxford Semiconductor 952 rev B | |
768 | * chip which causes it to seriously miscalculate baud rates | |
769 | * when DLL is 0. | |
770 | */ | |
771 | if (id3 == 0x52 && rev == 0x01) | |
772 | up->bugs |= UART_BUG_QUOT; | |
1da177e4 LT |
773 | return; |
774 | } | |
bd71c182 | 775 | |
1da177e4 LT |
776 | /* |
777 | * We check for a XR16C850 by setting DLL and DLM to 0, and then | |
778 | * reading back DLL and DLM. The chip type depends on the DLM | |
779 | * value read back: | |
780 | * 0x10 - XR16C850 and the DLL contains the chip revision. | |
781 | * 0x12 - XR16C2850. | |
782 | * 0x14 - XR16C854. | |
783 | */ | |
784 | id1 = autoconfig_read_divisor_id(up); | |
785 | DEBUG_AUTOCONF("850id=%04x ", id1); | |
786 | ||
787 | id2 = id1 >> 8; | |
788 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { | |
1da177e4 LT |
789 | up->port.type = PORT_16850; |
790 | return; | |
791 | } | |
792 | ||
793 | /* | |
794 | * It wasn't an XR16C850. | |
795 | * | |
796 | * We distinguish between the '654 and the '650 by counting | |
797 | * how many bytes are in the FIFO. I'm using this for now, | |
798 | * since that's the technique that was sent to me in the | |
799 | * serial driver update, but I'm not convinced this works. | |
800 | * I've had problems doing this in the past. -TYT | |
801 | */ | |
802 | if (size_fifo(up) == 64) | |
803 | up->port.type = PORT_16654; | |
804 | else | |
805 | up->port.type = PORT_16650V2; | |
806 | } | |
807 | ||
808 | /* | |
809 | * We detected a chip without a FIFO. Only two fall into | |
810 | * this category - the original 8250 and the 16450. The | |
811 | * 16450 has a scratch register (accessible with LCR=0) | |
812 | */ | |
813 | static void autoconfig_8250(struct uart_8250_port *up) | |
814 | { | |
815 | unsigned char scratch, status1, status2; | |
816 | ||
817 | up->port.type = PORT_8250; | |
818 | ||
819 | scratch = serial_in(up, UART_SCR); | |
820 | serial_outp(up, UART_SCR, 0xa5); | |
821 | status1 = serial_in(up, UART_SCR); | |
822 | serial_outp(up, UART_SCR, 0x5a); | |
823 | status2 = serial_in(up, UART_SCR); | |
824 | serial_outp(up, UART_SCR, scratch); | |
825 | ||
826 | if (status1 == 0xa5 && status2 == 0x5a) | |
827 | up->port.type = PORT_16450; | |
828 | } | |
829 | ||
830 | static int broken_efr(struct uart_8250_port *up) | |
831 | { | |
832 | /* | |
833 | * Exar ST16C2550 "A2" devices incorrectly detect as | |
834 | * having an EFR, and report an ID of 0x0201. See | |
835 | * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf | |
836 | */ | |
837 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | |
838 | return 1; | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
843 | /* | |
844 | * We know that the chip has FIFOs. Does it have an EFR? The | |
845 | * EFR is located in the same register position as the IIR and | |
846 | * we know the top two bits of the IIR are currently set. The | |
847 | * EFR should contain zero. Try to read the EFR. | |
848 | */ | |
849 | static void autoconfig_16550a(struct uart_8250_port *up) | |
850 | { | |
851 | unsigned char status1, status2; | |
852 | unsigned int iersave; | |
853 | ||
854 | up->port.type = PORT_16550A; | |
855 | up->capabilities |= UART_CAP_FIFO; | |
856 | ||
857 | /* | |
858 | * Check for presence of the EFR when DLAB is set. | |
859 | * Only ST16C650V1 UARTs pass this test. | |
860 | */ | |
861 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
862 | if (serial_in(up, UART_EFR) == 0) { | |
863 | serial_outp(up, UART_EFR, 0xA8); | |
864 | if (serial_in(up, UART_EFR) != 0) { | |
865 | DEBUG_AUTOCONF("EFRv1 "); | |
866 | up->port.type = PORT_16650; | |
867 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
868 | } else { | |
869 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); | |
870 | } | |
871 | serial_outp(up, UART_EFR, 0); | |
872 | return; | |
873 | } | |
874 | ||
875 | /* | |
876 | * Maybe it requires 0xbf to be written to the LCR. | |
877 | * (other ST16C650V2 UARTs, TI16C752A, etc) | |
878 | */ | |
879 | serial_outp(up, UART_LCR, 0xBF); | |
880 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { | |
881 | DEBUG_AUTOCONF("EFRv2 "); | |
882 | autoconfig_has_efr(up); | |
883 | return; | |
884 | } | |
885 | ||
886 | /* | |
887 | * Check for a National Semiconductor SuperIO chip. | |
888 | * Attempt to switch to bank 2, read the value of the LOOP bit | |
889 | * from EXCR1. Switch back to bank 0, change it in MCR. Then | |
890 | * switch back to bank 2, read it from EXCR1 again and check | |
891 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 | |
1da177e4 LT |
892 | */ |
893 | serial_outp(up, UART_LCR, 0); | |
894 | status1 = serial_in(up, UART_MCR); | |
895 | serial_outp(up, UART_LCR, 0xE0); | |
896 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
897 | ||
898 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { | |
899 | serial_outp(up, UART_LCR, 0); | |
900 | serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP); | |
901 | serial_outp(up, UART_LCR, 0xE0); | |
902 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
903 | serial_outp(up, UART_LCR, 0); | |
904 | serial_outp(up, UART_MCR, status1); | |
905 | ||
906 | if ((status2 ^ status1) & UART_MCR_LOOP) { | |
857dde2e DW |
907 | unsigned short quot; |
908 | ||
1da177e4 | 909 | serial_outp(up, UART_LCR, 0xE0); |
857dde2e | 910 | |
b32b19b8 | 911 | quot = serial_dl_read(up); |
857dde2e DW |
912 | quot <<= 3; |
913 | ||
b5b82df6 | 914 | status1 = serial_in(up, 0x04); /* EXCR2 */ |
1da177e4 LT |
915 | status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ |
916 | status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
917 | serial_outp(up, 0x04, status1); | |
bd71c182 | 918 | |
b32b19b8 | 919 | serial_dl_write(up, quot); |
857dde2e | 920 | |
1da177e4 | 921 | serial_outp(up, UART_LCR, 0); |
1da177e4 | 922 | |
857dde2e | 923 | up->port.uartclk = 921600*16; |
1da177e4 LT |
924 | up->port.type = PORT_NS16550A; |
925 | up->capabilities |= UART_NATSEMI; | |
926 | return; | |
927 | } | |
928 | } | |
929 | ||
930 | /* | |
931 | * No EFR. Try to detect a TI16750, which only sets bit 5 of | |
932 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. | |
933 | * Try setting it with and without DLAB set. Cheap clones | |
934 | * set bit 5 without DLAB set. | |
935 | */ | |
936 | serial_outp(up, UART_LCR, 0); | |
937 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
938 | status1 = serial_in(up, UART_IIR) >> 5; | |
939 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
940 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
941 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
942 | status2 = serial_in(up, UART_IIR) >> 5; | |
943 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
944 | serial_outp(up, UART_LCR, 0); | |
945 | ||
946 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); | |
947 | ||
948 | if (status1 == 6 && status2 == 7) { | |
949 | up->port.type = PORT_16750; | |
950 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; | |
951 | return; | |
952 | } | |
953 | ||
954 | /* | |
955 | * Try writing and reading the UART_IER_UUE bit (b6). | |
956 | * If it works, this is probably one of the Xscale platform's | |
957 | * internal UARTs. | |
958 | * We're going to explicitly set the UUE bit to 0 before | |
959 | * trying to write and read a 1 just to make sure it's not | |
960 | * already a 1 and maybe locked there before we even start start. | |
961 | */ | |
962 | iersave = serial_in(up, UART_IER); | |
963 | serial_outp(up, UART_IER, iersave & ~UART_IER_UUE); | |
964 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { | |
965 | /* | |
966 | * OK it's in a known zero state, try writing and reading | |
967 | * without disturbing the current state of the other bits. | |
968 | */ | |
969 | serial_outp(up, UART_IER, iersave | UART_IER_UUE); | |
970 | if (serial_in(up, UART_IER) & UART_IER_UUE) { | |
971 | /* | |
972 | * It's an Xscale. | |
973 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). | |
974 | */ | |
975 | DEBUG_AUTOCONF("Xscale "); | |
976 | up->port.type = PORT_XSCALE; | |
977 | up->capabilities |= UART_CAP_UUE; | |
978 | return; | |
979 | } | |
980 | } else { | |
981 | /* | |
982 | * If we got here we couldn't force the IER_UUE bit to 0. | |
983 | * Log it and continue. | |
984 | */ | |
985 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); | |
986 | } | |
987 | serial_outp(up, UART_IER, iersave); | |
988 | } | |
989 | ||
990 | /* | |
991 | * This routine is called by rs_init() to initialize a specific serial | |
992 | * port. It determines what type of UART chip this serial port is | |
993 | * using: 8250, 16450, 16550, 16550A. The important question is | |
994 | * whether or not this UART is a 16550A or not, since this will | |
995 | * determine whether or not we can use its FIFO features or not. | |
996 | */ | |
997 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | |
998 | { | |
999 | unsigned char status1, scratch, scratch2, scratch3; | |
1000 | unsigned char save_lcr, save_mcr; | |
1001 | unsigned long flags; | |
1002 | ||
1003 | if (!up->port.iobase && !up->port.mapbase && !up->port.membase) | |
1004 | return; | |
1005 | ||
1006 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ", | |
8440838b | 1007 | serial_index(&up->port), up->port.iobase, up->port.membase); |
1da177e4 LT |
1008 | |
1009 | /* | |
1010 | * We really do need global IRQs disabled here - we're going to | |
1011 | * be frobbing the chips IRQ enable register to see if it exists. | |
1012 | */ | |
1013 | spin_lock_irqsave(&up->port.lock, flags); | |
1da177e4 LT |
1014 | |
1015 | up->capabilities = 0; | |
4ba5e35d | 1016 | up->bugs = 0; |
1da177e4 LT |
1017 | |
1018 | if (!(up->port.flags & UPF_BUGGY_UART)) { | |
1019 | /* | |
1020 | * Do a simple existence test first; if we fail this, | |
1021 | * there's no point trying anything else. | |
bd71c182 | 1022 | * |
1da177e4 LT |
1023 | * 0x80 is used as a nonsense port to prevent against |
1024 | * false positives due to ISA bus float. The | |
1025 | * assumption is that 0x80 is a non-existent port; | |
1026 | * which should be safe since include/asm/io.h also | |
1027 | * makes this assumption. | |
1028 | * | |
1029 | * Note: this is safe as long as MCR bit 4 is clear | |
1030 | * and the device is in "PC" mode. | |
1031 | */ | |
1032 | scratch = serial_inp(up, UART_IER); | |
1033 | serial_outp(up, UART_IER, 0); | |
1034 | #ifdef __i386__ | |
1035 | outb(0xff, 0x080); | |
1036 | #endif | |
48212008 TH |
1037 | /* |
1038 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL | |
1039 | * 16C754B) allow only to modify them if an EFR bit is set. | |
1040 | */ | |
1041 | scratch2 = serial_inp(up, UART_IER) & 0x0f; | |
1da177e4 LT |
1042 | serial_outp(up, UART_IER, 0x0F); |
1043 | #ifdef __i386__ | |
1044 | outb(0, 0x080); | |
1045 | #endif | |
48212008 | 1046 | scratch3 = serial_inp(up, UART_IER) & 0x0f; |
1da177e4 LT |
1047 | serial_outp(up, UART_IER, scratch); |
1048 | if (scratch2 != 0 || scratch3 != 0x0F) { | |
1049 | /* | |
1050 | * We failed; there's nothing here | |
1051 | */ | |
1052 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", | |
1053 | scratch2, scratch3); | |
1054 | goto out; | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | save_mcr = serial_in(up, UART_MCR); | |
1059 | save_lcr = serial_in(up, UART_LCR); | |
1060 | ||
bd71c182 | 1061 | /* |
1da177e4 LT |
1062 | * Check to see if a UART is really there. Certain broken |
1063 | * internal modems based on the Rockwell chipset fail this | |
1064 | * test, because they apparently don't implement the loopback | |
1065 | * test mode. So this test is skipped on the COM 1 through | |
1066 | * COM 4 ports. This *should* be safe, since no board | |
1067 | * manufacturer would be stupid enough to design a board | |
1068 | * that conflicts with COM 1-4 --- we hope! | |
1069 | */ | |
1070 | if (!(up->port.flags & UPF_SKIP_TEST)) { | |
1071 | serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); | |
1072 | status1 = serial_inp(up, UART_MSR) & 0xF0; | |
1073 | serial_outp(up, UART_MCR, save_mcr); | |
1074 | if (status1 != 0x90) { | |
1075 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", | |
1076 | status1); | |
1077 | goto out; | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | /* | |
1082 | * We're pretty sure there's a port here. Lets find out what | |
1083 | * type of port it is. The IIR top two bits allows us to find | |
6f0d618f | 1084 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1da177e4 LT |
1085 | * determines what we test for next. |
1086 | * | |
1087 | * We also initialise the EFR (if any) to zero for later. The | |
1088 | * EFR occupies the same register location as the FCR and IIR. | |
1089 | */ | |
1090 | serial_outp(up, UART_LCR, 0xBF); | |
1091 | serial_outp(up, UART_EFR, 0); | |
1092 | serial_outp(up, UART_LCR, 0); | |
1093 | ||
1094 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1095 | scratch = serial_in(up, UART_IIR) >> 6; | |
1096 | ||
1097 | DEBUG_AUTOCONF("iir=%d ", scratch); | |
1098 | ||
1099 | switch (scratch) { | |
1100 | case 0: | |
1101 | autoconfig_8250(up); | |
1102 | break; | |
1103 | case 1: | |
1104 | up->port.type = PORT_UNKNOWN; | |
1105 | break; | |
1106 | case 2: | |
1107 | up->port.type = PORT_16550; | |
1108 | break; | |
1109 | case 3: | |
1110 | autoconfig_16550a(up); | |
1111 | break; | |
1112 | } | |
1113 | ||
1114 | #ifdef CONFIG_SERIAL_8250_RSA | |
1115 | /* | |
1116 | * Only probe for RSA ports if we got the region. | |
1117 | */ | |
1118 | if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) { | |
1119 | int i; | |
1120 | ||
1121 | for (i = 0 ; i < probe_rsa_count; ++i) { | |
1122 | if (probe_rsa[i] == up->port.iobase && | |
1123 | __enable_rsa(up)) { | |
1124 | up->port.type = PORT_RSA; | |
1125 | break; | |
1126 | } | |
1127 | } | |
1128 | } | |
1129 | #endif | |
21c614a7 PA |
1130 | |
1131 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |
1132 | /* if access method is AU, it is a 16550 with a quirk */ | |
1133 | if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU) | |
1134 | up->bugs |= UART_BUG_NOMSR; | |
1135 | #endif | |
1136 | ||
1da177e4 LT |
1137 | serial_outp(up, UART_LCR, save_lcr); |
1138 | ||
1139 | if (up->capabilities != uart_config[up->port.type].flags) { | |
1140 | printk(KERN_WARNING | |
1141 | "ttyS%d: detected caps %08x should be %08x\n", | |
8440838b DM |
1142 | serial_index(&up->port), up->capabilities, |
1143 | uart_config[up->port.type].flags); | |
1da177e4 LT |
1144 | } |
1145 | ||
1146 | up->port.fifosize = uart_config[up->port.type].fifo_size; | |
1147 | up->capabilities = uart_config[up->port.type].flags; | |
1148 | up->tx_loadsz = uart_config[up->port.type].tx_loadsz; | |
1149 | ||
1150 | if (up->port.type == PORT_UNKNOWN) | |
1151 | goto out; | |
1152 | ||
1153 | /* | |
1154 | * Reset the UART. | |
1155 | */ | |
1156 | #ifdef CONFIG_SERIAL_8250_RSA | |
1157 | if (up->port.type == PORT_RSA) | |
1158 | serial_outp(up, UART_RSA_FRR, 0); | |
1159 | #endif | |
1160 | serial_outp(up, UART_MCR, save_mcr); | |
1161 | serial8250_clear_fifos(up); | |
40b36daa | 1162 | serial_in(up, UART_RX); |
5c8c755c LB |
1163 | if (up->capabilities & UART_CAP_UUE) |
1164 | serial_outp(up, UART_IER, UART_IER_UUE); | |
1165 | else | |
1166 | serial_outp(up, UART_IER, 0); | |
1da177e4 | 1167 | |
bd71c182 | 1168 | out: |
1da177e4 | 1169 | spin_unlock_irqrestore(&up->port.lock, flags); |
1da177e4 LT |
1170 | DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name); |
1171 | } | |
1172 | ||
1173 | static void autoconfig_irq(struct uart_8250_port *up) | |
1174 | { | |
1175 | unsigned char save_mcr, save_ier; | |
1176 | unsigned char save_ICP = 0; | |
1177 | unsigned int ICP = 0; | |
1178 | unsigned long irqs; | |
1179 | int irq; | |
1180 | ||
1181 | if (up->port.flags & UPF_FOURPORT) { | |
1182 | ICP = (up->port.iobase & 0xfe0) | 0x1f; | |
1183 | save_ICP = inb_p(ICP); | |
1184 | outb_p(0x80, ICP); | |
1185 | (void) inb_p(ICP); | |
1186 | } | |
1187 | ||
1188 | /* forget possible initially masked and pending IRQ */ | |
1189 | probe_irq_off(probe_irq_on()); | |
1190 | save_mcr = serial_inp(up, UART_MCR); | |
1191 | save_ier = serial_inp(up, UART_IER); | |
1192 | serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); | |
bd71c182 | 1193 | |
1da177e4 LT |
1194 | irqs = probe_irq_on(); |
1195 | serial_outp(up, UART_MCR, 0); | |
6f803cd0 AC |
1196 | udelay(10); |
1197 | if (up->port.flags & UPF_FOURPORT) { | |
1da177e4 LT |
1198 | serial_outp(up, UART_MCR, |
1199 | UART_MCR_DTR | UART_MCR_RTS); | |
1200 | } else { | |
1201 | serial_outp(up, UART_MCR, | |
1202 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); | |
1203 | } | |
1204 | serial_outp(up, UART_IER, 0x0f); /* enable all intrs */ | |
1205 | (void)serial_inp(up, UART_LSR); | |
1206 | (void)serial_inp(up, UART_RX); | |
1207 | (void)serial_inp(up, UART_IIR); | |
1208 | (void)serial_inp(up, UART_MSR); | |
1209 | serial_outp(up, UART_TX, 0xFF); | |
6f803cd0 | 1210 | udelay(20); |
1da177e4 LT |
1211 | irq = probe_irq_off(irqs); |
1212 | ||
1213 | serial_outp(up, UART_MCR, save_mcr); | |
1214 | serial_outp(up, UART_IER, save_ier); | |
1215 | ||
1216 | if (up->port.flags & UPF_FOURPORT) | |
1217 | outb_p(save_ICP, ICP); | |
1218 | ||
1219 | up->port.irq = (irq > 0) ? irq : 0; | |
1220 | } | |
1221 | ||
e763b90c RK |
1222 | static inline void __stop_tx(struct uart_8250_port *p) |
1223 | { | |
1224 | if (p->ier & UART_IER_THRI) { | |
1225 | p->ier &= ~UART_IER_THRI; | |
1226 | serial_out(p, UART_IER, p->ier); | |
1227 | } | |
1228 | } | |
1229 | ||
b129a8cc | 1230 | static void serial8250_stop_tx(struct uart_port *port) |
1da177e4 LT |
1231 | { |
1232 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1233 | ||
e763b90c | 1234 | __stop_tx(up); |
1da177e4 LT |
1235 | |
1236 | /* | |
e763b90c | 1237 | * We really want to stop the transmitter from sending. |
1da177e4 | 1238 | */ |
e763b90c | 1239 | if (up->port.type == PORT_16C950) { |
1da177e4 LT |
1240 | up->acr |= UART_ACR_TXDIS; |
1241 | serial_icr_write(up, UART_ACR, up->acr); | |
1242 | } | |
1243 | } | |
1244 | ||
55d3b282 RK |
1245 | static void transmit_chars(struct uart_8250_port *up); |
1246 | ||
b129a8cc | 1247 | static void serial8250_start_tx(struct uart_port *port) |
1da177e4 LT |
1248 | { |
1249 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1250 | ||
1251 | if (!(up->ier & UART_IER_THRI)) { | |
1252 | up->ier |= UART_IER_THRI; | |
1253 | serial_out(up, UART_IER, up->ier); | |
55d3b282 | 1254 | |
67f7654e | 1255 | if (up->bugs & UART_BUG_TXEN) { |
55d3b282 RK |
1256 | unsigned char lsr, iir; |
1257 | lsr = serial_in(up, UART_LSR); | |
ad4c2aa6 | 1258 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
bd71c182 TK |
1259 | iir = serial_in(up, UART_IIR) & 0x0f; |
1260 | if ((up->port.type == PORT_RM9000) ? | |
1261 | (lsr & UART_LSR_THRE && | |
1262 | (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) : | |
1263 | (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)) | |
55d3b282 RK |
1264 | transmit_chars(up); |
1265 | } | |
1da177e4 | 1266 | } |
e763b90c | 1267 | |
1da177e4 | 1268 | /* |
e763b90c | 1269 | * Re-enable the transmitter if we disabled it. |
1da177e4 | 1270 | */ |
e763b90c | 1271 | if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1da177e4 LT |
1272 | up->acr &= ~UART_ACR_TXDIS; |
1273 | serial_icr_write(up, UART_ACR, up->acr); | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | static void serial8250_stop_rx(struct uart_port *port) | |
1278 | { | |
1279 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1280 | ||
1281 | up->ier &= ~UART_IER_RLSI; | |
1282 | up->port.read_status_mask &= ~UART_LSR_DR; | |
1283 | serial_out(up, UART_IER, up->ier); | |
1284 | } | |
1285 | ||
1286 | static void serial8250_enable_ms(struct uart_port *port) | |
1287 | { | |
1288 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1289 | ||
21c614a7 PA |
1290 | /* no MSR capabilities */ |
1291 | if (up->bugs & UART_BUG_NOMSR) | |
1292 | return; | |
1293 | ||
1da177e4 LT |
1294 | up->ier |= UART_IER_MSI; |
1295 | serial_out(up, UART_IER, up->ier); | |
1296 | } | |
1297 | ||
ea8874dc | 1298 | static void |
cc79aa9d | 1299 | receive_chars(struct uart_8250_port *up, unsigned int *status) |
1da177e4 | 1300 | { |
df4f4dd4 | 1301 | struct tty_struct *tty = up->port.info->port.tty; |
1da177e4 LT |
1302 | unsigned char ch, lsr = *status; |
1303 | int max_count = 256; | |
1304 | char flag; | |
1305 | ||
1306 | do { | |
7500b1f6 AR |
1307 | if (likely(lsr & UART_LSR_DR)) |
1308 | ch = serial_inp(up, UART_RX); | |
1309 | else | |
1310 | /* | |
1311 | * Intel 82571 has a Serial Over Lan device that will | |
1312 | * set UART_LSR_BI without setting UART_LSR_DR when | |
1313 | * it receives a break. To avoid reading from the | |
1314 | * receive buffer without UART_LSR_DR bit set, we | |
1315 | * just force the read character to be 0 | |
1316 | */ | |
1317 | ch = 0; | |
1318 | ||
1da177e4 LT |
1319 | flag = TTY_NORMAL; |
1320 | up->port.icount.rx++; | |
1321 | ||
ad4c2aa6 CM |
1322 | lsr |= up->lsr_saved_flags; |
1323 | up->lsr_saved_flags = 0; | |
1da177e4 | 1324 | |
ad4c2aa6 | 1325 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { |
1da177e4 LT |
1326 | /* |
1327 | * For statistics only | |
1328 | */ | |
1329 | if (lsr & UART_LSR_BI) { | |
1330 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
1331 | up->port.icount.brk++; | |
1332 | /* | |
1333 | * We do the SysRQ and SAK checking | |
1334 | * here because otherwise the break | |
1335 | * may get masked by ignore_status_mask | |
1336 | * or read_status_mask. | |
1337 | */ | |
1338 | if (uart_handle_break(&up->port)) | |
1339 | goto ignore_char; | |
1340 | } else if (lsr & UART_LSR_PE) | |
1341 | up->port.icount.parity++; | |
1342 | else if (lsr & UART_LSR_FE) | |
1343 | up->port.icount.frame++; | |
1344 | if (lsr & UART_LSR_OE) | |
1345 | up->port.icount.overrun++; | |
1346 | ||
1347 | /* | |
23907eb8 | 1348 | * Mask off conditions which should be ignored. |
1da177e4 LT |
1349 | */ |
1350 | lsr &= up->port.read_status_mask; | |
1351 | ||
1352 | if (lsr & UART_LSR_BI) { | |
1353 | DEBUG_INTR("handling break...."); | |
1354 | flag = TTY_BREAK; | |
1355 | } else if (lsr & UART_LSR_PE) | |
1356 | flag = TTY_PARITY; | |
1357 | else if (lsr & UART_LSR_FE) | |
1358 | flag = TTY_FRAME; | |
1359 | } | |
7d12e780 | 1360 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 1361 | goto ignore_char; |
05ab3014 RK |
1362 | |
1363 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
1364 | ||
6f803cd0 | 1365 | ignore_char: |
1da177e4 | 1366 | lsr = serial_inp(up, UART_LSR); |
7500b1f6 | 1367 | } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); |
1da177e4 LT |
1368 | spin_unlock(&up->port.lock); |
1369 | tty_flip_buffer_push(tty); | |
1370 | spin_lock(&up->port.lock); | |
1371 | *status = lsr; | |
1372 | } | |
1373 | ||
ea8874dc | 1374 | static void transmit_chars(struct uart_8250_port *up) |
1da177e4 LT |
1375 | { |
1376 | struct circ_buf *xmit = &up->port.info->xmit; | |
1377 | int count; | |
1378 | ||
1379 | if (up->port.x_char) { | |
1380 | serial_outp(up, UART_TX, up->port.x_char); | |
1381 | up->port.icount.tx++; | |
1382 | up->port.x_char = 0; | |
1383 | return; | |
1384 | } | |
b129a8cc RK |
1385 | if (uart_tx_stopped(&up->port)) { |
1386 | serial8250_stop_tx(&up->port); | |
1387 | return; | |
1388 | } | |
1389 | if (uart_circ_empty(xmit)) { | |
e763b90c | 1390 | __stop_tx(up); |
1da177e4 LT |
1391 | return; |
1392 | } | |
1393 | ||
1394 | count = up->tx_loadsz; | |
1395 | do { | |
1396 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
1397 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1398 | up->port.icount.tx++; | |
1399 | if (uart_circ_empty(xmit)) | |
1400 | break; | |
1401 | } while (--count > 0); | |
1402 | ||
1403 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1404 | uart_write_wakeup(&up->port); | |
1405 | ||
1406 | DEBUG_INTR("THRE..."); | |
1407 | ||
1408 | if (uart_circ_empty(xmit)) | |
e763b90c | 1409 | __stop_tx(up); |
1da177e4 LT |
1410 | } |
1411 | ||
2af7cd68 | 1412 | static unsigned int check_modem_status(struct uart_8250_port *up) |
1da177e4 | 1413 | { |
2af7cd68 RK |
1414 | unsigned int status = serial_in(up, UART_MSR); |
1415 | ||
ad4c2aa6 CM |
1416 | status |= up->msr_saved_flags; |
1417 | up->msr_saved_flags = 0; | |
fdc30b3d TI |
1418 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && |
1419 | up->port.info != NULL) { | |
2af7cd68 RK |
1420 | if (status & UART_MSR_TERI) |
1421 | up->port.icount.rng++; | |
1422 | if (status & UART_MSR_DDSR) | |
1423 | up->port.icount.dsr++; | |
1424 | if (status & UART_MSR_DDCD) | |
1425 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
1426 | if (status & UART_MSR_DCTS) | |
1427 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
1428 | ||
1429 | wake_up_interruptible(&up->port.info->delta_msr_wait); | |
1430 | } | |
1da177e4 | 1431 | |
2af7cd68 | 1432 | return status; |
1da177e4 LT |
1433 | } |
1434 | ||
1435 | /* | |
1436 | * This handles the interrupt from one port. | |
1437 | */ | |
b5d674ab | 1438 | static void serial8250_handle_port(struct uart_8250_port *up) |
1da177e4 | 1439 | { |
45e24601 | 1440 | unsigned int status; |
4bf3631c | 1441 | unsigned long flags; |
45e24601 | 1442 | |
4bf3631c | 1443 | spin_lock_irqsave(&up->port.lock, flags); |
45e24601 RK |
1444 | |
1445 | status = serial_inp(up, UART_LSR); | |
1da177e4 LT |
1446 | |
1447 | DEBUG_INTR("status = %x...", status); | |
1448 | ||
7500b1f6 | 1449 | if (status & (UART_LSR_DR | UART_LSR_BI)) |
7d12e780 | 1450 | receive_chars(up, &status); |
1da177e4 LT |
1451 | check_modem_status(up); |
1452 | if (status & UART_LSR_THRE) | |
1453 | transmit_chars(up); | |
45e24601 | 1454 | |
4bf3631c | 1455 | spin_unlock_irqrestore(&up->port.lock, flags); |
1da177e4 LT |
1456 | } |
1457 | ||
1458 | /* | |
1459 | * This is the serial driver's interrupt routine. | |
1460 | * | |
1461 | * Arjan thinks the old way was overly complex, so it got simplified. | |
1462 | * Alan disagrees, saying that need the complexity to handle the weird | |
1463 | * nature of ISA shared interrupts. (This is a special exception.) | |
1464 | * | |
1465 | * In order to handle ISA shared interrupts properly, we need to check | |
1466 | * that all ports have been serviced, and therefore the ISA interrupt | |
1467 | * line has been de-asserted. | |
1468 | * | |
1469 | * This means we need to loop through all ports. checking that they | |
1470 | * don't have an interrupt pending. | |
1471 | */ | |
7d12e780 | 1472 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1473 | { |
1474 | struct irq_info *i = dev_id; | |
1475 | struct list_head *l, *end = NULL; | |
1476 | int pass_counter = 0, handled = 0; | |
1477 | ||
1478 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); | |
1479 | ||
1480 | spin_lock(&i->lock); | |
1481 | ||
1482 | l = i->head; | |
1483 | do { | |
1484 | struct uart_8250_port *up; | |
1485 | unsigned int iir; | |
1486 | ||
1487 | up = list_entry(l, struct uart_8250_port, list); | |
1488 | ||
1489 | iir = serial_in(up, UART_IIR); | |
1490 | if (!(iir & UART_IIR_NO_INT)) { | |
7d12e780 | 1491 | serial8250_handle_port(up); |
1da177e4 LT |
1492 | |
1493 | handled = 1; | |
1494 | ||
beab697a MSJ |
1495 | end = NULL; |
1496 | } else if (up->port.iotype == UPIO_DWAPB && | |
1497 | (iir & UART_IIR_BUSY) == UART_IIR_BUSY) { | |
1498 | /* The DesignWare APB UART has an Busy Detect (0x07) | |
1499 | * interrupt meaning an LCR write attempt occured while the | |
1500 | * UART was busy. The interrupt must be cleared by reading | |
1501 | * the UART status register (USR) and the LCR re-written. */ | |
1502 | unsigned int status; | |
1503 | status = *(volatile u32 *)up->port.private_data; | |
1504 | serial_out(up, UART_LCR, up->lcr); | |
1505 | ||
1506 | handled = 1; | |
1507 | ||
1da177e4 LT |
1508 | end = NULL; |
1509 | } else if (end == NULL) | |
1510 | end = l; | |
1511 | ||
1512 | l = l->next; | |
1513 | ||
1514 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
1515 | /* If we hit this, we're dead. */ | |
1516 | printk(KERN_ERR "serial8250: too much work for " | |
1517 | "irq%d\n", irq); | |
1518 | break; | |
1519 | } | |
1520 | } while (l != end); | |
1521 | ||
1522 | spin_unlock(&i->lock); | |
1523 | ||
1524 | DEBUG_INTR("end.\n"); | |
1525 | ||
1526 | return IRQ_RETVAL(handled); | |
1527 | } | |
1528 | ||
1529 | /* | |
1530 | * To support ISA shared interrupts, we need to have one interrupt | |
1531 | * handler that ensures that the IRQ line has been deasserted | |
1532 | * before returning. Failing to do this will result in the IRQ | |
1533 | * line being stuck active, and, since ISA irqs are edge triggered, | |
1534 | * no more IRQs will be seen. | |
1535 | */ | |
1536 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) | |
1537 | { | |
1538 | spin_lock_irq(&i->lock); | |
1539 | ||
1540 | if (!list_empty(i->head)) { | |
1541 | if (i->head == &up->list) | |
1542 | i->head = i->head->next; | |
1543 | list_del(&up->list); | |
1544 | } else { | |
1545 | BUG_ON(i->head != &up->list); | |
1546 | i->head = NULL; | |
1547 | } | |
1548 | ||
1549 | spin_unlock_irq(&i->lock); | |
1550 | } | |
1551 | ||
1552 | static int serial_link_irq_chain(struct uart_8250_port *up) | |
1553 | { | |
1554 | struct irq_info *i = irq_lists + up->port.irq; | |
40663cc7 | 1555 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; |
1da177e4 LT |
1556 | |
1557 | spin_lock_irq(&i->lock); | |
1558 | ||
1559 | if (i->head) { | |
1560 | list_add(&up->list, i->head); | |
1561 | spin_unlock_irq(&i->lock); | |
1562 | ||
1563 | ret = 0; | |
1564 | } else { | |
1565 | INIT_LIST_HEAD(&up->list); | |
1566 | i->head = &up->list; | |
1567 | spin_unlock_irq(&i->lock); | |
1568 | ||
1569 | ret = request_irq(up->port.irq, serial8250_interrupt, | |
1570 | irq_flags, "serial", i); | |
1571 | if (ret < 0) | |
1572 | serial_do_unlink(i, up); | |
1573 | } | |
1574 | ||
1575 | return ret; | |
1576 | } | |
1577 | ||
1578 | static void serial_unlink_irq_chain(struct uart_8250_port *up) | |
1579 | { | |
1580 | struct irq_info *i = irq_lists + up->port.irq; | |
1581 | ||
1582 | BUG_ON(i->head == NULL); | |
1583 | ||
1584 | if (list_empty(i->head)) | |
1585 | free_irq(up->port.irq, i); | |
1586 | ||
1587 | serial_do_unlink(i, up); | |
1588 | } | |
1589 | ||
40b36daa AW |
1590 | /* Base timer interval for polling */ |
1591 | static inline int poll_timeout(int timeout) | |
1592 | { | |
1593 | return timeout > 6 ? (timeout / 2 - 2) : 1; | |
1594 | } | |
1595 | ||
1da177e4 LT |
1596 | /* |
1597 | * This function is used to handle ports that do not have an | |
1598 | * interrupt. This doesn't work very well for 16450's, but gives | |
1599 | * barely passable results for a 16550A. (Although at the expense | |
1600 | * of much CPU overhead). | |
1601 | */ | |
1602 | static void serial8250_timeout(unsigned long data) | |
1603 | { | |
1604 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
1da177e4 LT |
1605 | unsigned int iir; |
1606 | ||
1607 | iir = serial_in(up, UART_IIR); | |
45e24601 | 1608 | if (!(iir & UART_IIR_NO_INT)) |
7d12e780 | 1609 | serial8250_handle_port(up); |
40b36daa AW |
1610 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
1611 | } | |
1612 | ||
1613 | static void serial8250_backup_timeout(unsigned long data) | |
1614 | { | |
1615 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
ad4c2aa6 CM |
1616 | unsigned int iir, ier = 0, lsr; |
1617 | unsigned long flags; | |
40b36daa AW |
1618 | |
1619 | /* | |
1620 | * Must disable interrupts or else we risk racing with the interrupt | |
1621 | * based handler. | |
1622 | */ | |
1623 | if (is_real_interrupt(up->port.irq)) { | |
1624 | ier = serial_in(up, UART_IER); | |
1625 | serial_out(up, UART_IER, 0); | |
1626 | } | |
1da177e4 | 1627 | |
40b36daa AW |
1628 | iir = serial_in(up, UART_IIR); |
1629 | ||
1630 | /* | |
1631 | * This should be a safe test for anyone who doesn't trust the | |
1632 | * IIR bits on their UART, but it's specifically designed for | |
1633 | * the "Diva" UART used on the management processor on many HP | |
1634 | * ia64 and parisc boxes. | |
1635 | */ | |
ad4c2aa6 CM |
1636 | spin_lock_irqsave(&up->port.lock, flags); |
1637 | lsr = serial_in(up, UART_LSR); | |
1638 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
1639 | spin_unlock_irqrestore(&up->port.lock, flags); | |
40b36daa AW |
1640 | if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && |
1641 | (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) && | |
ad4c2aa6 | 1642 | (lsr & UART_LSR_THRE)) { |
40b36daa AW |
1643 | iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); |
1644 | iir |= UART_IIR_THRI; | |
1645 | } | |
1646 | ||
1647 | if (!(iir & UART_IIR_NO_INT)) | |
1648 | serial8250_handle_port(up); | |
1649 | ||
1650 | if (is_real_interrupt(up->port.irq)) | |
1651 | serial_out(up, UART_IER, ier); | |
1652 | ||
1653 | /* Standard timer interval plus 0.2s to keep the port running */ | |
6f803cd0 AC |
1654 | mod_timer(&up->timer, |
1655 | jiffies + poll_timeout(up->port.timeout) + HZ / 5); | |
1da177e4 LT |
1656 | } |
1657 | ||
1658 | static unsigned int serial8250_tx_empty(struct uart_port *port) | |
1659 | { | |
1660 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1661 | unsigned long flags; | |
ad4c2aa6 | 1662 | unsigned int lsr; |
1da177e4 LT |
1663 | |
1664 | spin_lock_irqsave(&up->port.lock, flags); | |
ad4c2aa6 CM |
1665 | lsr = serial_in(up, UART_LSR); |
1666 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
1da177e4 LT |
1667 | spin_unlock_irqrestore(&up->port.lock, flags); |
1668 | ||
ad4c2aa6 | 1669 | return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0; |
1da177e4 LT |
1670 | } |
1671 | ||
1672 | static unsigned int serial8250_get_mctrl(struct uart_port *port) | |
1673 | { | |
1674 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2af7cd68 | 1675 | unsigned int status; |
1da177e4 LT |
1676 | unsigned int ret; |
1677 | ||
2af7cd68 | 1678 | status = check_modem_status(up); |
1da177e4 LT |
1679 | |
1680 | ret = 0; | |
1681 | if (status & UART_MSR_DCD) | |
1682 | ret |= TIOCM_CAR; | |
1683 | if (status & UART_MSR_RI) | |
1684 | ret |= TIOCM_RNG; | |
1685 | if (status & UART_MSR_DSR) | |
1686 | ret |= TIOCM_DSR; | |
1687 | if (status & UART_MSR_CTS) | |
1688 | ret |= TIOCM_CTS; | |
1689 | return ret; | |
1690 | } | |
1691 | ||
1692 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1693 | { | |
1694 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1695 | unsigned char mcr = 0; | |
1696 | ||
1697 | if (mctrl & TIOCM_RTS) | |
1698 | mcr |= UART_MCR_RTS; | |
1699 | if (mctrl & TIOCM_DTR) | |
1700 | mcr |= UART_MCR_DTR; | |
1701 | if (mctrl & TIOCM_OUT1) | |
1702 | mcr |= UART_MCR_OUT1; | |
1703 | if (mctrl & TIOCM_OUT2) | |
1704 | mcr |= UART_MCR_OUT2; | |
1705 | if (mctrl & TIOCM_LOOP) | |
1706 | mcr |= UART_MCR_LOOP; | |
1707 | ||
1708 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; | |
1709 | ||
1710 | serial_out(up, UART_MCR, mcr); | |
1711 | } | |
1712 | ||
1713 | static void serial8250_break_ctl(struct uart_port *port, int break_state) | |
1714 | { | |
1715 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1716 | unsigned long flags; | |
1717 | ||
1718 | spin_lock_irqsave(&up->port.lock, flags); | |
1719 | if (break_state == -1) | |
1720 | up->lcr |= UART_LCR_SBC; | |
1721 | else | |
1722 | up->lcr &= ~UART_LCR_SBC; | |
1723 | serial_out(up, UART_LCR, up->lcr); | |
1724 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1725 | } | |
1726 | ||
40b36daa AW |
1727 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
1728 | ||
1729 | /* | |
1730 | * Wait for transmitter & holding register to empty | |
1731 | */ | |
b5d674ab | 1732 | static void wait_for_xmitr(struct uart_8250_port *up, int bits) |
40b36daa AW |
1733 | { |
1734 | unsigned int status, tmout = 10000; | |
1735 | ||
1736 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1737 | do { | |
1738 | status = serial_in(up, UART_LSR); | |
1739 | ||
ad4c2aa6 | 1740 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; |
40b36daa AW |
1741 | |
1742 | if (--tmout == 0) | |
1743 | break; | |
1744 | udelay(1); | |
1745 | } while ((status & bits) != bits); | |
1746 | ||
1747 | /* Wait up to 1s for flow control if necessary */ | |
1748 | if (up->port.flags & UPF_CONS_FLOW) { | |
ad4c2aa6 CM |
1749 | unsigned int tmout; |
1750 | for (tmout = 1000000; tmout; tmout--) { | |
1751 | unsigned int msr = serial_in(up, UART_MSR); | |
1752 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1753 | if (msr & UART_MSR_CTS) | |
1754 | break; | |
40b36daa AW |
1755 | udelay(1); |
1756 | touch_nmi_watchdog(); | |
1757 | } | |
1758 | } | |
1759 | } | |
1760 | ||
f2d937f3 JW |
1761 | #ifdef CONFIG_CONSOLE_POLL |
1762 | /* | |
1763 | * Console polling routines for writing and reading from the uart while | |
1764 | * in an interrupt or debug context. | |
1765 | */ | |
1766 | ||
1767 | static int serial8250_get_poll_char(struct uart_port *port) | |
1768 | { | |
1769 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1770 | unsigned char lsr = serial_inp(up, UART_LSR); | |
1771 | ||
1772 | while (!(lsr & UART_LSR_DR)) | |
1773 | lsr = serial_inp(up, UART_LSR); | |
1774 | ||
1775 | return serial_inp(up, UART_RX); | |
1776 | } | |
1777 | ||
1778 | ||
1779 | static void serial8250_put_poll_char(struct uart_port *port, | |
1780 | unsigned char c) | |
1781 | { | |
1782 | unsigned int ier; | |
1783 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1784 | ||
1785 | /* | |
1786 | * First save the IER then disable the interrupts | |
1787 | */ | |
1788 | ier = serial_in(up, UART_IER); | |
1789 | if (up->capabilities & UART_CAP_UUE) | |
1790 | serial_out(up, UART_IER, UART_IER_UUE); | |
1791 | else | |
1792 | serial_out(up, UART_IER, 0); | |
1793 | ||
1794 | wait_for_xmitr(up, BOTH_EMPTY); | |
1795 | /* | |
1796 | * Send the character out. | |
1797 | * If a LF, also do CR... | |
1798 | */ | |
1799 | serial_out(up, UART_TX, c); | |
1800 | if (c == 10) { | |
1801 | wait_for_xmitr(up, BOTH_EMPTY); | |
1802 | serial_out(up, UART_TX, 13); | |
1803 | } | |
1804 | ||
1805 | /* | |
1806 | * Finally, wait for transmitter to become empty | |
1807 | * and restore the IER | |
1808 | */ | |
1809 | wait_for_xmitr(up, BOTH_EMPTY); | |
1810 | serial_out(up, UART_IER, ier); | |
1811 | } | |
1812 | ||
1813 | #endif /* CONFIG_CONSOLE_POLL */ | |
1814 | ||
1da177e4 LT |
1815 | static int serial8250_startup(struct uart_port *port) |
1816 | { | |
1817 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1818 | unsigned long flags; | |
55d3b282 | 1819 | unsigned char lsr, iir; |
1da177e4 LT |
1820 | int retval; |
1821 | ||
1822 | up->capabilities = uart_config[up->port.type].flags; | |
1823 | up->mcr = 0; | |
1824 | ||
1825 | if (up->port.type == PORT_16C950) { | |
1826 | /* Wake up and initialize UART */ | |
1827 | up->acr = 0; | |
1828 | serial_outp(up, UART_LCR, 0xBF); | |
1829 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
1830 | serial_outp(up, UART_IER, 0); | |
1831 | serial_outp(up, UART_LCR, 0); | |
1832 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ | |
1833 | serial_outp(up, UART_LCR, 0xBF); | |
1834 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
1835 | serial_outp(up, UART_LCR, 0); | |
1836 | } | |
1837 | ||
1838 | #ifdef CONFIG_SERIAL_8250_RSA | |
1839 | /* | |
1840 | * If this is an RSA port, see if we can kick it up to the | |
1841 | * higher speed clock. | |
1842 | */ | |
1843 | enable_rsa(up); | |
1844 | #endif | |
1845 | ||
1846 | /* | |
1847 | * Clear the FIFO buffers and disable them. | |
7f927fcc | 1848 | * (they will be reenabled in set_termios()) |
1da177e4 LT |
1849 | */ |
1850 | serial8250_clear_fifos(up); | |
1851 | ||
1852 | /* | |
1853 | * Clear the interrupt registers. | |
1854 | */ | |
1855 | (void) serial_inp(up, UART_LSR); | |
1856 | (void) serial_inp(up, UART_RX); | |
1857 | (void) serial_inp(up, UART_IIR); | |
1858 | (void) serial_inp(up, UART_MSR); | |
1859 | ||
1860 | /* | |
1861 | * At this point, there's no way the LSR could still be 0xff; | |
1862 | * if it is, then bail out, because there's likely no UART | |
1863 | * here. | |
1864 | */ | |
1865 | if (!(up->port.flags & UPF_BUGGY_UART) && | |
1866 | (serial_inp(up, UART_LSR) == 0xff)) { | |
8440838b DM |
1867 | printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n", |
1868 | serial_index(&up->port)); | |
1da177e4 LT |
1869 | return -ENODEV; |
1870 | } | |
1871 | ||
1872 | /* | |
1873 | * For a XR16C850, we need to set the trigger levels | |
1874 | */ | |
1875 | if (up->port.type == PORT_16850) { | |
1876 | unsigned char fctr; | |
1877 | ||
1878 | serial_outp(up, UART_LCR, 0xbf); | |
1879 | ||
1880 | fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); | |
1881 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); | |
1882 | serial_outp(up, UART_TRG, UART_TRG_96); | |
1883 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX); | |
1884 | serial_outp(up, UART_TRG, UART_TRG_96); | |
1885 | ||
1886 | serial_outp(up, UART_LCR, 0); | |
1887 | } | |
1888 | ||
40b36daa | 1889 | if (is_real_interrupt(up->port.irq)) { |
01c194d9 | 1890 | unsigned char iir1; |
40b36daa AW |
1891 | /* |
1892 | * Test for UARTs that do not reassert THRE when the | |
1893 | * transmitter is idle and the interrupt has already | |
1894 | * been cleared. Real 16550s should always reassert | |
1895 | * this interrupt whenever the transmitter is idle and | |
1896 | * the interrupt is enabled. Delays are necessary to | |
1897 | * allow register changes to become visible. | |
1898 | */ | |
c389d27b | 1899 | spin_lock_irqsave(&up->port.lock, flags); |
768aec0b AV |
1900 | if (up->port.flags & UPF_SHARE_IRQ) |
1901 | disable_irq_nosync(up->port.irq); | |
40b36daa AW |
1902 | |
1903 | wait_for_xmitr(up, UART_LSR_THRE); | |
1904 | serial_out_sync(up, UART_IER, UART_IER_THRI); | |
1905 | udelay(1); /* allow THRE to set */ | |
01c194d9 | 1906 | iir1 = serial_in(up, UART_IIR); |
40b36daa AW |
1907 | serial_out(up, UART_IER, 0); |
1908 | serial_out_sync(up, UART_IER, UART_IER_THRI); | |
1909 | udelay(1); /* allow a working UART time to re-assert THRE */ | |
1910 | iir = serial_in(up, UART_IIR); | |
1911 | serial_out(up, UART_IER, 0); | |
1912 | ||
768aec0b AV |
1913 | if (up->port.flags & UPF_SHARE_IRQ) |
1914 | enable_irq(up->port.irq); | |
c389d27b | 1915 | spin_unlock_irqrestore(&up->port.lock, flags); |
40b36daa AW |
1916 | |
1917 | /* | |
1918 | * If the interrupt is not reasserted, setup a timer to | |
1919 | * kick the UART on a regular basis. | |
1920 | */ | |
01c194d9 | 1921 | if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) { |
363f66fe | 1922 | up->bugs |= UART_BUG_THRE; |
8440838b DM |
1923 | pr_debug("ttyS%d - using backup timer\n", |
1924 | serial_index(port)); | |
40b36daa AW |
1925 | } |
1926 | } | |
1927 | ||
363f66fe WN |
1928 | /* |
1929 | * The above check will only give an accurate result the first time | |
1930 | * the port is opened so this value needs to be preserved. | |
1931 | */ | |
1932 | if (up->bugs & UART_BUG_THRE) { | |
1933 | up->timer.function = serial8250_backup_timeout; | |
1934 | up->timer.data = (unsigned long)up; | |
1935 | mod_timer(&up->timer, jiffies + | |
1936 | poll_timeout(up->port.timeout) + HZ / 5); | |
1937 | } | |
1938 | ||
1da177e4 LT |
1939 | /* |
1940 | * If the "interrupt" for this port doesn't correspond with any | |
1941 | * hardware interrupt, we use a timer-based system. The original | |
1942 | * driver used to do this with IRQ0. | |
1943 | */ | |
1944 | if (!is_real_interrupt(up->port.irq)) { | |
1da177e4 | 1945 | up->timer.data = (unsigned long)up; |
40b36daa | 1946 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
1da177e4 LT |
1947 | } else { |
1948 | retval = serial_link_irq_chain(up); | |
1949 | if (retval) | |
1950 | return retval; | |
1951 | } | |
1952 | ||
1953 | /* | |
1954 | * Now, initialize the UART | |
1955 | */ | |
1956 | serial_outp(up, UART_LCR, UART_LCR_WLEN8); | |
1957 | ||
1958 | spin_lock_irqsave(&up->port.lock, flags); | |
1959 | if (up->port.flags & UPF_FOURPORT) { | |
1960 | if (!is_real_interrupt(up->port.irq)) | |
1961 | up->port.mctrl |= TIOCM_OUT1; | |
1962 | } else | |
1963 | /* | |
1964 | * Most PC uarts need OUT2 raised to enable interrupts. | |
1965 | */ | |
1966 | if (is_real_interrupt(up->port.irq)) | |
1967 | up->port.mctrl |= TIOCM_OUT2; | |
1968 | ||
1969 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
55d3b282 RK |
1970 | |
1971 | /* | |
1972 | * Do a quick test to see if we receive an | |
1973 | * interrupt when we enable the TX irq. | |
1974 | */ | |
1975 | serial_outp(up, UART_IER, UART_IER_THRI); | |
1976 | lsr = serial_in(up, UART_LSR); | |
1977 | iir = serial_in(up, UART_IIR); | |
1978 | serial_outp(up, UART_IER, 0); | |
1979 | ||
1980 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { | |
67f7654e RK |
1981 | if (!(up->bugs & UART_BUG_TXEN)) { |
1982 | up->bugs |= UART_BUG_TXEN; | |
55d3b282 | 1983 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
8440838b | 1984 | serial_index(port)); |
55d3b282 RK |
1985 | } |
1986 | } else { | |
67f7654e | 1987 | up->bugs &= ~UART_BUG_TXEN; |
55d3b282 RK |
1988 | } |
1989 | ||
1da177e4 LT |
1990 | spin_unlock_irqrestore(&up->port.lock, flags); |
1991 | ||
ad4c2aa6 CM |
1992 | /* |
1993 | * Clear the interrupt registers again for luck, and clear the | |
1994 | * saved flags to avoid getting false values from polling | |
1995 | * routines or the previous session. | |
1996 | */ | |
1997 | serial_inp(up, UART_LSR); | |
1998 | serial_inp(up, UART_RX); | |
1999 | serial_inp(up, UART_IIR); | |
2000 | serial_inp(up, UART_MSR); | |
2001 | up->lsr_saved_flags = 0; | |
2002 | up->msr_saved_flags = 0; | |
2003 | ||
1da177e4 LT |
2004 | /* |
2005 | * Finally, enable interrupts. Note: Modem status interrupts | |
2006 | * are set via set_termios(), which will be occurring imminently | |
2007 | * anyway, so we don't enable them here. | |
2008 | */ | |
2009 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
2010 | serial_outp(up, UART_IER, up->ier); | |
2011 | ||
2012 | if (up->port.flags & UPF_FOURPORT) { | |
2013 | unsigned int icp; | |
2014 | /* | |
2015 | * Enable interrupts on the AST Fourport board | |
2016 | */ | |
2017 | icp = (up->port.iobase & 0xfe0) | 0x01f; | |
2018 | outb_p(0x80, icp); | |
2019 | (void) inb_p(icp); | |
2020 | } | |
2021 | ||
1da177e4 LT |
2022 | return 0; |
2023 | } | |
2024 | ||
2025 | static void serial8250_shutdown(struct uart_port *port) | |
2026 | { | |
2027 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2028 | unsigned long flags; | |
2029 | ||
2030 | /* | |
2031 | * Disable interrupts from this port | |
2032 | */ | |
2033 | up->ier = 0; | |
2034 | serial_outp(up, UART_IER, 0); | |
2035 | ||
2036 | spin_lock_irqsave(&up->port.lock, flags); | |
2037 | if (up->port.flags & UPF_FOURPORT) { | |
2038 | /* reset interrupts on the AST Fourport board */ | |
2039 | inb((up->port.iobase & 0xfe0) | 0x1f); | |
2040 | up->port.mctrl |= TIOCM_OUT1; | |
2041 | } else | |
2042 | up->port.mctrl &= ~TIOCM_OUT2; | |
2043 | ||
2044 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
2045 | spin_unlock_irqrestore(&up->port.lock, flags); | |
2046 | ||
2047 | /* | |
2048 | * Disable break condition and FIFOs | |
2049 | */ | |
2050 | serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); | |
2051 | serial8250_clear_fifos(up); | |
2052 | ||
2053 | #ifdef CONFIG_SERIAL_8250_RSA | |
2054 | /* | |
2055 | * Reset the RSA board back to 115kbps compat mode. | |
2056 | */ | |
2057 | disable_rsa(up); | |
2058 | #endif | |
2059 | ||
2060 | /* | |
2061 | * Read data port to reset things, and then unlink from | |
2062 | * the IRQ chain. | |
2063 | */ | |
2064 | (void) serial_in(up, UART_RX); | |
2065 | ||
40b36daa AW |
2066 | del_timer_sync(&up->timer); |
2067 | up->timer.function = serial8250_timeout; | |
2068 | if (is_real_interrupt(up->port.irq)) | |
1da177e4 LT |
2069 | serial_unlink_irq_chain(up); |
2070 | } | |
2071 | ||
2072 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) | |
2073 | { | |
2074 | unsigned int quot; | |
2075 | ||
2076 | /* | |
2077 | * Handle magic divisors for baud rates above baud_base on | |
2078 | * SMSC SuperIO chips. | |
2079 | */ | |
2080 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2081 | baud == (port->uartclk/4)) | |
2082 | quot = 0x8001; | |
2083 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2084 | baud == (port->uartclk/8)) | |
2085 | quot = 0x8002; | |
2086 | else | |
2087 | quot = uart_get_divisor(port, baud); | |
2088 | ||
2089 | return quot; | |
2090 | } | |
2091 | ||
2092 | static void | |
606d099c AC |
2093 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, |
2094 | struct ktermios *old) | |
1da177e4 LT |
2095 | { |
2096 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2097 | unsigned char cval, fcr = 0; | |
2098 | unsigned long flags; | |
2099 | unsigned int baud, quot; | |
2100 | ||
2101 | switch (termios->c_cflag & CSIZE) { | |
2102 | case CS5: | |
0a8b80c5 | 2103 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
2104 | break; |
2105 | case CS6: | |
0a8b80c5 | 2106 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
2107 | break; |
2108 | case CS7: | |
0a8b80c5 | 2109 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
2110 | break; |
2111 | default: | |
2112 | case CS8: | |
0a8b80c5 | 2113 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
2114 | break; |
2115 | } | |
2116 | ||
2117 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 2118 | cval |= UART_LCR_STOP; |
1da177e4 LT |
2119 | if (termios->c_cflag & PARENB) |
2120 | cval |= UART_LCR_PARITY; | |
2121 | if (!(termios->c_cflag & PARODD)) | |
2122 | cval |= UART_LCR_EPAR; | |
2123 | #ifdef CMSPAR | |
2124 | if (termios->c_cflag & CMSPAR) | |
2125 | cval |= UART_LCR_SPAR; | |
2126 | #endif | |
2127 | ||
2128 | /* | |
2129 | * Ask the core to calculate the divisor for us. | |
2130 | */ | |
bd71c182 | 2131 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); |
1da177e4 LT |
2132 | quot = serial8250_get_divisor(port, baud); |
2133 | ||
2134 | /* | |
4ba5e35d | 2135 | * Oxford Semi 952 rev B workaround |
1da177e4 | 2136 | */ |
4ba5e35d | 2137 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
3e8d4e20 | 2138 | quot++; |
1da177e4 LT |
2139 | |
2140 | if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) { | |
2141 | if (baud < 2400) | |
2142 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; | |
2143 | else | |
2144 | fcr = uart_config[up->port.type].fcr; | |
2145 | } | |
2146 | ||
2147 | /* | |
2148 | * MCR-based auto flow control. When AFE is enabled, RTS will be | |
2149 | * deasserted when the receive FIFO contains more characters than | |
2150 | * the trigger, or the MCR RTS bit is cleared. In the case where | |
2151 | * the remote UART is not using CTS auto flow control, we must | |
2152 | * have sufficient FIFO entries for the latency of the remote | |
2153 | * UART to respond. IOW, at least 32 bytes of FIFO. | |
2154 | */ | |
2155 | if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { | |
2156 | up->mcr &= ~UART_MCR_AFE; | |
2157 | if (termios->c_cflag & CRTSCTS) | |
2158 | up->mcr |= UART_MCR_AFE; | |
2159 | } | |
2160 | ||
2161 | /* | |
2162 | * Ok, we're now changing the port state. Do it with | |
2163 | * interrupts disabled. | |
2164 | */ | |
2165 | spin_lock_irqsave(&up->port.lock, flags); | |
2166 | ||
2167 | /* | |
2168 | * Update the per-port timeout. | |
2169 | */ | |
2170 | uart_update_timeout(port, termios->c_cflag, baud); | |
2171 | ||
2172 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
2173 | if (termios->c_iflag & INPCK) | |
2174 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
2175 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
2176 | up->port.read_status_mask |= UART_LSR_BI; | |
2177 | ||
2178 | /* | |
2179 | * Characteres to ignore | |
2180 | */ | |
2181 | up->port.ignore_status_mask = 0; | |
2182 | if (termios->c_iflag & IGNPAR) | |
2183 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
2184 | if (termios->c_iflag & IGNBRK) { | |
2185 | up->port.ignore_status_mask |= UART_LSR_BI; | |
2186 | /* | |
2187 | * If we're ignoring parity and break indicators, | |
2188 | * ignore overruns too (for real raw support). | |
2189 | */ | |
2190 | if (termios->c_iflag & IGNPAR) | |
2191 | up->port.ignore_status_mask |= UART_LSR_OE; | |
2192 | } | |
2193 | ||
2194 | /* | |
2195 | * ignore all characters if CREAD is not set | |
2196 | */ | |
2197 | if ((termios->c_cflag & CREAD) == 0) | |
2198 | up->port.ignore_status_mask |= UART_LSR_DR; | |
2199 | ||
2200 | /* | |
2201 | * CTS flow control flag and modem status interrupts | |
2202 | */ | |
2203 | up->ier &= ~UART_IER_MSI; | |
21c614a7 PA |
2204 | if (!(up->bugs & UART_BUG_NOMSR) && |
2205 | UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
1da177e4 LT |
2206 | up->ier |= UART_IER_MSI; |
2207 | if (up->capabilities & UART_CAP_UUE) | |
2208 | up->ier |= UART_IER_UUE | UART_IER_RTOIE; | |
2209 | ||
2210 | serial_out(up, UART_IER, up->ier); | |
2211 | ||
2212 | if (up->capabilities & UART_CAP_EFR) { | |
2213 | unsigned char efr = 0; | |
2214 | /* | |
2215 | * TI16C752/Startech hardware flow control. FIXME: | |
2216 | * - TI16C752 requires control thresholds to be set. | |
2217 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. | |
2218 | */ | |
2219 | if (termios->c_cflag & CRTSCTS) | |
2220 | efr |= UART_EFR_CTS; | |
2221 | ||
2222 | serial_outp(up, UART_LCR, 0xBF); | |
2223 | serial_outp(up, UART_EFR, efr); | |
2224 | } | |
2225 | ||
255341c6 JM |
2226 | #ifdef CONFIG_ARCH_OMAP15XX |
2227 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ | |
2228 | if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) { | |
2229 | if (baud == 115200) { | |
2230 | quot = 1; | |
2231 | serial_out(up, UART_OMAP_OSC_12M_SEL, 1); | |
2232 | } else | |
2233 | serial_out(up, UART_OMAP_OSC_12M_SEL, 0); | |
2234 | } | |
2235 | #endif | |
2236 | ||
1da177e4 LT |
2237 | if (up->capabilities & UART_NATSEMI) { |
2238 | /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ | |
2239 | serial_outp(up, UART_LCR, 0xe0); | |
2240 | } else { | |
2241 | serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ | |
2242 | } | |
2243 | ||
b32b19b8 | 2244 | serial_dl_write(up, quot); |
1da177e4 LT |
2245 | |
2246 | /* | |
2247 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR | |
2248 | * is written without DLAB set, this mode will be disabled. | |
2249 | */ | |
2250 | if (up->port.type == PORT_16750) | |
2251 | serial_outp(up, UART_FCR, fcr); | |
2252 | ||
2253 | serial_outp(up, UART_LCR, cval); /* reset DLAB */ | |
2254 | up->lcr = cval; /* Save LCR */ | |
2255 | if (up->port.type != PORT_16750) { | |
2256 | if (fcr & UART_FCR_ENABLE_FIFO) { | |
2257 | /* emulated UARTs (Lucent Venus 167x) need two steps */ | |
2258 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
2259 | } | |
2260 | serial_outp(up, UART_FCR, fcr); /* set fcr */ | |
2261 | } | |
2262 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
2263 | spin_unlock_irqrestore(&up->port.lock, flags); | |
e991a2bd AC |
2264 | /* Don't rewrite B0 */ |
2265 | if (tty_termios_baud_rate(termios)) | |
2266 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1da177e4 LT |
2267 | } |
2268 | ||
2269 | static void | |
2270 | serial8250_pm(struct uart_port *port, unsigned int state, | |
2271 | unsigned int oldstate) | |
2272 | { | |
2273 | struct uart_8250_port *p = (struct uart_8250_port *)port; | |
2274 | ||
2275 | serial8250_set_sleep(p, state != 0); | |
2276 | ||
2277 | if (p->pm) | |
2278 | p->pm(port, state, oldstate); | |
2279 | } | |
2280 | ||
2281 | /* | |
2282 | * Resource handling. | |
2283 | */ | |
2284 | static int serial8250_request_std_resource(struct uart_8250_port *up) | |
2285 | { | |
2286 | unsigned int size = 8 << up->port.regshift; | |
2287 | int ret = 0; | |
2288 | ||
2289 | switch (up->port.iotype) { | |
85835f44 SS |
2290 | case UPIO_AU: |
2291 | size = 0x100000; | |
2292 | /* fall thru */ | |
0b30d668 SS |
2293 | case UPIO_TSI: |
2294 | case UPIO_MEM32: | |
1da177e4 | 2295 | case UPIO_MEM: |
beab697a | 2296 | case UPIO_DWAPB: |
1da177e4 LT |
2297 | if (!up->port.mapbase) |
2298 | break; | |
2299 | ||
2300 | if (!request_mem_region(up->port.mapbase, size, "serial")) { | |
2301 | ret = -EBUSY; | |
2302 | break; | |
2303 | } | |
2304 | ||
2305 | if (up->port.flags & UPF_IOREMAP) { | |
6f441fe9 AC |
2306 | up->port.membase = ioremap_nocache(up->port.mapbase, |
2307 | size); | |
1da177e4 LT |
2308 | if (!up->port.membase) { |
2309 | release_mem_region(up->port.mapbase, size); | |
2310 | ret = -ENOMEM; | |
2311 | } | |
2312 | } | |
2313 | break; | |
2314 | ||
2315 | case UPIO_HUB6: | |
2316 | case UPIO_PORT: | |
2317 | if (!request_region(up->port.iobase, size, "serial")) | |
2318 | ret = -EBUSY; | |
2319 | break; | |
2320 | } | |
2321 | return ret; | |
2322 | } | |
2323 | ||
2324 | static void serial8250_release_std_resource(struct uart_8250_port *up) | |
2325 | { | |
2326 | unsigned int size = 8 << up->port.regshift; | |
2327 | ||
2328 | switch (up->port.iotype) { | |
85835f44 SS |
2329 | case UPIO_AU: |
2330 | size = 0x100000; | |
2331 | /* fall thru */ | |
0b30d668 SS |
2332 | case UPIO_TSI: |
2333 | case UPIO_MEM32: | |
1da177e4 | 2334 | case UPIO_MEM: |
beab697a | 2335 | case UPIO_DWAPB: |
1da177e4 LT |
2336 | if (!up->port.mapbase) |
2337 | break; | |
2338 | ||
2339 | if (up->port.flags & UPF_IOREMAP) { | |
2340 | iounmap(up->port.membase); | |
2341 | up->port.membase = NULL; | |
2342 | } | |
2343 | ||
2344 | release_mem_region(up->port.mapbase, size); | |
2345 | break; | |
2346 | ||
2347 | case UPIO_HUB6: | |
2348 | case UPIO_PORT: | |
2349 | release_region(up->port.iobase, size); | |
2350 | break; | |
2351 | } | |
2352 | } | |
2353 | ||
2354 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) | |
2355 | { | |
2356 | unsigned long start = UART_RSA_BASE << up->port.regshift; | |
2357 | unsigned int size = 8 << up->port.regshift; | |
0b30d668 | 2358 | int ret = -EINVAL; |
1da177e4 LT |
2359 | |
2360 | switch (up->port.iotype) { | |
1da177e4 LT |
2361 | case UPIO_HUB6: |
2362 | case UPIO_PORT: | |
2363 | start += up->port.iobase; | |
0b30d668 SS |
2364 | if (request_region(start, size, "serial-rsa")) |
2365 | ret = 0; | |
2366 | else | |
1da177e4 LT |
2367 | ret = -EBUSY; |
2368 | break; | |
2369 | } | |
2370 | ||
2371 | return ret; | |
2372 | } | |
2373 | ||
2374 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) | |
2375 | { | |
2376 | unsigned long offset = UART_RSA_BASE << up->port.regshift; | |
2377 | unsigned int size = 8 << up->port.regshift; | |
2378 | ||
2379 | switch (up->port.iotype) { | |
1da177e4 LT |
2380 | case UPIO_HUB6: |
2381 | case UPIO_PORT: | |
2382 | release_region(up->port.iobase + offset, size); | |
2383 | break; | |
2384 | } | |
2385 | } | |
2386 | ||
2387 | static void serial8250_release_port(struct uart_port *port) | |
2388 | { | |
2389 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2390 | ||
2391 | serial8250_release_std_resource(up); | |
2392 | if (up->port.type == PORT_RSA) | |
2393 | serial8250_release_rsa_resource(up); | |
2394 | } | |
2395 | ||
2396 | static int serial8250_request_port(struct uart_port *port) | |
2397 | { | |
2398 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2399 | int ret = 0; | |
2400 | ||
2401 | ret = serial8250_request_std_resource(up); | |
2402 | if (ret == 0 && up->port.type == PORT_RSA) { | |
2403 | ret = serial8250_request_rsa_resource(up); | |
2404 | if (ret < 0) | |
2405 | serial8250_release_std_resource(up); | |
2406 | } | |
2407 | ||
2408 | return ret; | |
2409 | } | |
2410 | ||
2411 | static void serial8250_config_port(struct uart_port *port, int flags) | |
2412 | { | |
2413 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2414 | int probeflags = PROBE_ANY; | |
2415 | int ret; | |
2416 | ||
1da177e4 LT |
2417 | /* |
2418 | * Find the region that we can probe for. This in turn | |
2419 | * tells us whether we can probe for the type of port. | |
2420 | */ | |
2421 | ret = serial8250_request_std_resource(up); | |
2422 | if (ret < 0) | |
2423 | return; | |
2424 | ||
2425 | ret = serial8250_request_rsa_resource(up); | |
2426 | if (ret < 0) | |
2427 | probeflags &= ~PROBE_RSA; | |
2428 | ||
2429 | if (flags & UART_CONFIG_TYPE) | |
2430 | autoconfig(up, probeflags); | |
2431 | if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) | |
2432 | autoconfig_irq(up); | |
2433 | ||
2434 | if (up->port.type != PORT_RSA && probeflags & PROBE_RSA) | |
2435 | serial8250_release_rsa_resource(up); | |
2436 | if (up->port.type == PORT_UNKNOWN) | |
2437 | serial8250_release_std_resource(up); | |
2438 | } | |
2439 | ||
2440 | static int | |
2441 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2442 | { | |
2443 | if (ser->irq >= NR_IRQS || ser->irq < 0 || | |
2444 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || | |
2445 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || | |
2446 | ser->type == PORT_STARTECH) | |
2447 | return -EINVAL; | |
2448 | return 0; | |
2449 | } | |
2450 | ||
2451 | static const char * | |
2452 | serial8250_type(struct uart_port *port) | |
2453 | { | |
2454 | int type = port->type; | |
2455 | ||
2456 | if (type >= ARRAY_SIZE(uart_config)) | |
2457 | type = 0; | |
2458 | return uart_config[type].name; | |
2459 | } | |
2460 | ||
2461 | static struct uart_ops serial8250_pops = { | |
2462 | .tx_empty = serial8250_tx_empty, | |
2463 | .set_mctrl = serial8250_set_mctrl, | |
2464 | .get_mctrl = serial8250_get_mctrl, | |
2465 | .stop_tx = serial8250_stop_tx, | |
2466 | .start_tx = serial8250_start_tx, | |
2467 | .stop_rx = serial8250_stop_rx, | |
2468 | .enable_ms = serial8250_enable_ms, | |
2469 | .break_ctl = serial8250_break_ctl, | |
2470 | .startup = serial8250_startup, | |
2471 | .shutdown = serial8250_shutdown, | |
2472 | .set_termios = serial8250_set_termios, | |
2473 | .pm = serial8250_pm, | |
2474 | .type = serial8250_type, | |
2475 | .release_port = serial8250_release_port, | |
2476 | .request_port = serial8250_request_port, | |
2477 | .config_port = serial8250_config_port, | |
2478 | .verify_port = serial8250_verify_port, | |
f2d937f3 JW |
2479 | #ifdef CONFIG_CONSOLE_POLL |
2480 | .poll_get_char = serial8250_get_poll_char, | |
2481 | .poll_put_char = serial8250_put_poll_char, | |
2482 | #endif | |
1da177e4 LT |
2483 | }; |
2484 | ||
2485 | static struct uart_8250_port serial8250_ports[UART_NR]; | |
2486 | ||
2487 | static void __init serial8250_isa_init_ports(void) | |
2488 | { | |
2489 | struct uart_8250_port *up; | |
2490 | static int first = 1; | |
2491 | int i; | |
2492 | ||
2493 | if (!first) | |
2494 | return; | |
2495 | first = 0; | |
2496 | ||
a61c2d78 | 2497 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2498 | struct uart_8250_port *up = &serial8250_ports[i]; |
2499 | ||
2500 | up->port.line = i; | |
2501 | spin_lock_init(&up->port.lock); | |
2502 | ||
2503 | init_timer(&up->timer); | |
2504 | up->timer.function = serial8250_timeout; | |
2505 | ||
2506 | /* | |
2507 | * ALPHA_KLUDGE_MCR needs to be killed. | |
2508 | */ | |
2509 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | |
2510 | up->mcr_force = ALPHA_KLUDGE_MCR; | |
2511 | ||
2512 | up->port.ops = &serial8250_pops; | |
2513 | } | |
2514 | ||
44454bcd | 2515 | for (i = 0, up = serial8250_ports; |
a61c2d78 | 2516 | i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; |
1da177e4 LT |
2517 | i++, up++) { |
2518 | up->port.iobase = old_serial_port[i].port; | |
2519 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); | |
2520 | up->port.uartclk = old_serial_port[i].baud_base * 16; | |
2521 | up->port.flags = old_serial_port[i].flags; | |
2522 | up->port.hub6 = old_serial_port[i].hub6; | |
2523 | up->port.membase = old_serial_port[i].iomem_base; | |
2524 | up->port.iotype = old_serial_port[i].io_type; | |
2525 | up->port.regshift = old_serial_port[i].iomem_reg_shift; | |
2526 | if (share_irqs) | |
2527 | up->port.flags |= UPF_SHARE_IRQ; | |
2528 | } | |
2529 | } | |
2530 | ||
2531 | static void __init | |
2532 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) | |
2533 | { | |
2534 | int i; | |
2535 | ||
2536 | serial8250_isa_init_ports(); | |
2537 | ||
a61c2d78 | 2538 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2539 | struct uart_8250_port *up = &serial8250_ports[i]; |
2540 | ||
2541 | up->port.dev = dev; | |
2542 | uart_add_one_port(drv, &up->port); | |
2543 | } | |
2544 | } | |
2545 | ||
2546 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
2547 | ||
d358788f RK |
2548 | static void serial8250_console_putchar(struct uart_port *port, int ch) |
2549 | { | |
2550 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2551 | ||
2552 | wait_for_xmitr(up, UART_LSR_THRE); | |
2553 | serial_out(up, UART_TX, ch); | |
2554 | } | |
2555 | ||
1da177e4 LT |
2556 | /* |
2557 | * Print a string to the serial port trying not to disturb | |
2558 | * any possible real use of the port... | |
2559 | * | |
2560 | * The console_lock must be held when we get here. | |
2561 | */ | |
2562 | static void | |
2563 | serial8250_console_write(struct console *co, const char *s, unsigned int count) | |
2564 | { | |
2565 | struct uart_8250_port *up = &serial8250_ports[co->index]; | |
d8a5a8d7 | 2566 | unsigned long flags; |
1da177e4 | 2567 | unsigned int ier; |
d8a5a8d7 | 2568 | int locked = 1; |
1da177e4 | 2569 | |
78512ece AM |
2570 | touch_nmi_watchdog(); |
2571 | ||
68aa2c0d AM |
2572 | local_irq_save(flags); |
2573 | if (up->port.sysrq) { | |
2574 | /* serial8250_handle_port() already took the lock */ | |
2575 | locked = 0; | |
2576 | } else if (oops_in_progress) { | |
2577 | locked = spin_trylock(&up->port.lock); | |
d8a5a8d7 | 2578 | } else |
68aa2c0d | 2579 | spin_lock(&up->port.lock); |
d8a5a8d7 | 2580 | |
1da177e4 | 2581 | /* |
dc7bf130 | 2582 | * First save the IER then disable the interrupts |
1da177e4 LT |
2583 | */ |
2584 | ier = serial_in(up, UART_IER); | |
2585 | ||
2586 | if (up->capabilities & UART_CAP_UUE) | |
2587 | serial_out(up, UART_IER, UART_IER_UUE); | |
2588 | else | |
2589 | serial_out(up, UART_IER, 0); | |
2590 | ||
d358788f | 2591 | uart_console_write(&up->port, s, count, serial8250_console_putchar); |
1da177e4 LT |
2592 | |
2593 | /* | |
2594 | * Finally, wait for transmitter to become empty | |
2595 | * and restore the IER | |
2596 | */ | |
f91a3715 | 2597 | wait_for_xmitr(up, BOTH_EMPTY); |
a88d75b2 | 2598 | serial_out(up, UART_IER, ier); |
d8a5a8d7 | 2599 | |
ad4c2aa6 CM |
2600 | /* |
2601 | * The receive handling will happen properly because the | |
2602 | * receive ready bit will still be set; it is not cleared | |
2603 | * on read. However, modem control will not, we must | |
2604 | * call it if we have saved something in the saved flags | |
2605 | * while processing with interrupts off. | |
2606 | */ | |
2607 | if (up->msr_saved_flags) | |
2608 | check_modem_status(up); | |
2609 | ||
d8a5a8d7 | 2610 | if (locked) |
68aa2c0d AM |
2611 | spin_unlock(&up->port.lock); |
2612 | local_irq_restore(flags); | |
1da177e4 LT |
2613 | } |
2614 | ||
118c0ace | 2615 | static int __init serial8250_console_setup(struct console *co, char *options) |
1da177e4 LT |
2616 | { |
2617 | struct uart_port *port; | |
2618 | int baud = 9600; | |
2619 | int bits = 8; | |
2620 | int parity = 'n'; | |
2621 | int flow = 'n'; | |
2622 | ||
2623 | /* | |
2624 | * Check whether an invalid uart number has been specified, and | |
2625 | * if so, search for the first available port that does have | |
2626 | * console support. | |
2627 | */ | |
a61c2d78 | 2628 | if (co->index >= nr_uarts) |
1da177e4 LT |
2629 | co->index = 0; |
2630 | port = &serial8250_ports[co->index].port; | |
2631 | if (!port->iobase && !port->membase) | |
2632 | return -ENODEV; | |
2633 | ||
2634 | if (options) | |
2635 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2636 | ||
2637 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2638 | } | |
2639 | ||
b6b1d877 | 2640 | static int serial8250_console_early_setup(void) |
18a8bd94 YL |
2641 | { |
2642 | return serial8250_find_port_for_earlycon(); | |
2643 | } | |
2644 | ||
1da177e4 LT |
2645 | static struct console serial8250_console = { |
2646 | .name = "ttyS", | |
2647 | .write = serial8250_console_write, | |
2648 | .device = uart_console_device, | |
2649 | .setup = serial8250_console_setup, | |
18a8bd94 | 2650 | .early_setup = serial8250_console_early_setup, |
1da177e4 LT |
2651 | .flags = CON_PRINTBUFFER, |
2652 | .index = -1, | |
2653 | .data = &serial8250_reg, | |
2654 | }; | |
2655 | ||
2656 | static int __init serial8250_console_init(void) | |
2657 | { | |
05d81d22 EB |
2658 | if (nr_uarts > UART_NR) |
2659 | nr_uarts = UART_NR; | |
2660 | ||
1da177e4 LT |
2661 | serial8250_isa_init_ports(); |
2662 | register_console(&serial8250_console); | |
2663 | return 0; | |
2664 | } | |
2665 | console_initcall(serial8250_console_init); | |
2666 | ||
18a8bd94 | 2667 | int serial8250_find_port(struct uart_port *p) |
1da177e4 LT |
2668 | { |
2669 | int line; | |
2670 | struct uart_port *port; | |
2671 | ||
a61c2d78 | 2672 | for (line = 0; line < nr_uarts; line++) { |
1da177e4 | 2673 | port = &serial8250_ports[line].port; |
50aec3b5 | 2674 | if (uart_match_port(p, port)) |
1da177e4 LT |
2675 | return line; |
2676 | } | |
2677 | return -ENODEV; | |
2678 | } | |
2679 | ||
1da177e4 LT |
2680 | #define SERIAL8250_CONSOLE &serial8250_console |
2681 | #else | |
2682 | #define SERIAL8250_CONSOLE NULL | |
2683 | #endif | |
2684 | ||
2685 | static struct uart_driver serial8250_reg = { | |
2686 | .owner = THIS_MODULE, | |
2687 | .driver_name = "serial", | |
1da177e4 LT |
2688 | .dev_name = "ttyS", |
2689 | .major = TTY_MAJOR, | |
2690 | .minor = 64, | |
1da177e4 LT |
2691 | .cons = SERIAL8250_CONSOLE, |
2692 | }; | |
2693 | ||
d856c666 RK |
2694 | /* |
2695 | * early_serial_setup - early registration for 8250 ports | |
2696 | * | |
2697 | * Setup an 8250 port structure prior to console initialisation. Use | |
2698 | * after console initialisation will cause undefined behaviour. | |
2699 | */ | |
1da177e4 LT |
2700 | int __init early_serial_setup(struct uart_port *port) |
2701 | { | |
2702 | if (port->line >= ARRAY_SIZE(serial8250_ports)) | |
2703 | return -ENODEV; | |
2704 | ||
2705 | serial8250_isa_init_ports(); | |
2706 | serial8250_ports[port->line].port = *port; | |
2707 | serial8250_ports[port->line].port.ops = &serial8250_pops; | |
2708 | return 0; | |
2709 | } | |
2710 | ||
2711 | /** | |
2712 | * serial8250_suspend_port - suspend one serial port | |
2713 | * @line: serial line number | |
1da177e4 LT |
2714 | * |
2715 | * Suspend one serial port. | |
2716 | */ | |
2717 | void serial8250_suspend_port(int line) | |
2718 | { | |
2719 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); | |
2720 | } | |
2721 | ||
2722 | /** | |
2723 | * serial8250_resume_port - resume one serial port | |
2724 | * @line: serial line number | |
1da177e4 LT |
2725 | * |
2726 | * Resume one serial port. | |
2727 | */ | |
2728 | void serial8250_resume_port(int line) | |
2729 | { | |
b5b82df6 DW |
2730 | struct uart_8250_port *up = &serial8250_ports[line]; |
2731 | ||
2732 | if (up->capabilities & UART_NATSEMI) { | |
2733 | unsigned char tmp; | |
2734 | ||
2735 | /* Ensure it's still in high speed mode */ | |
2736 | serial_outp(up, UART_LCR, 0xE0); | |
2737 | ||
2738 | tmp = serial_in(up, 0x04); /* EXCR2 */ | |
2739 | tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | |
2740 | tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
2741 | serial_outp(up, 0x04, tmp); | |
2742 | ||
2743 | serial_outp(up, UART_LCR, 0); | |
2744 | } | |
2745 | uart_resume_port(&serial8250_reg, &up->port); | |
1da177e4 LT |
2746 | } |
2747 | ||
2748 | /* | |
2749 | * Register a set of serial devices attached to a platform device. The | |
2750 | * list is terminated with a zero flags entry, which means we expect | |
2751 | * all entries to have at least UPF_BOOT_AUTOCONF set. | |
2752 | */ | |
3ae5eaec | 2753 | static int __devinit serial8250_probe(struct platform_device *dev) |
1da177e4 | 2754 | { |
3ae5eaec | 2755 | struct plat_serial8250_port *p = dev->dev.platform_data; |
1da177e4 | 2756 | struct uart_port port; |
ec9f47cd | 2757 | int ret, i; |
1da177e4 LT |
2758 | |
2759 | memset(&port, 0, sizeof(struct uart_port)); | |
2760 | ||
ec9f47cd | 2761 | for (i = 0; p && p->flags != 0; p++, i++) { |
74a19741 WN |
2762 | port.iobase = p->iobase; |
2763 | port.membase = p->membase; | |
2764 | port.irq = p->irq; | |
2765 | port.uartclk = p->uartclk; | |
2766 | port.regshift = p->regshift; | |
2767 | port.iotype = p->iotype; | |
2768 | port.flags = p->flags; | |
2769 | port.mapbase = p->mapbase; | |
2770 | port.hub6 = p->hub6; | |
2771 | port.private_data = p->private_data; | |
2772 | port.dev = &dev->dev; | |
1da177e4 LT |
2773 | if (share_irqs) |
2774 | port.flags |= UPF_SHARE_IRQ; | |
ec9f47cd RK |
2775 | ret = serial8250_register_port(&port); |
2776 | if (ret < 0) { | |
3ae5eaec | 2777 | dev_err(&dev->dev, "unable to register port at index %d " |
4f640efb JB |
2778 | "(IO%lx MEM%llx IRQ%d): %d\n", i, |
2779 | p->iobase, (unsigned long long)p->mapbase, | |
2780 | p->irq, ret); | |
ec9f47cd | 2781 | } |
1da177e4 LT |
2782 | } |
2783 | return 0; | |
2784 | } | |
2785 | ||
2786 | /* | |
2787 | * Remove serial ports registered against a platform device. | |
2788 | */ | |
3ae5eaec | 2789 | static int __devexit serial8250_remove(struct platform_device *dev) |
1da177e4 LT |
2790 | { |
2791 | int i; | |
2792 | ||
a61c2d78 | 2793 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2794 | struct uart_8250_port *up = &serial8250_ports[i]; |
2795 | ||
3ae5eaec | 2796 | if (up->port.dev == &dev->dev) |
1da177e4 LT |
2797 | serial8250_unregister_port(i); |
2798 | } | |
2799 | return 0; | |
2800 | } | |
2801 | ||
3ae5eaec | 2802 | static int serial8250_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 LT |
2803 | { |
2804 | int i; | |
2805 | ||
1da177e4 LT |
2806 | for (i = 0; i < UART_NR; i++) { |
2807 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2808 | ||
3ae5eaec | 2809 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
1da177e4 LT |
2810 | uart_suspend_port(&serial8250_reg, &up->port); |
2811 | } | |
2812 | ||
2813 | return 0; | |
2814 | } | |
2815 | ||
3ae5eaec | 2816 | static int serial8250_resume(struct platform_device *dev) |
1da177e4 LT |
2817 | { |
2818 | int i; | |
2819 | ||
1da177e4 LT |
2820 | for (i = 0; i < UART_NR; i++) { |
2821 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2822 | ||
3ae5eaec | 2823 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
b5b82df6 | 2824 | serial8250_resume_port(i); |
1da177e4 LT |
2825 | } |
2826 | ||
2827 | return 0; | |
2828 | } | |
2829 | ||
3ae5eaec | 2830 | static struct platform_driver serial8250_isa_driver = { |
1da177e4 LT |
2831 | .probe = serial8250_probe, |
2832 | .remove = __devexit_p(serial8250_remove), | |
2833 | .suspend = serial8250_suspend, | |
2834 | .resume = serial8250_resume, | |
3ae5eaec RK |
2835 | .driver = { |
2836 | .name = "serial8250", | |
7493a314 | 2837 | .owner = THIS_MODULE, |
3ae5eaec | 2838 | }, |
1da177e4 LT |
2839 | }; |
2840 | ||
2841 | /* | |
2842 | * This "device" covers _all_ ISA 8250-compatible serial devices listed | |
2843 | * in the table in include/asm/serial.h | |
2844 | */ | |
2845 | static struct platform_device *serial8250_isa_devs; | |
2846 | ||
2847 | /* | |
2848 | * serial8250_register_port and serial8250_unregister_port allows for | |
2849 | * 16x50 serial ports to be configured at run-time, to support PCMCIA | |
2850 | * modems and PCI multiport cards. | |
2851 | */ | |
f392ecfa | 2852 | static DEFINE_MUTEX(serial_mutex); |
1da177e4 LT |
2853 | |
2854 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) | |
2855 | { | |
2856 | int i; | |
2857 | ||
2858 | /* | |
2859 | * First, find a port entry which matches. | |
2860 | */ | |
a61c2d78 | 2861 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
2862 | if (uart_match_port(&serial8250_ports[i].port, port)) |
2863 | return &serial8250_ports[i]; | |
2864 | ||
2865 | /* | |
2866 | * We didn't find a matching entry, so look for the first | |
2867 | * free entry. We look for one which hasn't been previously | |
2868 | * used (indicated by zero iobase). | |
2869 | */ | |
a61c2d78 | 2870 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
2871 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && |
2872 | serial8250_ports[i].port.iobase == 0) | |
2873 | return &serial8250_ports[i]; | |
2874 | ||
2875 | /* | |
2876 | * That also failed. Last resort is to find any entry which | |
2877 | * doesn't have a real port associated with it. | |
2878 | */ | |
a61c2d78 | 2879 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
2880 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) |
2881 | return &serial8250_ports[i]; | |
2882 | ||
2883 | return NULL; | |
2884 | } | |
2885 | ||
2886 | /** | |
2887 | * serial8250_register_port - register a serial port | |
2888 | * @port: serial port template | |
2889 | * | |
2890 | * Configure the serial port specified by the request. If the | |
2891 | * port exists and is in use, it is hung up and unregistered | |
2892 | * first. | |
2893 | * | |
2894 | * The port is then probed and if necessary the IRQ is autodetected | |
2895 | * If this fails an error is returned. | |
2896 | * | |
2897 | * On success the port is ready to use and the line number is returned. | |
2898 | */ | |
2899 | int serial8250_register_port(struct uart_port *port) | |
2900 | { | |
2901 | struct uart_8250_port *uart; | |
2902 | int ret = -ENOSPC; | |
2903 | ||
2904 | if (port->uartclk == 0) | |
2905 | return -EINVAL; | |
2906 | ||
f392ecfa | 2907 | mutex_lock(&serial_mutex); |
1da177e4 LT |
2908 | |
2909 | uart = serial8250_find_match_or_unused(port); | |
2910 | if (uart) { | |
2911 | uart_remove_one_port(&serial8250_reg, &uart->port); | |
2912 | ||
74a19741 WN |
2913 | uart->port.iobase = port->iobase; |
2914 | uart->port.membase = port->membase; | |
2915 | uart->port.irq = port->irq; | |
2916 | uart->port.uartclk = port->uartclk; | |
2917 | uart->port.fifosize = port->fifosize; | |
2918 | uart->port.regshift = port->regshift; | |
2919 | uart->port.iotype = port->iotype; | |
2920 | uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; | |
2921 | uart->port.mapbase = port->mapbase; | |
2922 | uart->port.private_data = port->private_data; | |
1da177e4 LT |
2923 | if (port->dev) |
2924 | uart->port.dev = port->dev; | |
2925 | ||
2926 | ret = uart_add_one_port(&serial8250_reg, &uart->port); | |
2927 | if (ret == 0) | |
2928 | ret = uart->port.line; | |
2929 | } | |
f392ecfa | 2930 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
2931 | |
2932 | return ret; | |
2933 | } | |
2934 | EXPORT_SYMBOL(serial8250_register_port); | |
2935 | ||
2936 | /** | |
2937 | * serial8250_unregister_port - remove a 16x50 serial port at runtime | |
2938 | * @line: serial line number | |
2939 | * | |
2940 | * Remove one serial port. This may not be called from interrupt | |
2941 | * context. We hand the port back to the our control. | |
2942 | */ | |
2943 | void serial8250_unregister_port(int line) | |
2944 | { | |
2945 | struct uart_8250_port *uart = &serial8250_ports[line]; | |
2946 | ||
f392ecfa | 2947 | mutex_lock(&serial_mutex); |
1da177e4 LT |
2948 | uart_remove_one_port(&serial8250_reg, &uart->port); |
2949 | if (serial8250_isa_devs) { | |
2950 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; | |
2951 | uart->port.type = PORT_UNKNOWN; | |
2952 | uart->port.dev = &serial8250_isa_devs->dev; | |
2953 | uart_add_one_port(&serial8250_reg, &uart->port); | |
2954 | } else { | |
2955 | uart->port.dev = NULL; | |
2956 | } | |
f392ecfa | 2957 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
2958 | } |
2959 | EXPORT_SYMBOL(serial8250_unregister_port); | |
2960 | ||
2961 | static int __init serial8250_init(void) | |
2962 | { | |
2963 | int ret, i; | |
2964 | ||
a61c2d78 DJ |
2965 | if (nr_uarts > UART_NR) |
2966 | nr_uarts = UART_NR; | |
2967 | ||
d87a6d95 | 2968 | printk(KERN_INFO "Serial: 8250/16550 driver" |
a61c2d78 | 2969 | "%d ports, IRQ sharing %sabled\n", nr_uarts, |
1da177e4 LT |
2970 | share_irqs ? "en" : "dis"); |
2971 | ||
4aba41ea AC |
2972 | for (i = 0; i < NR_IRQS; i++) |
2973 | spin_lock_init(&irq_lists[i].lock); | |
2974 | ||
b70ac771 DM |
2975 | #ifdef CONFIG_SPARC |
2976 | ret = sunserial_register_minors(&serial8250_reg, UART_NR); | |
2977 | #else | |
2978 | serial8250_reg.nr = UART_NR; | |
1da177e4 | 2979 | ret = uart_register_driver(&serial8250_reg); |
b70ac771 | 2980 | #endif |
1da177e4 LT |
2981 | if (ret) |
2982 | goto out; | |
2983 | ||
7493a314 DT |
2984 | serial8250_isa_devs = platform_device_alloc("serial8250", |
2985 | PLAT8250_DEV_LEGACY); | |
2986 | if (!serial8250_isa_devs) { | |
2987 | ret = -ENOMEM; | |
bc965a7f | 2988 | goto unreg_uart_drv; |
1da177e4 LT |
2989 | } |
2990 | ||
7493a314 DT |
2991 | ret = platform_device_add(serial8250_isa_devs); |
2992 | if (ret) | |
2993 | goto put_dev; | |
2994 | ||
1da177e4 LT |
2995 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); |
2996 | ||
bc965a7f RK |
2997 | ret = platform_driver_register(&serial8250_isa_driver); |
2998 | if (ret == 0) | |
2999 | goto out; | |
1da177e4 | 3000 | |
bc965a7f | 3001 | platform_device_del(serial8250_isa_devs); |
7493a314 DT |
3002 | put_dev: |
3003 | platform_device_put(serial8250_isa_devs); | |
7493a314 | 3004 | unreg_uart_drv: |
b70ac771 DM |
3005 | #ifdef CONFIG_SPARC |
3006 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3007 | #else | |
1da177e4 | 3008 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3009 | #endif |
1da177e4 LT |
3010 | out: |
3011 | return ret; | |
3012 | } | |
3013 | ||
3014 | static void __exit serial8250_exit(void) | |
3015 | { | |
3016 | struct platform_device *isa_dev = serial8250_isa_devs; | |
3017 | ||
3018 | /* | |
3019 | * This tells serial8250_unregister_port() not to re-register | |
3020 | * the ports (thereby making serial8250_isa_driver permanently | |
3021 | * in use.) | |
3022 | */ | |
3023 | serial8250_isa_devs = NULL; | |
3024 | ||
3ae5eaec | 3025 | platform_driver_unregister(&serial8250_isa_driver); |
1da177e4 LT |
3026 | platform_device_unregister(isa_dev); |
3027 | ||
b70ac771 DM |
3028 | #ifdef CONFIG_SPARC |
3029 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3030 | #else | |
1da177e4 | 3031 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3032 | #endif |
1da177e4 LT |
3033 | } |
3034 | ||
3035 | module_init(serial8250_init); | |
3036 | module_exit(serial8250_exit); | |
3037 | ||
3038 | EXPORT_SYMBOL(serial8250_suspend_port); | |
3039 | EXPORT_SYMBOL(serial8250_resume_port); | |
3040 | ||
3041 | MODULE_LICENSE("GPL"); | |
d87a6d95 | 3042 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); |
1da177e4 LT |
3043 | |
3044 | module_param(share_irqs, uint, 0644); | |
3045 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" | |
3046 | " (unsafe)"); | |
3047 | ||
a61c2d78 DJ |
3048 | module_param(nr_uarts, uint, 0644); |
3049 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); | |
3050 | ||
1da177e4 LT |
3051 | #ifdef CONFIG_SERIAL_8250_RSA |
3052 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); | |
3053 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); | |
3054 | #endif | |
3055 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); |