Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/amba.c | |
3 | * | |
4 | * Driver for AMBA serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright 1999 ARM Limited | |
9 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $ | |
26 | * | |
27 | * This is a generic driver for ARM AMBA-type serial ports. They | |
28 | * have a lot of 16550-like features, but are not register compatible. | |
29 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
30 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
31 | * required, these have to be supplied via some other means (eg, GPIO) | |
32 | * and hooked into this driver. | |
33 | */ | |
34 | #include <linux/config.h> | |
35 | ||
36 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
37 | #define SUPPORT_SYSRQ | |
38 | #endif | |
39 | ||
40 | #include <linux/module.h> | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/console.h> | |
44 | #include <linux/sysrq.h> | |
45 | #include <linux/device.h> | |
46 | #include <linux/tty.h> | |
47 | #include <linux/tty_flip.h> | |
48 | #include <linux/serial_core.h> | |
49 | #include <linux/serial.h> | |
50 | ||
51 | #include <asm/io.h> | |
52 | #include <asm/irq.h> | |
53 | #include <asm/hardware/amba.h> | |
54 | #include <asm/hardware/clock.h> | |
55 | #include <asm/hardware/amba_serial.h> | |
56 | ||
57 | #define UART_NR 14 | |
58 | ||
59 | #define SERIAL_AMBA_MAJOR 204 | |
60 | #define SERIAL_AMBA_MINOR 64 | |
61 | #define SERIAL_AMBA_NR UART_NR | |
62 | ||
63 | #define AMBA_ISR_PASS_LIMIT 256 | |
64 | ||
65 | #define UART_DUMMY_RSR_RX 256 | |
66 | ||
67 | /* | |
68 | * We wrap our port structure around the generic uart_port. | |
69 | */ | |
70 | struct uart_amba_port { | |
71 | struct uart_port port; | |
72 | struct clk *clk; | |
73 | unsigned int im; /* interrupt mask */ | |
74 | unsigned int old_status; | |
75 | }; | |
76 | ||
77 | static void pl011_stop_tx(struct uart_port *port, unsigned int tty_stop) | |
78 | { | |
79 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
80 | ||
81 | uap->im &= ~UART011_TXIM; | |
82 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
83 | } | |
84 | ||
85 | static void pl011_start_tx(struct uart_port *port, unsigned int tty_start) | |
86 | { | |
87 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
88 | ||
89 | uap->im |= UART011_TXIM; | |
90 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
91 | } | |
92 | ||
93 | static void pl011_stop_rx(struct uart_port *port) | |
94 | { | |
95 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
96 | ||
97 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
98 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
99 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
100 | } | |
101 | ||
102 | static void pl011_enable_ms(struct uart_port *port) | |
103 | { | |
104 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
105 | ||
106 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
107 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
108 | } | |
109 | ||
110 | static void | |
111 | #ifdef SUPPORT_SYSRQ | |
112 | pl011_rx_chars(struct uart_amba_port *uap, struct pt_regs *regs) | |
113 | #else | |
114 | pl011_rx_chars(struct uart_amba_port *uap) | |
115 | #endif | |
116 | { | |
117 | struct tty_struct *tty = uap->port.info->tty; | |
118 | unsigned int status, ch, flag, rsr, max_count = 256; | |
119 | ||
120 | status = readw(uap->port.membase + UART01x_FR); | |
121 | while ((status & UART01x_FR_RXFE) == 0 && max_count--) { | |
122 | if (tty->flip.count >= TTY_FLIPBUF_SIZE) { | |
123 | if (tty->low_latency) | |
124 | tty_flip_buffer_push(tty); | |
125 | /* | |
126 | * If this failed then we will throw away the | |
127 | * bytes but must do so to clear interrupts | |
128 | */ | |
129 | } | |
130 | ||
131 | ch = readw(uap->port.membase + UART01x_DR); | |
132 | flag = TTY_NORMAL; | |
133 | uap->port.icount.rx++; | |
134 | ||
135 | /* | |
136 | * Note that the error handling code is | |
137 | * out of the main execution path | |
138 | */ | |
139 | rsr = readw(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; | |
45849282 | 140 | if (unlikely(rsr & UART01x_RSR_ANY)) { |
1da177e4 LT |
141 | if (rsr & UART01x_RSR_BE) { |
142 | rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); | |
143 | uap->port.icount.brk++; | |
144 | if (uart_handle_break(&uap->port)) | |
145 | goto ignore_char; | |
146 | } else if (rsr & UART01x_RSR_PE) | |
147 | uap->port.icount.parity++; | |
148 | else if (rsr & UART01x_RSR_FE) | |
149 | uap->port.icount.frame++; | |
150 | if (rsr & UART01x_RSR_OE) | |
151 | uap->port.icount.overrun++; | |
152 | ||
153 | rsr &= uap->port.read_status_mask; | |
154 | ||
155 | if (rsr & UART01x_RSR_BE) | |
156 | flag = TTY_BREAK; | |
157 | else if (rsr & UART01x_RSR_PE) | |
158 | flag = TTY_PARITY; | |
159 | else if (rsr & UART01x_RSR_FE) | |
160 | flag = TTY_FRAME; | |
161 | } | |
162 | ||
163 | if (uart_handle_sysrq_char(&uap->port, ch, regs)) | |
164 | goto ignore_char; | |
165 | ||
05ab3014 RK |
166 | uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); |
167 | ||
1da177e4 LT |
168 | ignore_char: |
169 | status = readw(uap->port.membase + UART01x_FR); | |
170 | } | |
171 | tty_flip_buffer_push(tty); | |
172 | return; | |
173 | } | |
174 | ||
175 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
176 | { | |
177 | struct circ_buf *xmit = &uap->port.info->xmit; | |
178 | int count; | |
179 | ||
180 | if (uap->port.x_char) { | |
181 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
182 | uap->port.icount.tx++; | |
183 | uap->port.x_char = 0; | |
184 | return; | |
185 | } | |
186 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
187 | pl011_stop_tx(&uap->port, 0); | |
188 | return; | |
189 | } | |
190 | ||
191 | count = uap->port.fifosize >> 1; | |
192 | do { | |
193 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
194 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
195 | uap->port.icount.tx++; | |
196 | if (uart_circ_empty(xmit)) | |
197 | break; | |
198 | } while (--count > 0); | |
199 | ||
200 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
201 | uart_write_wakeup(&uap->port); | |
202 | ||
203 | if (uart_circ_empty(xmit)) | |
204 | pl011_stop_tx(&uap->port, 0); | |
205 | } | |
206 | ||
207 | static void pl011_modem_status(struct uart_amba_port *uap) | |
208 | { | |
209 | unsigned int status, delta; | |
210 | ||
211 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
212 | ||
213 | delta = status ^ uap->old_status; | |
214 | uap->old_status = status; | |
215 | ||
216 | if (!delta) | |
217 | return; | |
218 | ||
219 | if (delta & UART01x_FR_DCD) | |
220 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
221 | ||
222 | if (delta & UART01x_FR_DSR) | |
223 | uap->port.icount.dsr++; | |
224 | ||
225 | if (delta & UART01x_FR_CTS) | |
226 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
227 | ||
228 | wake_up_interruptible(&uap->port.info->delta_msr_wait); | |
229 | } | |
230 | ||
231 | static irqreturn_t pl011_int(int irq, void *dev_id, struct pt_regs *regs) | |
232 | { | |
233 | struct uart_amba_port *uap = dev_id; | |
234 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; | |
235 | int handled = 0; | |
236 | ||
237 | spin_lock(&uap->port.lock); | |
238 | ||
239 | status = readw(uap->port.membase + UART011_MIS); | |
240 | if (status) { | |
241 | do { | |
242 | writew(status & ~(UART011_TXIS|UART011_RTIS| | |
243 | UART011_RXIS), | |
244 | uap->port.membase + UART011_ICR); | |
245 | ||
246 | if (status & (UART011_RTIS|UART011_RXIS)) | |
247 | #ifdef SUPPORT_SYSRQ | |
248 | pl011_rx_chars(uap, regs); | |
249 | #else | |
250 | pl011_rx_chars(uap); | |
251 | #endif | |
252 | if (status & (UART011_DSRMIS|UART011_DCDMIS| | |
253 | UART011_CTSMIS|UART011_RIMIS)) | |
254 | pl011_modem_status(uap); | |
255 | if (status & UART011_TXIS) | |
256 | pl011_tx_chars(uap); | |
257 | ||
258 | if (pass_counter-- == 0) | |
259 | break; | |
260 | ||
261 | status = readw(uap->port.membase + UART011_MIS); | |
262 | } while (status != 0); | |
263 | handled = 1; | |
264 | } | |
265 | ||
266 | spin_unlock(&uap->port.lock); | |
267 | ||
268 | return IRQ_RETVAL(handled); | |
269 | } | |
270 | ||
271 | static unsigned int pl01x_tx_empty(struct uart_port *port) | |
272 | { | |
273 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
274 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
275 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
276 | } | |
277 | ||
278 | static unsigned int pl01x_get_mctrl(struct uart_port *port) | |
279 | { | |
280 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
281 | unsigned int result = 0; | |
282 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
283 | ||
284 | #define BIT(uartbit, tiocmbit) \ | |
285 | if (status & uartbit) \ | |
286 | result |= tiocmbit | |
287 | ||
288 | BIT(UART01x_FR_DCD, TIOCM_CAR); | |
289 | BIT(UART01x_FR_DSR, TIOCM_DSR); | |
290 | BIT(UART01x_FR_CTS, TIOCM_CTS); | |
291 | BIT(UART011_FR_RI, TIOCM_RNG); | |
292 | #undef BIT | |
293 | return result; | |
294 | } | |
295 | ||
296 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
297 | { | |
298 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
299 | unsigned int cr; | |
300 | ||
301 | cr = readw(uap->port.membase + UART011_CR); | |
302 | ||
303 | #define BIT(tiocmbit, uartbit) \ | |
304 | if (mctrl & tiocmbit) \ | |
305 | cr |= uartbit; \ | |
306 | else \ | |
307 | cr &= ~uartbit | |
308 | ||
309 | BIT(TIOCM_RTS, UART011_CR_RTS); | |
310 | BIT(TIOCM_DTR, UART011_CR_DTR); | |
311 | BIT(TIOCM_OUT1, UART011_CR_OUT1); | |
312 | BIT(TIOCM_OUT2, UART011_CR_OUT2); | |
313 | BIT(TIOCM_LOOP, UART011_CR_LBE); | |
314 | #undef BIT | |
315 | ||
316 | writew(cr, uap->port.membase + UART011_CR); | |
317 | } | |
318 | ||
319 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
320 | { | |
321 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
322 | unsigned long flags; | |
323 | unsigned int lcr_h; | |
324 | ||
325 | spin_lock_irqsave(&uap->port.lock, flags); | |
326 | lcr_h = readw(uap->port.membase + UART011_LCRH); | |
327 | if (break_state == -1) | |
328 | lcr_h |= UART01x_LCRH_BRK; | |
329 | else | |
330 | lcr_h &= ~UART01x_LCRH_BRK; | |
331 | writew(lcr_h, uap->port.membase + UART011_LCRH); | |
332 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
333 | } | |
334 | ||
335 | static int pl011_startup(struct uart_port *port) | |
336 | { | |
337 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
338 | unsigned int cr; | |
339 | int retval; | |
340 | ||
341 | /* | |
342 | * Try to enable the clock producer. | |
343 | */ | |
344 | retval = clk_enable(uap->clk); | |
345 | if (retval) | |
346 | goto out; | |
347 | ||
348 | uap->port.uartclk = clk_get_rate(uap->clk); | |
349 | ||
350 | /* | |
351 | * Allocate the IRQ | |
352 | */ | |
353 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
354 | if (retval) | |
355 | goto clk_dis; | |
356 | ||
357 | writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
358 | uap->port.membase + UART011_IFLS); | |
359 | ||
360 | /* | |
361 | * Provoke TX FIFO interrupt into asserting. | |
362 | */ | |
363 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | |
364 | writew(cr, uap->port.membase + UART011_CR); | |
365 | writew(0, uap->port.membase + UART011_FBRD); | |
366 | writew(1, uap->port.membase + UART011_IBRD); | |
367 | writew(0, uap->port.membase + UART011_LCRH); | |
368 | writew(0, uap->port.membase + UART01x_DR); | |
369 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
370 | barrier(); | |
371 | ||
372 | cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
373 | writew(cr, uap->port.membase + UART011_CR); | |
374 | ||
375 | /* | |
376 | * initialise the old status of the modem signals | |
377 | */ | |
378 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
379 | ||
380 | /* | |
381 | * Finally, enable interrupts | |
382 | */ | |
383 | spin_lock_irq(&uap->port.lock); | |
384 | uap->im = UART011_RXIM | UART011_RTIM; | |
385 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
386 | spin_unlock_irq(&uap->port.lock); | |
387 | ||
388 | return 0; | |
389 | ||
390 | clk_dis: | |
391 | clk_disable(uap->clk); | |
392 | out: | |
393 | return retval; | |
394 | } | |
395 | ||
396 | static void pl011_shutdown(struct uart_port *port) | |
397 | { | |
398 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
399 | unsigned long val; | |
400 | ||
401 | /* | |
402 | * disable all interrupts | |
403 | */ | |
404 | spin_lock_irq(&uap->port.lock); | |
405 | uap->im = 0; | |
406 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
407 | writew(0xffff, uap->port.membase + UART011_ICR); | |
408 | spin_unlock_irq(&uap->port.lock); | |
409 | ||
410 | /* | |
411 | * Free the interrupt | |
412 | */ | |
413 | free_irq(uap->port.irq, uap); | |
414 | ||
415 | /* | |
416 | * disable the port | |
417 | */ | |
418 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); | |
419 | ||
420 | /* | |
421 | * disable break condition and fifos | |
422 | */ | |
423 | val = readw(uap->port.membase + UART011_LCRH); | |
424 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
425 | writew(val, uap->port.membase + UART011_LCRH); | |
426 | ||
427 | /* | |
428 | * Shut down the clock producer | |
429 | */ | |
430 | clk_disable(uap->clk); | |
431 | } | |
432 | ||
433 | static void | |
434 | pl011_set_termios(struct uart_port *port, struct termios *termios, | |
435 | struct termios *old) | |
436 | { | |
437 | unsigned int lcr_h, old_cr; | |
438 | unsigned long flags; | |
439 | unsigned int baud, quot; | |
440 | ||
441 | /* | |
442 | * Ask the core to calculate the divisor for us. | |
443 | */ | |
444 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
445 | quot = port->uartclk * 4 / baud; | |
446 | ||
447 | switch (termios->c_cflag & CSIZE) { | |
448 | case CS5: | |
449 | lcr_h = UART01x_LCRH_WLEN_5; | |
450 | break; | |
451 | case CS6: | |
452 | lcr_h = UART01x_LCRH_WLEN_6; | |
453 | break; | |
454 | case CS7: | |
455 | lcr_h = UART01x_LCRH_WLEN_7; | |
456 | break; | |
457 | default: // CS8 | |
458 | lcr_h = UART01x_LCRH_WLEN_8; | |
459 | break; | |
460 | } | |
461 | if (termios->c_cflag & CSTOPB) | |
462 | lcr_h |= UART01x_LCRH_STP2; | |
463 | if (termios->c_cflag & PARENB) { | |
464 | lcr_h |= UART01x_LCRH_PEN; | |
465 | if (!(termios->c_cflag & PARODD)) | |
466 | lcr_h |= UART01x_LCRH_EPS; | |
467 | } | |
468 | if (port->fifosize > 1) | |
469 | lcr_h |= UART01x_LCRH_FEN; | |
470 | ||
471 | spin_lock_irqsave(&port->lock, flags); | |
472 | ||
473 | /* | |
474 | * Update the per-port timeout. | |
475 | */ | |
476 | uart_update_timeout(port, termios->c_cflag, baud); | |
477 | ||
478 | port->read_status_mask = UART01x_RSR_OE; | |
479 | if (termios->c_iflag & INPCK) | |
480 | port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; | |
481 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
482 | port->read_status_mask |= UART01x_RSR_BE; | |
483 | ||
484 | /* | |
485 | * Characters to ignore | |
486 | */ | |
487 | port->ignore_status_mask = 0; | |
488 | if (termios->c_iflag & IGNPAR) | |
489 | port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; | |
490 | if (termios->c_iflag & IGNBRK) { | |
491 | port->ignore_status_mask |= UART01x_RSR_BE; | |
492 | /* | |
493 | * If we're ignoring parity and break indicators, | |
494 | * ignore overruns too (for real raw support). | |
495 | */ | |
496 | if (termios->c_iflag & IGNPAR) | |
497 | port->ignore_status_mask |= UART01x_RSR_OE; | |
498 | } | |
499 | ||
500 | /* | |
501 | * Ignore all characters if CREAD is not set. | |
502 | */ | |
503 | if ((termios->c_cflag & CREAD) == 0) | |
504 | port->ignore_status_mask |= UART_DUMMY_RSR_RX; | |
505 | ||
506 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
507 | pl011_enable_ms(port); | |
508 | ||
509 | /* first, disable everything */ | |
510 | old_cr = readw(port->membase + UART011_CR); | |
511 | writew(0, port->membase + UART011_CR); | |
512 | ||
513 | /* Set baud rate */ | |
514 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
515 | writew(quot >> 6, port->membase + UART011_IBRD); | |
516 | ||
517 | /* | |
518 | * ----------v----------v----------v----------v----- | |
519 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
520 | * ----------^----------^----------^----------^----- | |
521 | */ | |
522 | writew(lcr_h, port->membase + UART011_LCRH); | |
523 | writew(old_cr, port->membase + UART011_CR); | |
524 | ||
525 | spin_unlock_irqrestore(&port->lock, flags); | |
526 | } | |
527 | ||
528 | static const char *pl011_type(struct uart_port *port) | |
529 | { | |
530 | return port->type == PORT_AMBA ? "AMBA/PL011" : NULL; | |
531 | } | |
532 | ||
533 | /* | |
534 | * Release the memory region(s) being used by 'port' | |
535 | */ | |
536 | static void pl010_release_port(struct uart_port *port) | |
537 | { | |
538 | release_mem_region(port->mapbase, SZ_4K); | |
539 | } | |
540 | ||
541 | /* | |
542 | * Request the memory region(s) being used by 'port' | |
543 | */ | |
544 | static int pl010_request_port(struct uart_port *port) | |
545 | { | |
546 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
547 | != NULL ? 0 : -EBUSY; | |
548 | } | |
549 | ||
550 | /* | |
551 | * Configure/autoconfigure the port. | |
552 | */ | |
553 | static void pl010_config_port(struct uart_port *port, int flags) | |
554 | { | |
555 | if (flags & UART_CONFIG_TYPE) { | |
556 | port->type = PORT_AMBA; | |
557 | pl010_request_port(port); | |
558 | } | |
559 | } | |
560 | ||
561 | /* | |
562 | * verify the new serial_struct (for TIOCSSERIAL). | |
563 | */ | |
564 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
565 | { | |
566 | int ret = 0; | |
567 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
568 | ret = -EINVAL; | |
569 | if (ser->irq < 0 || ser->irq >= NR_IRQS) | |
570 | ret = -EINVAL; | |
571 | if (ser->baud_base < 9600) | |
572 | ret = -EINVAL; | |
573 | return ret; | |
574 | } | |
575 | ||
576 | static struct uart_ops amba_pl011_pops = { | |
577 | .tx_empty = pl01x_tx_empty, | |
578 | .set_mctrl = pl011_set_mctrl, | |
579 | .get_mctrl = pl01x_get_mctrl, | |
580 | .stop_tx = pl011_stop_tx, | |
581 | .start_tx = pl011_start_tx, | |
582 | .stop_rx = pl011_stop_rx, | |
583 | .enable_ms = pl011_enable_ms, | |
584 | .break_ctl = pl011_break_ctl, | |
585 | .startup = pl011_startup, | |
586 | .shutdown = pl011_shutdown, | |
587 | .set_termios = pl011_set_termios, | |
588 | .type = pl011_type, | |
589 | .release_port = pl010_release_port, | |
590 | .request_port = pl010_request_port, | |
591 | .config_port = pl010_config_port, | |
592 | .verify_port = pl010_verify_port, | |
593 | }; | |
594 | ||
595 | static struct uart_amba_port *amba_ports[UART_NR]; | |
596 | ||
597 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
598 | ||
599 | static inline void | |
600 | pl011_console_write_char(struct uart_amba_port *uap, char ch) | |
601 | { | |
602 | unsigned int status; | |
603 | ||
604 | do { | |
605 | status = readw(uap->port.membase + UART01x_FR); | |
606 | } while (status & UART01x_FR_TXFF); | |
607 | writew(ch, uap->port.membase + UART01x_DR); | |
608 | } | |
609 | ||
610 | static void | |
611 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
612 | { | |
613 | struct uart_amba_port *uap = amba_ports[co->index]; | |
614 | unsigned int status, old_cr, new_cr; | |
615 | int i; | |
616 | ||
617 | clk_enable(uap->clk); | |
618 | ||
619 | /* | |
620 | * First save the CR then disable the interrupts | |
621 | */ | |
622 | old_cr = readw(uap->port.membase + UART011_CR); | |
623 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
624 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
625 | writew(new_cr, uap->port.membase + UART011_CR); | |
626 | ||
627 | /* | |
628 | * Now, do each character | |
629 | */ | |
630 | for (i = 0; i < count; i++) { | |
631 | pl011_console_write_char(uap, s[i]); | |
632 | if (s[i] == '\n') | |
633 | pl011_console_write_char(uap, '\r'); | |
634 | } | |
635 | ||
636 | /* | |
637 | * Finally, wait for transmitter to become empty | |
638 | * and restore the TCR | |
639 | */ | |
640 | do { | |
641 | status = readw(uap->port.membase + UART01x_FR); | |
642 | } while (status & UART01x_FR_BUSY); | |
643 | writew(old_cr, uap->port.membase + UART011_CR); | |
644 | ||
645 | clk_disable(uap->clk); | |
646 | } | |
647 | ||
648 | static void __init | |
649 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
650 | int *parity, int *bits) | |
651 | { | |
652 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
653 | unsigned int lcr_h, ibrd, fbrd; | |
654 | ||
655 | lcr_h = readw(uap->port.membase + UART011_LCRH); | |
656 | ||
657 | *parity = 'n'; | |
658 | if (lcr_h & UART01x_LCRH_PEN) { | |
659 | if (lcr_h & UART01x_LCRH_EPS) | |
660 | *parity = 'e'; | |
661 | else | |
662 | *parity = 'o'; | |
663 | } | |
664 | ||
665 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
666 | *bits = 7; | |
667 | else | |
668 | *bits = 8; | |
669 | ||
670 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
671 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
672 | ||
673 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
674 | } | |
675 | } | |
676 | ||
677 | static int __init pl011_console_setup(struct console *co, char *options) | |
678 | { | |
679 | struct uart_amba_port *uap; | |
680 | int baud = 38400; | |
681 | int bits = 8; | |
682 | int parity = 'n'; | |
683 | int flow = 'n'; | |
684 | ||
685 | /* | |
686 | * Check whether an invalid uart number has been specified, and | |
687 | * if so, search for the first available port that does have | |
688 | * console support. | |
689 | */ | |
690 | if (co->index >= UART_NR) | |
691 | co->index = 0; | |
692 | uap = amba_ports[co->index]; | |
693 | ||
694 | uap->port.uartclk = clk_get_rate(uap->clk); | |
695 | ||
696 | if (options) | |
697 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
698 | else | |
699 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
700 | ||
701 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
702 | } | |
703 | ||
704 | extern struct uart_driver amba_reg; | |
705 | static struct console amba_console = { | |
706 | .name = "ttyAMA", | |
707 | .write = pl011_console_write, | |
708 | .device = uart_console_device, | |
709 | .setup = pl011_console_setup, | |
710 | .flags = CON_PRINTBUFFER, | |
711 | .index = -1, | |
712 | .data = &amba_reg, | |
713 | }; | |
714 | ||
715 | #define AMBA_CONSOLE (&amba_console) | |
716 | #else | |
717 | #define AMBA_CONSOLE NULL | |
718 | #endif | |
719 | ||
720 | static struct uart_driver amba_reg = { | |
721 | .owner = THIS_MODULE, | |
722 | .driver_name = "ttyAMA", | |
723 | .dev_name = "ttyAMA", | |
724 | .major = SERIAL_AMBA_MAJOR, | |
725 | .minor = SERIAL_AMBA_MINOR, | |
726 | .nr = UART_NR, | |
727 | .cons = AMBA_CONSOLE, | |
728 | }; | |
729 | ||
730 | static int pl011_probe(struct amba_device *dev, void *id) | |
731 | { | |
732 | struct uart_amba_port *uap; | |
733 | void __iomem *base; | |
734 | int i, ret; | |
735 | ||
736 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
737 | if (amba_ports[i] == NULL) | |
738 | break; | |
739 | ||
740 | if (i == ARRAY_SIZE(amba_ports)) { | |
741 | ret = -EBUSY; | |
742 | goto out; | |
743 | } | |
744 | ||
745 | uap = kmalloc(sizeof(struct uart_amba_port), GFP_KERNEL); | |
746 | if (uap == NULL) { | |
747 | ret = -ENOMEM; | |
748 | goto out; | |
749 | } | |
750 | ||
751 | base = ioremap(dev->res.start, PAGE_SIZE); | |
752 | if (!base) { | |
753 | ret = -ENOMEM; | |
754 | goto free; | |
755 | } | |
756 | ||
757 | memset(uap, 0, sizeof(struct uart_amba_port)); | |
758 | uap->clk = clk_get(&dev->dev, "UARTCLK"); | |
759 | if (IS_ERR(uap->clk)) { | |
760 | ret = PTR_ERR(uap->clk); | |
761 | goto unmap; | |
762 | } | |
763 | ||
764 | ret = clk_use(uap->clk); | |
765 | if (ret) | |
766 | goto putclk; | |
767 | ||
768 | uap->port.dev = &dev->dev; | |
769 | uap->port.mapbase = dev->res.start; | |
770 | uap->port.membase = base; | |
771 | uap->port.iotype = UPIO_MEM; | |
772 | uap->port.irq = dev->irq[0]; | |
773 | uap->port.fifosize = 16; | |
774 | uap->port.ops = &amba_pl011_pops; | |
775 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
776 | uap->port.line = i; | |
777 | ||
778 | amba_ports[i] = uap; | |
779 | ||
780 | amba_set_drvdata(dev, uap); | |
781 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
782 | if (ret) { | |
783 | amba_set_drvdata(dev, NULL); | |
784 | amba_ports[i] = NULL; | |
785 | clk_unuse(uap->clk); | |
786 | putclk: | |
787 | clk_put(uap->clk); | |
788 | unmap: | |
789 | iounmap(base); | |
790 | free: | |
791 | kfree(uap); | |
792 | } | |
793 | out: | |
794 | return ret; | |
795 | } | |
796 | ||
797 | static int pl011_remove(struct amba_device *dev) | |
798 | { | |
799 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
800 | int i; | |
801 | ||
802 | amba_set_drvdata(dev, NULL); | |
803 | ||
804 | uart_remove_one_port(&amba_reg, &uap->port); | |
805 | ||
806 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
807 | if (amba_ports[i] == uap) | |
808 | amba_ports[i] = NULL; | |
809 | ||
810 | iounmap(uap->port.membase); | |
811 | clk_unuse(uap->clk); | |
812 | clk_put(uap->clk); | |
813 | kfree(uap); | |
814 | return 0; | |
815 | } | |
816 | ||
817 | static struct amba_id pl011_ids[] __initdata = { | |
818 | { | |
819 | .id = 0x00041011, | |
820 | .mask = 0x000fffff, | |
821 | }, | |
822 | { 0, 0 }, | |
823 | }; | |
824 | ||
825 | static struct amba_driver pl011_driver = { | |
826 | .drv = { | |
827 | .name = "uart-pl011", | |
828 | }, | |
829 | .id_table = pl011_ids, | |
830 | .probe = pl011_probe, | |
831 | .remove = pl011_remove, | |
832 | }; | |
833 | ||
834 | static int __init pl011_init(void) | |
835 | { | |
836 | int ret; | |
837 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
838 | ||
839 | ret = uart_register_driver(&amba_reg); | |
840 | if (ret == 0) { | |
841 | ret = amba_driver_register(&pl011_driver); | |
842 | if (ret) | |
843 | uart_unregister_driver(&amba_reg); | |
844 | } | |
845 | return ret; | |
846 | } | |
847 | ||
848 | static void __exit pl011_exit(void) | |
849 | { | |
850 | amba_driver_unregister(&pl011_driver); | |
851 | uart_unregister_driver(&amba_reg); | |
852 | } | |
853 | ||
854 | module_init(pl011_init); | |
855 | module_exit(pl011_exit); | |
856 | ||
857 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
858 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
859 | MODULE_LICENSE("GPL"); |