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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/amba.c | |
3 | * | |
4 | * Driver for AMBA serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright 1999 ARM Limited | |
9 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $ | |
26 | * | |
27 | * This is a generic driver for ARM AMBA-type serial ports. They | |
28 | * have a lot of 16550-like features, but are not register compatible. | |
29 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
30 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
31 | * required, these have to be supplied via some other means (eg, GPIO) | |
32 | * and hooked into this driver. | |
33 | */ | |
34 | #include <linux/config.h> | |
35 | ||
36 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
37 | #define SUPPORT_SYSRQ | |
38 | #endif | |
39 | ||
40 | #include <linux/module.h> | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/console.h> | |
44 | #include <linux/sysrq.h> | |
45 | #include <linux/device.h> | |
46 | #include <linux/tty.h> | |
47 | #include <linux/tty_flip.h> | |
48 | #include <linux/serial_core.h> | |
49 | #include <linux/serial.h> | |
50 | ||
51 | #include <asm/io.h> | |
52 | #include <asm/irq.h> | |
c6b8fdad | 53 | #include <asm/sizes.h> |
1da177e4 LT |
54 | #include <asm/hardware/amba.h> |
55 | #include <asm/hardware/clock.h> | |
56 | #include <asm/hardware/amba_serial.h> | |
57 | ||
58 | #define UART_NR 14 | |
59 | ||
60 | #define SERIAL_AMBA_MAJOR 204 | |
61 | #define SERIAL_AMBA_MINOR 64 | |
62 | #define SERIAL_AMBA_NR UART_NR | |
63 | ||
64 | #define AMBA_ISR_PASS_LIMIT 256 | |
65 | ||
66 | #define UART_DUMMY_RSR_RX 256 | |
67 | ||
68 | /* | |
69 | * We wrap our port structure around the generic uart_port. | |
70 | */ | |
71 | struct uart_amba_port { | |
72 | struct uart_port port; | |
73 | struct clk *clk; | |
74 | unsigned int im; /* interrupt mask */ | |
75 | unsigned int old_status; | |
76 | }; | |
77 | ||
b129a8cc | 78 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 LT |
79 | { |
80 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
81 | ||
82 | uap->im &= ~UART011_TXIM; | |
83 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
84 | } | |
85 | ||
b129a8cc | 86 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 LT |
87 | { |
88 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
89 | ||
90 | uap->im |= UART011_TXIM; | |
91 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
92 | } | |
93 | ||
94 | static void pl011_stop_rx(struct uart_port *port) | |
95 | { | |
96 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
97 | ||
98 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
99 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
100 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
101 | } | |
102 | ||
103 | static void pl011_enable_ms(struct uart_port *port) | |
104 | { | |
105 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
106 | ||
107 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
108 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
109 | } | |
110 | ||
111 | static void | |
112 | #ifdef SUPPORT_SYSRQ | |
113 | pl011_rx_chars(struct uart_amba_port *uap, struct pt_regs *regs) | |
114 | #else | |
115 | pl011_rx_chars(struct uart_amba_port *uap) | |
116 | #endif | |
117 | { | |
118 | struct tty_struct *tty = uap->port.info->tty; | |
119 | unsigned int status, ch, flag, rsr, max_count = 256; | |
120 | ||
121 | status = readw(uap->port.membase + UART01x_FR); | |
122 | while ((status & UART01x_FR_RXFE) == 0 && max_count--) { | |
123 | if (tty->flip.count >= TTY_FLIPBUF_SIZE) { | |
124 | if (tty->low_latency) | |
125 | tty_flip_buffer_push(tty); | |
126 | /* | |
127 | * If this failed then we will throw away the | |
128 | * bytes but must do so to clear interrupts | |
129 | */ | |
130 | } | |
131 | ||
132 | ch = readw(uap->port.membase + UART01x_DR); | |
133 | flag = TTY_NORMAL; | |
134 | uap->port.icount.rx++; | |
135 | ||
136 | /* | |
137 | * Note that the error handling code is | |
138 | * out of the main execution path | |
139 | */ | |
140 | rsr = readw(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; | |
45849282 | 141 | if (unlikely(rsr & UART01x_RSR_ANY)) { |
1da177e4 LT |
142 | if (rsr & UART01x_RSR_BE) { |
143 | rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); | |
144 | uap->port.icount.brk++; | |
145 | if (uart_handle_break(&uap->port)) | |
146 | goto ignore_char; | |
147 | } else if (rsr & UART01x_RSR_PE) | |
148 | uap->port.icount.parity++; | |
149 | else if (rsr & UART01x_RSR_FE) | |
150 | uap->port.icount.frame++; | |
151 | if (rsr & UART01x_RSR_OE) | |
152 | uap->port.icount.overrun++; | |
153 | ||
154 | rsr &= uap->port.read_status_mask; | |
155 | ||
156 | if (rsr & UART01x_RSR_BE) | |
157 | flag = TTY_BREAK; | |
158 | else if (rsr & UART01x_RSR_PE) | |
159 | flag = TTY_PARITY; | |
160 | else if (rsr & UART01x_RSR_FE) | |
161 | flag = TTY_FRAME; | |
162 | } | |
163 | ||
164 | if (uart_handle_sysrq_char(&uap->port, ch, regs)) | |
165 | goto ignore_char; | |
166 | ||
05ab3014 RK |
167 | uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); |
168 | ||
1da177e4 LT |
169 | ignore_char: |
170 | status = readw(uap->port.membase + UART01x_FR); | |
171 | } | |
172 | tty_flip_buffer_push(tty); | |
173 | return; | |
174 | } | |
175 | ||
176 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
177 | { | |
178 | struct circ_buf *xmit = &uap->port.info->xmit; | |
179 | int count; | |
180 | ||
181 | if (uap->port.x_char) { | |
182 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
183 | uap->port.icount.tx++; | |
184 | uap->port.x_char = 0; | |
185 | return; | |
186 | } | |
187 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 188 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
189 | return; |
190 | } | |
191 | ||
192 | count = uap->port.fifosize >> 1; | |
193 | do { | |
194 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
195 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
196 | uap->port.icount.tx++; | |
197 | if (uart_circ_empty(xmit)) | |
198 | break; | |
199 | } while (--count > 0); | |
200 | ||
201 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
202 | uart_write_wakeup(&uap->port); | |
203 | ||
204 | if (uart_circ_empty(xmit)) | |
b129a8cc | 205 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
206 | } |
207 | ||
208 | static void pl011_modem_status(struct uart_amba_port *uap) | |
209 | { | |
210 | unsigned int status, delta; | |
211 | ||
212 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
213 | ||
214 | delta = status ^ uap->old_status; | |
215 | uap->old_status = status; | |
216 | ||
217 | if (!delta) | |
218 | return; | |
219 | ||
220 | if (delta & UART01x_FR_DCD) | |
221 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
222 | ||
223 | if (delta & UART01x_FR_DSR) | |
224 | uap->port.icount.dsr++; | |
225 | ||
226 | if (delta & UART01x_FR_CTS) | |
227 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
228 | ||
229 | wake_up_interruptible(&uap->port.info->delta_msr_wait); | |
230 | } | |
231 | ||
232 | static irqreturn_t pl011_int(int irq, void *dev_id, struct pt_regs *regs) | |
233 | { | |
234 | struct uart_amba_port *uap = dev_id; | |
235 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; | |
236 | int handled = 0; | |
237 | ||
238 | spin_lock(&uap->port.lock); | |
239 | ||
240 | status = readw(uap->port.membase + UART011_MIS); | |
241 | if (status) { | |
242 | do { | |
243 | writew(status & ~(UART011_TXIS|UART011_RTIS| | |
244 | UART011_RXIS), | |
245 | uap->port.membase + UART011_ICR); | |
246 | ||
247 | if (status & (UART011_RTIS|UART011_RXIS)) | |
248 | #ifdef SUPPORT_SYSRQ | |
249 | pl011_rx_chars(uap, regs); | |
250 | #else | |
251 | pl011_rx_chars(uap); | |
252 | #endif | |
253 | if (status & (UART011_DSRMIS|UART011_DCDMIS| | |
254 | UART011_CTSMIS|UART011_RIMIS)) | |
255 | pl011_modem_status(uap); | |
256 | if (status & UART011_TXIS) | |
257 | pl011_tx_chars(uap); | |
258 | ||
259 | if (pass_counter-- == 0) | |
260 | break; | |
261 | ||
262 | status = readw(uap->port.membase + UART011_MIS); | |
263 | } while (status != 0); | |
264 | handled = 1; | |
265 | } | |
266 | ||
267 | spin_unlock(&uap->port.lock); | |
268 | ||
269 | return IRQ_RETVAL(handled); | |
270 | } | |
271 | ||
272 | static unsigned int pl01x_tx_empty(struct uart_port *port) | |
273 | { | |
274 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
275 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
276 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
277 | } | |
278 | ||
279 | static unsigned int pl01x_get_mctrl(struct uart_port *port) | |
280 | { | |
281 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
282 | unsigned int result = 0; | |
283 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
284 | ||
285 | #define BIT(uartbit, tiocmbit) \ | |
286 | if (status & uartbit) \ | |
287 | result |= tiocmbit | |
288 | ||
289 | BIT(UART01x_FR_DCD, TIOCM_CAR); | |
290 | BIT(UART01x_FR_DSR, TIOCM_DSR); | |
291 | BIT(UART01x_FR_CTS, TIOCM_CTS); | |
292 | BIT(UART011_FR_RI, TIOCM_RNG); | |
293 | #undef BIT | |
294 | return result; | |
295 | } | |
296 | ||
297 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
298 | { | |
299 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
300 | unsigned int cr; | |
301 | ||
302 | cr = readw(uap->port.membase + UART011_CR); | |
303 | ||
304 | #define BIT(tiocmbit, uartbit) \ | |
305 | if (mctrl & tiocmbit) \ | |
306 | cr |= uartbit; \ | |
307 | else \ | |
308 | cr &= ~uartbit | |
309 | ||
310 | BIT(TIOCM_RTS, UART011_CR_RTS); | |
311 | BIT(TIOCM_DTR, UART011_CR_DTR); | |
312 | BIT(TIOCM_OUT1, UART011_CR_OUT1); | |
313 | BIT(TIOCM_OUT2, UART011_CR_OUT2); | |
314 | BIT(TIOCM_LOOP, UART011_CR_LBE); | |
315 | #undef BIT | |
316 | ||
317 | writew(cr, uap->port.membase + UART011_CR); | |
318 | } | |
319 | ||
320 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
321 | { | |
322 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
323 | unsigned long flags; | |
324 | unsigned int lcr_h; | |
325 | ||
326 | spin_lock_irqsave(&uap->port.lock, flags); | |
327 | lcr_h = readw(uap->port.membase + UART011_LCRH); | |
328 | if (break_state == -1) | |
329 | lcr_h |= UART01x_LCRH_BRK; | |
330 | else | |
331 | lcr_h &= ~UART01x_LCRH_BRK; | |
332 | writew(lcr_h, uap->port.membase + UART011_LCRH); | |
333 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
334 | } | |
335 | ||
336 | static int pl011_startup(struct uart_port *port) | |
337 | { | |
338 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
339 | unsigned int cr; | |
340 | int retval; | |
341 | ||
342 | /* | |
343 | * Try to enable the clock producer. | |
344 | */ | |
345 | retval = clk_enable(uap->clk); | |
346 | if (retval) | |
347 | goto out; | |
348 | ||
349 | uap->port.uartclk = clk_get_rate(uap->clk); | |
350 | ||
351 | /* | |
352 | * Allocate the IRQ | |
353 | */ | |
354 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
355 | if (retval) | |
356 | goto clk_dis; | |
357 | ||
358 | writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
359 | uap->port.membase + UART011_IFLS); | |
360 | ||
361 | /* | |
362 | * Provoke TX FIFO interrupt into asserting. | |
363 | */ | |
364 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | |
365 | writew(cr, uap->port.membase + UART011_CR); | |
366 | writew(0, uap->port.membase + UART011_FBRD); | |
367 | writew(1, uap->port.membase + UART011_IBRD); | |
368 | writew(0, uap->port.membase + UART011_LCRH); | |
369 | writew(0, uap->port.membase + UART01x_DR); | |
370 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
371 | barrier(); | |
372 | ||
373 | cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
374 | writew(cr, uap->port.membase + UART011_CR); | |
375 | ||
376 | /* | |
377 | * initialise the old status of the modem signals | |
378 | */ | |
379 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
380 | ||
381 | /* | |
382 | * Finally, enable interrupts | |
383 | */ | |
384 | spin_lock_irq(&uap->port.lock); | |
385 | uap->im = UART011_RXIM | UART011_RTIM; | |
386 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
387 | spin_unlock_irq(&uap->port.lock); | |
388 | ||
389 | return 0; | |
390 | ||
391 | clk_dis: | |
392 | clk_disable(uap->clk); | |
393 | out: | |
394 | return retval; | |
395 | } | |
396 | ||
397 | static void pl011_shutdown(struct uart_port *port) | |
398 | { | |
399 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
400 | unsigned long val; | |
401 | ||
402 | /* | |
403 | * disable all interrupts | |
404 | */ | |
405 | spin_lock_irq(&uap->port.lock); | |
406 | uap->im = 0; | |
407 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
408 | writew(0xffff, uap->port.membase + UART011_ICR); | |
409 | spin_unlock_irq(&uap->port.lock); | |
410 | ||
411 | /* | |
412 | * Free the interrupt | |
413 | */ | |
414 | free_irq(uap->port.irq, uap); | |
415 | ||
416 | /* | |
417 | * disable the port | |
418 | */ | |
419 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); | |
420 | ||
421 | /* | |
422 | * disable break condition and fifos | |
423 | */ | |
424 | val = readw(uap->port.membase + UART011_LCRH); | |
425 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
426 | writew(val, uap->port.membase + UART011_LCRH); | |
427 | ||
428 | /* | |
429 | * Shut down the clock producer | |
430 | */ | |
431 | clk_disable(uap->clk); | |
432 | } | |
433 | ||
434 | static void | |
435 | pl011_set_termios(struct uart_port *port, struct termios *termios, | |
436 | struct termios *old) | |
437 | { | |
438 | unsigned int lcr_h, old_cr; | |
439 | unsigned long flags; | |
440 | unsigned int baud, quot; | |
441 | ||
442 | /* | |
443 | * Ask the core to calculate the divisor for us. | |
444 | */ | |
445 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
446 | quot = port->uartclk * 4 / baud; | |
447 | ||
448 | switch (termios->c_cflag & CSIZE) { | |
449 | case CS5: | |
450 | lcr_h = UART01x_LCRH_WLEN_5; | |
451 | break; | |
452 | case CS6: | |
453 | lcr_h = UART01x_LCRH_WLEN_6; | |
454 | break; | |
455 | case CS7: | |
456 | lcr_h = UART01x_LCRH_WLEN_7; | |
457 | break; | |
458 | default: // CS8 | |
459 | lcr_h = UART01x_LCRH_WLEN_8; | |
460 | break; | |
461 | } | |
462 | if (termios->c_cflag & CSTOPB) | |
463 | lcr_h |= UART01x_LCRH_STP2; | |
464 | if (termios->c_cflag & PARENB) { | |
465 | lcr_h |= UART01x_LCRH_PEN; | |
466 | if (!(termios->c_cflag & PARODD)) | |
467 | lcr_h |= UART01x_LCRH_EPS; | |
468 | } | |
469 | if (port->fifosize > 1) | |
470 | lcr_h |= UART01x_LCRH_FEN; | |
471 | ||
472 | spin_lock_irqsave(&port->lock, flags); | |
473 | ||
474 | /* | |
475 | * Update the per-port timeout. | |
476 | */ | |
477 | uart_update_timeout(port, termios->c_cflag, baud); | |
478 | ||
479 | port->read_status_mask = UART01x_RSR_OE; | |
480 | if (termios->c_iflag & INPCK) | |
481 | port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; | |
482 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
483 | port->read_status_mask |= UART01x_RSR_BE; | |
484 | ||
485 | /* | |
486 | * Characters to ignore | |
487 | */ | |
488 | port->ignore_status_mask = 0; | |
489 | if (termios->c_iflag & IGNPAR) | |
490 | port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; | |
491 | if (termios->c_iflag & IGNBRK) { | |
492 | port->ignore_status_mask |= UART01x_RSR_BE; | |
493 | /* | |
494 | * If we're ignoring parity and break indicators, | |
495 | * ignore overruns too (for real raw support). | |
496 | */ | |
497 | if (termios->c_iflag & IGNPAR) | |
498 | port->ignore_status_mask |= UART01x_RSR_OE; | |
499 | } | |
500 | ||
501 | /* | |
502 | * Ignore all characters if CREAD is not set. | |
503 | */ | |
504 | if ((termios->c_cflag & CREAD) == 0) | |
505 | port->ignore_status_mask |= UART_DUMMY_RSR_RX; | |
506 | ||
507 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
508 | pl011_enable_ms(port); | |
509 | ||
510 | /* first, disable everything */ | |
511 | old_cr = readw(port->membase + UART011_CR); | |
512 | writew(0, port->membase + UART011_CR); | |
513 | ||
514 | /* Set baud rate */ | |
515 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
516 | writew(quot >> 6, port->membase + UART011_IBRD); | |
517 | ||
518 | /* | |
519 | * ----------v----------v----------v----------v----- | |
520 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
521 | * ----------^----------^----------^----------^----- | |
522 | */ | |
523 | writew(lcr_h, port->membase + UART011_LCRH); | |
524 | writew(old_cr, port->membase + UART011_CR); | |
525 | ||
526 | spin_unlock_irqrestore(&port->lock, flags); | |
527 | } | |
528 | ||
529 | static const char *pl011_type(struct uart_port *port) | |
530 | { | |
531 | return port->type == PORT_AMBA ? "AMBA/PL011" : NULL; | |
532 | } | |
533 | ||
534 | /* | |
535 | * Release the memory region(s) being used by 'port' | |
536 | */ | |
537 | static void pl010_release_port(struct uart_port *port) | |
538 | { | |
539 | release_mem_region(port->mapbase, SZ_4K); | |
540 | } | |
541 | ||
542 | /* | |
543 | * Request the memory region(s) being used by 'port' | |
544 | */ | |
545 | static int pl010_request_port(struct uart_port *port) | |
546 | { | |
547 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
548 | != NULL ? 0 : -EBUSY; | |
549 | } | |
550 | ||
551 | /* | |
552 | * Configure/autoconfigure the port. | |
553 | */ | |
554 | static void pl010_config_port(struct uart_port *port, int flags) | |
555 | { | |
556 | if (flags & UART_CONFIG_TYPE) { | |
557 | port->type = PORT_AMBA; | |
558 | pl010_request_port(port); | |
559 | } | |
560 | } | |
561 | ||
562 | /* | |
563 | * verify the new serial_struct (for TIOCSSERIAL). | |
564 | */ | |
565 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
566 | { | |
567 | int ret = 0; | |
568 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
569 | ret = -EINVAL; | |
570 | if (ser->irq < 0 || ser->irq >= NR_IRQS) | |
571 | ret = -EINVAL; | |
572 | if (ser->baud_base < 9600) | |
573 | ret = -EINVAL; | |
574 | return ret; | |
575 | } | |
576 | ||
577 | static struct uart_ops amba_pl011_pops = { | |
578 | .tx_empty = pl01x_tx_empty, | |
579 | .set_mctrl = pl011_set_mctrl, | |
580 | .get_mctrl = pl01x_get_mctrl, | |
581 | .stop_tx = pl011_stop_tx, | |
582 | .start_tx = pl011_start_tx, | |
583 | .stop_rx = pl011_stop_rx, | |
584 | .enable_ms = pl011_enable_ms, | |
585 | .break_ctl = pl011_break_ctl, | |
586 | .startup = pl011_startup, | |
587 | .shutdown = pl011_shutdown, | |
588 | .set_termios = pl011_set_termios, | |
589 | .type = pl011_type, | |
590 | .release_port = pl010_release_port, | |
591 | .request_port = pl010_request_port, | |
592 | .config_port = pl010_config_port, | |
593 | .verify_port = pl010_verify_port, | |
594 | }; | |
595 | ||
596 | static struct uart_amba_port *amba_ports[UART_NR]; | |
597 | ||
598 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
599 | ||
600 | static inline void | |
601 | pl011_console_write_char(struct uart_amba_port *uap, char ch) | |
602 | { | |
603 | unsigned int status; | |
604 | ||
605 | do { | |
606 | status = readw(uap->port.membase + UART01x_FR); | |
607 | } while (status & UART01x_FR_TXFF); | |
608 | writew(ch, uap->port.membase + UART01x_DR); | |
609 | } | |
610 | ||
611 | static void | |
612 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
613 | { | |
614 | struct uart_amba_port *uap = amba_ports[co->index]; | |
615 | unsigned int status, old_cr, new_cr; | |
616 | int i; | |
617 | ||
618 | clk_enable(uap->clk); | |
619 | ||
620 | /* | |
621 | * First save the CR then disable the interrupts | |
622 | */ | |
623 | old_cr = readw(uap->port.membase + UART011_CR); | |
624 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
625 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
626 | writew(new_cr, uap->port.membase + UART011_CR); | |
627 | ||
628 | /* | |
629 | * Now, do each character | |
630 | */ | |
631 | for (i = 0; i < count; i++) { | |
632 | pl011_console_write_char(uap, s[i]); | |
633 | if (s[i] == '\n') | |
634 | pl011_console_write_char(uap, '\r'); | |
635 | } | |
636 | ||
637 | /* | |
638 | * Finally, wait for transmitter to become empty | |
639 | * and restore the TCR | |
640 | */ | |
641 | do { | |
642 | status = readw(uap->port.membase + UART01x_FR); | |
643 | } while (status & UART01x_FR_BUSY); | |
644 | writew(old_cr, uap->port.membase + UART011_CR); | |
645 | ||
646 | clk_disable(uap->clk); | |
647 | } | |
648 | ||
649 | static void __init | |
650 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
651 | int *parity, int *bits) | |
652 | { | |
653 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
654 | unsigned int lcr_h, ibrd, fbrd; | |
655 | ||
656 | lcr_h = readw(uap->port.membase + UART011_LCRH); | |
657 | ||
658 | *parity = 'n'; | |
659 | if (lcr_h & UART01x_LCRH_PEN) { | |
660 | if (lcr_h & UART01x_LCRH_EPS) | |
661 | *parity = 'e'; | |
662 | else | |
663 | *parity = 'o'; | |
664 | } | |
665 | ||
666 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
667 | *bits = 7; | |
668 | else | |
669 | *bits = 8; | |
670 | ||
671 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
672 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
673 | ||
674 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
675 | } | |
676 | } | |
677 | ||
678 | static int __init pl011_console_setup(struct console *co, char *options) | |
679 | { | |
680 | struct uart_amba_port *uap; | |
681 | int baud = 38400; | |
682 | int bits = 8; | |
683 | int parity = 'n'; | |
684 | int flow = 'n'; | |
685 | ||
686 | /* | |
687 | * Check whether an invalid uart number has been specified, and | |
688 | * if so, search for the first available port that does have | |
689 | * console support. | |
690 | */ | |
691 | if (co->index >= UART_NR) | |
692 | co->index = 0; | |
693 | uap = amba_ports[co->index]; | |
694 | ||
695 | uap->port.uartclk = clk_get_rate(uap->clk); | |
696 | ||
697 | if (options) | |
698 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
699 | else | |
700 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
701 | ||
702 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
703 | } | |
704 | ||
2d93486c | 705 | static struct uart_driver amba_reg; |
1da177e4 LT |
706 | static struct console amba_console = { |
707 | .name = "ttyAMA", | |
708 | .write = pl011_console_write, | |
709 | .device = uart_console_device, | |
710 | .setup = pl011_console_setup, | |
711 | .flags = CON_PRINTBUFFER, | |
712 | .index = -1, | |
713 | .data = &amba_reg, | |
714 | }; | |
715 | ||
716 | #define AMBA_CONSOLE (&amba_console) | |
717 | #else | |
718 | #define AMBA_CONSOLE NULL | |
719 | #endif | |
720 | ||
721 | static struct uart_driver amba_reg = { | |
722 | .owner = THIS_MODULE, | |
723 | .driver_name = "ttyAMA", | |
724 | .dev_name = "ttyAMA", | |
725 | .major = SERIAL_AMBA_MAJOR, | |
726 | .minor = SERIAL_AMBA_MINOR, | |
727 | .nr = UART_NR, | |
728 | .cons = AMBA_CONSOLE, | |
729 | }; | |
730 | ||
731 | static int pl011_probe(struct amba_device *dev, void *id) | |
732 | { | |
733 | struct uart_amba_port *uap; | |
734 | void __iomem *base; | |
735 | int i, ret; | |
736 | ||
737 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
738 | if (amba_ports[i] == NULL) | |
739 | break; | |
740 | ||
741 | if (i == ARRAY_SIZE(amba_ports)) { | |
742 | ret = -EBUSY; | |
743 | goto out; | |
744 | } | |
745 | ||
746 | uap = kmalloc(sizeof(struct uart_amba_port), GFP_KERNEL); | |
747 | if (uap == NULL) { | |
748 | ret = -ENOMEM; | |
749 | goto out; | |
750 | } | |
751 | ||
752 | base = ioremap(dev->res.start, PAGE_SIZE); | |
753 | if (!base) { | |
754 | ret = -ENOMEM; | |
755 | goto free; | |
756 | } | |
757 | ||
758 | memset(uap, 0, sizeof(struct uart_amba_port)); | |
759 | uap->clk = clk_get(&dev->dev, "UARTCLK"); | |
760 | if (IS_ERR(uap->clk)) { | |
761 | ret = PTR_ERR(uap->clk); | |
762 | goto unmap; | |
763 | } | |
764 | ||
765 | ret = clk_use(uap->clk); | |
766 | if (ret) | |
767 | goto putclk; | |
768 | ||
769 | uap->port.dev = &dev->dev; | |
770 | uap->port.mapbase = dev->res.start; | |
771 | uap->port.membase = base; | |
772 | uap->port.iotype = UPIO_MEM; | |
773 | uap->port.irq = dev->irq[0]; | |
774 | uap->port.fifosize = 16; | |
775 | uap->port.ops = &amba_pl011_pops; | |
776 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
777 | uap->port.line = i; | |
778 | ||
779 | amba_ports[i] = uap; | |
780 | ||
781 | amba_set_drvdata(dev, uap); | |
782 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
783 | if (ret) { | |
784 | amba_set_drvdata(dev, NULL); | |
785 | amba_ports[i] = NULL; | |
786 | clk_unuse(uap->clk); | |
787 | putclk: | |
788 | clk_put(uap->clk); | |
789 | unmap: | |
790 | iounmap(base); | |
791 | free: | |
792 | kfree(uap); | |
793 | } | |
794 | out: | |
795 | return ret; | |
796 | } | |
797 | ||
798 | static int pl011_remove(struct amba_device *dev) | |
799 | { | |
800 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
801 | int i; | |
802 | ||
803 | amba_set_drvdata(dev, NULL); | |
804 | ||
805 | uart_remove_one_port(&amba_reg, &uap->port); | |
806 | ||
807 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
808 | if (amba_ports[i] == uap) | |
809 | amba_ports[i] = NULL; | |
810 | ||
811 | iounmap(uap->port.membase); | |
812 | clk_unuse(uap->clk); | |
813 | clk_put(uap->clk); | |
814 | kfree(uap); | |
815 | return 0; | |
816 | } | |
817 | ||
818 | static struct amba_id pl011_ids[] __initdata = { | |
819 | { | |
820 | .id = 0x00041011, | |
821 | .mask = 0x000fffff, | |
822 | }, | |
823 | { 0, 0 }, | |
824 | }; | |
825 | ||
826 | static struct amba_driver pl011_driver = { | |
827 | .drv = { | |
828 | .name = "uart-pl011", | |
829 | }, | |
830 | .id_table = pl011_ids, | |
831 | .probe = pl011_probe, | |
832 | .remove = pl011_remove, | |
833 | }; | |
834 | ||
835 | static int __init pl011_init(void) | |
836 | { | |
837 | int ret; | |
838 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
839 | ||
840 | ret = uart_register_driver(&amba_reg); | |
841 | if (ret == 0) { | |
842 | ret = amba_driver_register(&pl011_driver); | |
843 | if (ret) | |
844 | uart_unregister_driver(&amba_reg); | |
845 | } | |
846 | return ret; | |
847 | } | |
848 | ||
849 | static void __exit pl011_exit(void) | |
850 | { | |
851 | amba_driver_unregister(&pl011_driver); | |
852 | uart_unregister_driver(&amba_reg); | |
853 | } | |
854 | ||
855 | module_init(pl011_init); | |
856 | module_exit(pl011_exit); | |
857 | ||
858 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
859 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
860 | MODULE_LICENSE("GPL"); |