Commit | Line | Data |
---|---|---|
1e6c9c28 | 1 | /* |
c2f5ccfb | 2 | * linux/drivers/char/atmel_serial.c |
1e6c9c28 | 3 | * |
7192f92c | 4 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
5 | * Copyright (C) 2003 Rick Bronson |
6 | * | |
7 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
8 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
9 | * | |
a6670615 CC |
10 | * DMA support added by Chip Coldwell. |
11 | * | |
1e6c9c28 AV |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | */ | |
1e6c9c28 AV |
27 | #include <linux/module.h> |
28 | #include <linux/tty.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/serial.h> | |
afefc415 | 33 | #include <linux/clk.h> |
1e6c9c28 AV |
34 | #include <linux/console.h> |
35 | #include <linux/sysrq.h> | |
36 | #include <linux/tty_flip.h> | |
afefc415 | 37 | #include <linux/platform_device.h> |
a6670615 | 38 | #include <linux/dma-mapping.h> |
93a3ddc2 | 39 | #include <linux/atmel_pdc.h> |
fa3218d8 | 40 | #include <linux/atmel_serial.h> |
1e6c9c28 AV |
41 | |
42 | #include <asm/io.h> | |
43 | ||
afefc415 | 44 | #include <asm/mach/serial_at91.h> |
a09e64fb | 45 | #include <mach/board.h> |
93a3ddc2 | 46 | |
acca9b83 | 47 | #ifdef CONFIG_ARM |
a09e64fb RK |
48 | #include <mach/cpu.h> |
49 | #include <mach/gpio.h> | |
acca9b83 | 50 | #endif |
1e6c9c28 | 51 | |
a6670615 CC |
52 | #define PDC_BUFFER_SIZE 512 |
53 | /* Revisit: We should calculate this based on the actual port settings */ | |
54 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
55 | ||
749c4e60 | 56 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
57 | #define SUPPORT_SYSRQ |
58 | #endif | |
59 | ||
60 | #include <linux/serial_core.h> | |
61 | ||
749c4e60 | 62 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
63 | |
64 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
65 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
66 | * UART. */ | |
7192f92c | 67 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 68 | #define MINOR_START 154 |
7192f92c | 69 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
70 | |
71 | #else | |
72 | ||
73 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
74 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 75 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 76 | #define MINOR_START 64 |
7192f92c | 77 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
78 | |
79 | #endif | |
80 | ||
7192f92c | 81 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 82 | |
b843aa21 | 83 | /* UART registers. CR is write-only, hence no GET macro */ |
544fc728 HS |
84 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
85 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
86 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
87 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
88 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
89 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
90 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
91 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
92 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
93 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
94 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
95 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
96 | ||
1e6c9c28 | 97 | /* PDC registers */ |
544fc728 HS |
98 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
99 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
100 | ||
101 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
102 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
103 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
104 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
105 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
106 | ||
107 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
108 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
39d4c922 | 109 | #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) |
1e6c9c28 | 110 | |
71f2e2b8 HS |
111 | static int (*atmel_open_hook)(struct uart_port *); |
112 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 113 | |
a6670615 CC |
114 | struct atmel_dma_buffer { |
115 | unsigned char *buf; | |
116 | dma_addr_t dma_addr; | |
117 | unsigned int dma_size; | |
118 | unsigned int ofs; | |
119 | }; | |
120 | ||
1ecc26bd RB |
121 | struct atmel_uart_char { |
122 | u16 status; | |
123 | u16 ch; | |
124 | }; | |
125 | ||
126 | #define ATMEL_SERIAL_RINGSIZE 1024 | |
127 | ||
afefc415 AV |
128 | /* |
129 | * We wrap our port structure around the generic uart_port. | |
130 | */ | |
7192f92c | 131 | struct atmel_uart_port { |
afefc415 AV |
132 | struct uart_port uart; /* uart */ |
133 | struct clk *clk; /* uart clock */ | |
f05596db AS |
134 | int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ |
135 | u32 backup_imr; /* IMR saved during suspend */ | |
9e6077bd | 136 | int break_active; /* break being received */ |
1ecc26bd | 137 | |
a6670615 CC |
138 | short use_dma_rx; /* enable PDC receiver */ |
139 | short pdc_rx_idx; /* current PDC RX buffer */ | |
140 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
141 | ||
142 | short use_dma_tx; /* enable PDC transmitter */ | |
143 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ | |
144 | ||
1ecc26bd RB |
145 | struct tasklet_struct tasklet; |
146 | unsigned int irq_status; | |
147 | unsigned int irq_status_prev; | |
148 | ||
149 | struct circ_buf rx_ring; | |
afefc415 AV |
150 | }; |
151 | ||
7192f92c | 152 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
afefc415 | 153 | |
1e6c9c28 | 154 | #ifdef SUPPORT_SYSRQ |
7192f92c | 155 | static struct console atmel_console; |
1e6c9c28 AV |
156 | #endif |
157 | ||
c811ab8c HS |
158 | static inline struct atmel_uart_port * |
159 | to_atmel_uart_port(struct uart_port *uart) | |
160 | { | |
161 | return container_of(uart, struct atmel_uart_port, uart); | |
162 | } | |
163 | ||
a6670615 CC |
164 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
165 | static bool atmel_use_dma_rx(struct uart_port *port) | |
166 | { | |
c811ab8c | 167 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
168 | |
169 | return atmel_port->use_dma_rx; | |
170 | } | |
171 | ||
172 | static bool atmel_use_dma_tx(struct uart_port *port) | |
173 | { | |
c811ab8c | 174 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
175 | |
176 | return atmel_port->use_dma_tx; | |
177 | } | |
178 | #else | |
179 | static bool atmel_use_dma_rx(struct uart_port *port) | |
180 | { | |
181 | return false; | |
182 | } | |
183 | ||
184 | static bool atmel_use_dma_tx(struct uart_port *port) | |
185 | { | |
186 | return false; | |
187 | } | |
188 | #endif | |
189 | ||
1e6c9c28 AV |
190 | /* |
191 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
192 | */ | |
7192f92c | 193 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 194 | { |
7192f92c | 195 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
196 | } |
197 | ||
198 | /* | |
199 | * Set state of the modem control output lines | |
200 | */ | |
7192f92c | 201 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
202 | { |
203 | unsigned int control = 0; | |
afefc415 | 204 | unsigned int mode; |
1e6c9c28 | 205 | |
c2f5ccfb | 206 | #ifdef CONFIG_ARCH_AT91RM9200 |
79da7a61 | 207 | if (cpu_is_at91rm9200()) { |
afefc415 | 208 | /* |
b843aa21 RB |
209 | * AT91RM9200 Errata #39: RTS0 is not internally connected |
210 | * to PA21. We need to drive the pin manually. | |
afefc415 | 211 | */ |
72729910 | 212 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 213 | if (mctrl & TIOCM_RTS) |
20e65276 | 214 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 215 | else |
20e65276 | 216 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 217 | } |
1e6c9c28 | 218 | } |
acca9b83 | 219 | #endif |
1e6c9c28 AV |
220 | |
221 | if (mctrl & TIOCM_RTS) | |
7192f92c | 222 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 223 | else |
7192f92c | 224 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
225 | |
226 | if (mctrl & TIOCM_DTR) | |
7192f92c | 227 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 228 | else |
7192f92c | 229 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 230 | |
afefc415 AV |
231 | UART_PUT_CR(port, control); |
232 | ||
233 | /* Local loopback mode? */ | |
7192f92c | 234 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 235 | if (mctrl & TIOCM_LOOP) |
7192f92c | 236 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 237 | else |
7192f92c | 238 | mode |= ATMEL_US_CHMODE_NORMAL; |
afefc415 | 239 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
240 | } |
241 | ||
242 | /* | |
243 | * Get state of the modem control input lines | |
244 | */ | |
7192f92c | 245 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
246 | { |
247 | unsigned int status, ret = 0; | |
248 | ||
249 | status = UART_GET_CSR(port); | |
250 | ||
251 | /* | |
252 | * The control signals are active low. | |
253 | */ | |
7192f92c | 254 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 255 | ret |= TIOCM_CD; |
7192f92c | 256 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 257 | ret |= TIOCM_CTS; |
7192f92c | 258 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 259 | ret |= TIOCM_DSR; |
7192f92c | 260 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
261 | ret |= TIOCM_RI; |
262 | ||
263 | return ret; | |
264 | } | |
265 | ||
266 | /* | |
267 | * Stop transmitting. | |
268 | */ | |
7192f92c | 269 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 270 | { |
a6670615 CC |
271 | if (atmel_use_dma_tx(port)) { |
272 | /* disable PDC transmit */ | |
273 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
274 | UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); | |
275 | } else | |
276 | UART_PUT_IDR(port, ATMEL_US_TXRDY); | |
1e6c9c28 AV |
277 | } |
278 | ||
279 | /* | |
280 | * Start transmitting. | |
281 | */ | |
7192f92c | 282 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 283 | { |
a6670615 CC |
284 | if (atmel_use_dma_tx(port)) { |
285 | if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) | |
286 | /* The transmitter is already running. Yes, we | |
287 | really need this.*/ | |
288 | return; | |
289 | ||
290 | UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); | |
291 | /* re-enable PDC transmit */ | |
292 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
293 | } else | |
294 | UART_PUT_IER(port, ATMEL_US_TXRDY); | |
1e6c9c28 AV |
295 | } |
296 | ||
297 | /* | |
298 | * Stop receiving - port is in process of being closed. | |
299 | */ | |
7192f92c | 300 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 301 | { |
a6670615 CC |
302 | if (atmel_use_dma_rx(port)) { |
303 | /* disable PDC receive */ | |
304 | UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); | |
305 | UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
306 | } else | |
307 | UART_PUT_IDR(port, ATMEL_US_RXRDY); | |
1e6c9c28 AV |
308 | } |
309 | ||
310 | /* | |
311 | * Enable modem status interrupts | |
312 | */ | |
7192f92c | 313 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 314 | { |
b843aa21 RB |
315 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC |
316 | | ATMEL_US_DCDIC | ATMEL_US_CTSIC); | |
1e6c9c28 AV |
317 | } |
318 | ||
319 | /* | |
320 | * Control the transmission of a break signal | |
321 | */ | |
7192f92c | 322 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
323 | { |
324 | if (break_state != 0) | |
7192f92c | 325 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 326 | else |
7192f92c | 327 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
328 | } |
329 | ||
1ecc26bd RB |
330 | /* |
331 | * Stores the incoming character in the ring buffer | |
332 | */ | |
333 | static void | |
334 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
335 | unsigned int ch) | |
336 | { | |
c811ab8c | 337 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
338 | struct circ_buf *ring = &atmel_port->rx_ring; |
339 | struct atmel_uart_char *c; | |
340 | ||
341 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
342 | /* Buffer overflow, ignore char */ | |
343 | return; | |
344 | ||
345 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
346 | c->status = status; | |
347 | c->ch = ch; | |
348 | ||
349 | /* Make sure the character is stored before we update head. */ | |
350 | smp_wmb(); | |
351 | ||
352 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
353 | } | |
354 | ||
a6670615 CC |
355 | /* |
356 | * Deal with parity, framing and overrun errors. | |
357 | */ | |
358 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
359 | { | |
360 | /* clear error */ | |
361 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
362 | ||
363 | if (status & ATMEL_US_RXBRK) { | |
364 | /* ignore side-effect */ | |
365 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
366 | port->icount.brk++; | |
367 | } | |
368 | if (status & ATMEL_US_PARE) | |
369 | port->icount.parity++; | |
370 | if (status & ATMEL_US_FRAME) | |
371 | port->icount.frame++; | |
372 | if (status & ATMEL_US_OVRE) | |
373 | port->icount.overrun++; | |
374 | } | |
375 | ||
1e6c9c28 AV |
376 | /* |
377 | * Characters received (called from interrupt handler) | |
378 | */ | |
7d12e780 | 379 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 380 | { |
c811ab8c | 381 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 382 | unsigned int status, ch; |
1e6c9c28 | 383 | |
afefc415 | 384 | status = UART_GET_CSR(port); |
7192f92c | 385 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
386 | ch = UART_GET_CHAR(port); |
387 | ||
1e6c9c28 AV |
388 | /* |
389 | * note that the error handling code is | |
390 | * out of the main execution path | |
391 | */ | |
9e6077bd HS |
392 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
393 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
394 | || atmel_port->break_active)) { | |
1ecc26bd | 395 | |
b843aa21 RB |
396 | /* clear error */ |
397 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1ecc26bd | 398 | |
9e6077bd HS |
399 | if (status & ATMEL_US_RXBRK |
400 | && !atmel_port->break_active) { | |
9e6077bd HS |
401 | atmel_port->break_active = 1; |
402 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
9e6077bd HS |
403 | } else { |
404 | /* | |
405 | * This is either the end-of-break | |
406 | * condition or we've received at | |
407 | * least one character without RXBRK | |
408 | * being set. In both cases, the next | |
409 | * RXBRK will indicate start-of-break. | |
410 | */ | |
411 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
412 | status &= ~ATMEL_US_RXBRK; | |
413 | atmel_port->break_active = 0; | |
afefc415 | 414 | } |
1e6c9c28 AV |
415 | } |
416 | ||
1ecc26bd | 417 | atmel_buffer_rx_char(port, status, ch); |
afefc415 | 418 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
419 | } |
420 | ||
1ecc26bd | 421 | tasklet_schedule(&atmel_port->tasklet); |
1e6c9c28 AV |
422 | } |
423 | ||
424 | /* | |
1ecc26bd RB |
425 | * Transmit characters (called from tasklet with TXRDY interrupt |
426 | * disabled) | |
1e6c9c28 | 427 | */ |
7192f92c | 428 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 AV |
429 | { |
430 | struct circ_buf *xmit = &port->info->xmit; | |
431 | ||
1ecc26bd | 432 | if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) { |
1e6c9c28 AV |
433 | UART_PUT_CHAR(port, port->x_char); |
434 | port->icount.tx++; | |
435 | port->x_char = 0; | |
1e6c9c28 | 436 | } |
1ecc26bd | 437 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 438 | return; |
1e6c9c28 | 439 | |
7192f92c | 440 | while (UART_GET_CSR(port) & ATMEL_US_TXRDY) { |
1e6c9c28 AV |
441 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
442 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
443 | port->icount.tx++; | |
444 | if (uart_circ_empty(xmit)) | |
445 | break; | |
446 | } | |
447 | ||
448 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
449 | uart_write_wakeup(port); | |
450 | ||
1ecc26bd RB |
451 | if (!uart_circ_empty(xmit)) |
452 | UART_PUT_IER(port, ATMEL_US_TXRDY); | |
1e6c9c28 AV |
453 | } |
454 | ||
b843aa21 RB |
455 | /* |
456 | * receive interrupt handler. | |
457 | */ | |
458 | static void | |
459 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
460 | { | |
c811ab8c | 461 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 462 | |
a6670615 CC |
463 | if (atmel_use_dma_rx(port)) { |
464 | /* | |
465 | * PDC receive. Just schedule the tasklet and let it | |
466 | * figure out the details. | |
467 | * | |
468 | * TODO: We're not handling error flags correctly at | |
469 | * the moment. | |
470 | */ | |
471 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
472 | UART_PUT_IDR(port, (ATMEL_US_ENDRX | |
473 | | ATMEL_US_TIMEOUT)); | |
474 | tasklet_schedule(&atmel_port->tasklet); | |
475 | } | |
476 | ||
477 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
478 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
479 | atmel_pdc_rxerr(port, pending); | |
480 | } | |
481 | ||
b843aa21 RB |
482 | /* Interrupt receive */ |
483 | if (pending & ATMEL_US_RXRDY) | |
484 | atmel_rx_chars(port); | |
485 | else if (pending & ATMEL_US_RXBRK) { | |
486 | /* | |
487 | * End of break detected. If it came along with a | |
488 | * character, atmel_rx_chars will handle it. | |
489 | */ | |
490 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
491 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
492 | atmel_port->break_active = 0; | |
493 | } | |
494 | } | |
495 | ||
496 | /* | |
1ecc26bd | 497 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
498 | */ |
499 | static void | |
500 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
501 | { | |
c811ab8c | 502 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 503 | |
a6670615 CC |
504 | if (atmel_use_dma_tx(port)) { |
505 | /* PDC transmit */ | |
506 | if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) { | |
507 | UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); | |
508 | tasklet_schedule(&atmel_port->tasklet); | |
509 | } | |
510 | } else { | |
511 | /* Interrupt transmit */ | |
512 | if (pending & ATMEL_US_TXRDY) { | |
513 | UART_PUT_IDR(port, ATMEL_US_TXRDY); | |
514 | tasklet_schedule(&atmel_port->tasklet); | |
515 | } | |
1ecc26bd | 516 | } |
b843aa21 RB |
517 | } |
518 | ||
519 | /* | |
520 | * status flags interrupt handler. | |
521 | */ | |
522 | static void | |
523 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
524 | unsigned int status) | |
525 | { | |
c811ab8c | 526 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 527 | |
b843aa21 | 528 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd RB |
529 | | ATMEL_US_CTSIC)) { |
530 | atmel_port->irq_status = status; | |
531 | tasklet_schedule(&atmel_port->tasklet); | |
532 | } | |
b843aa21 RB |
533 | } |
534 | ||
1e6c9c28 AV |
535 | /* |
536 | * Interrupt handler | |
537 | */ | |
7d12e780 | 538 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
539 | { |
540 | struct uart_port *port = dev_id; | |
541 | unsigned int status, pending, pass_counter = 0; | |
542 | ||
a6670615 CC |
543 | do { |
544 | status = UART_GET_CSR(port); | |
545 | pending = status & UART_GET_IMR(port); | |
546 | if (!pending) | |
547 | break; | |
548 | ||
b843aa21 RB |
549 | atmel_handle_receive(port, pending); |
550 | atmel_handle_status(port, pending, status); | |
551 | atmel_handle_transmit(port, pending); | |
a6670615 | 552 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 553 | |
0400b697 | 554 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 555 | } |
1e6c9c28 | 556 | |
a6670615 CC |
557 | /* |
558 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
559 | */ | |
560 | static void atmel_tx_dma(struct uart_port *port) | |
561 | { | |
c811ab8c | 562 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
563 | struct circ_buf *xmit = &port->info->xmit; |
564 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
565 | int count; | |
566 | ||
ba0657ff MT |
567 | /* nothing left to transmit? */ |
568 | if (UART_GET_TCR(port)) | |
569 | return; | |
570 | ||
a6670615 CC |
571 | xmit->tail += pdc->ofs; |
572 | xmit->tail &= UART_XMIT_SIZE - 1; | |
573 | ||
574 | port->icount.tx += pdc->ofs; | |
575 | pdc->ofs = 0; | |
576 | ||
ba0657ff | 577 | /* more to transmit - setup next transfer */ |
a6670615 | 578 | |
ba0657ff MT |
579 | /* disable PDC transmit */ |
580 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
581 | ||
582 | if (!uart_circ_empty(xmit)) { | |
a6670615 CC |
583 | dma_sync_single_for_device(port->dev, |
584 | pdc->dma_addr, | |
585 | pdc->dma_size, | |
586 | DMA_TO_DEVICE); | |
587 | ||
588 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
589 | pdc->ofs = count; | |
590 | ||
591 | UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); | |
592 | UART_PUT_TCR(port, count); | |
593 | /* re-enable PDC transmit and interrupts */ | |
594 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
595 | UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); | |
1e6c9c28 | 596 | } |
a6670615 CC |
597 | |
598 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
599 | uart_write_wakeup(port); | |
1e6c9c28 AV |
600 | } |
601 | ||
1ecc26bd RB |
602 | static void atmel_rx_from_ring(struct uart_port *port) |
603 | { | |
c811ab8c | 604 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
605 | struct circ_buf *ring = &atmel_port->rx_ring; |
606 | unsigned int flg; | |
607 | unsigned int status; | |
608 | ||
609 | while (ring->head != ring->tail) { | |
610 | struct atmel_uart_char c; | |
611 | ||
612 | /* Make sure c is loaded after head. */ | |
613 | smp_rmb(); | |
614 | ||
615 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
616 | ||
617 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
618 | ||
619 | port->icount.rx++; | |
620 | status = c.status; | |
621 | flg = TTY_NORMAL; | |
622 | ||
623 | /* | |
624 | * note that the error handling code is | |
625 | * out of the main execution path | |
626 | */ | |
627 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
628 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
629 | if (status & ATMEL_US_RXBRK) { | |
630 | /* ignore side-effect */ | |
631 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
632 | ||
633 | port->icount.brk++; | |
634 | if (uart_handle_break(port)) | |
635 | continue; | |
636 | } | |
637 | if (status & ATMEL_US_PARE) | |
638 | port->icount.parity++; | |
639 | if (status & ATMEL_US_FRAME) | |
640 | port->icount.frame++; | |
641 | if (status & ATMEL_US_OVRE) | |
642 | port->icount.overrun++; | |
643 | ||
644 | status &= port->read_status_mask; | |
645 | ||
646 | if (status & ATMEL_US_RXBRK) | |
647 | flg = TTY_BREAK; | |
648 | else if (status & ATMEL_US_PARE) | |
649 | flg = TTY_PARITY; | |
650 | else if (status & ATMEL_US_FRAME) | |
651 | flg = TTY_FRAME; | |
652 | } | |
653 | ||
654 | ||
655 | if (uart_handle_sysrq_char(port, c.ch)) | |
656 | continue; | |
657 | ||
658 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
659 | } | |
660 | ||
661 | /* | |
662 | * Drop the lock here since it might end up calling | |
663 | * uart_start(), which takes the lock. | |
664 | */ | |
665 | spin_unlock(&port->lock); | |
b1d1619b | 666 | tty_flip_buffer_push(port->info->port.tty); |
1ecc26bd RB |
667 | spin_lock(&port->lock); |
668 | } | |
669 | ||
a6670615 CC |
670 | static void atmel_rx_from_dma(struct uart_port *port) |
671 | { | |
c811ab8c | 672 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b1d1619b | 673 | struct tty_struct *tty = port->info->port.tty; |
a6670615 CC |
674 | struct atmel_dma_buffer *pdc; |
675 | int rx_idx = atmel_port->pdc_rx_idx; | |
676 | unsigned int head; | |
677 | unsigned int tail; | |
678 | unsigned int count; | |
679 | ||
680 | do { | |
681 | /* Reset the UART timeout early so that we don't miss one */ | |
682 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
683 | ||
684 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
685 | head = UART_GET_RPR(port) - pdc->dma_addr; | |
686 | tail = pdc->ofs; | |
687 | ||
688 | /* If the PDC has switched buffers, RPR won't contain | |
689 | * any address within the current buffer. Since head | |
690 | * is unsigned, we just need a one-way comparison to | |
691 | * find out. | |
692 | * | |
693 | * In this case, we just need to consume the entire | |
694 | * buffer and resubmit it for DMA. This will clear the | |
695 | * ENDRX bit as well, so that we can safely re-enable | |
696 | * all interrupts below. | |
697 | */ | |
698 | head = min(head, pdc->dma_size); | |
699 | ||
700 | if (likely(head != tail)) { | |
701 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
702 | pdc->dma_size, DMA_FROM_DEVICE); | |
703 | ||
704 | /* | |
705 | * head will only wrap around when we recycle | |
706 | * the DMA buffer, and when that happens, we | |
707 | * explicitly set tail to 0. So head will | |
708 | * always be greater than tail. | |
709 | */ | |
710 | count = head - tail; | |
711 | ||
712 | tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); | |
713 | ||
714 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
715 | pdc->dma_size, DMA_FROM_DEVICE); | |
716 | ||
717 | port->icount.rx += count; | |
718 | pdc->ofs = head; | |
719 | } | |
720 | ||
721 | /* | |
722 | * If the current buffer is full, we need to check if | |
723 | * the next one contains any additional data. | |
724 | */ | |
725 | if (head >= pdc->dma_size) { | |
726 | pdc->ofs = 0; | |
727 | UART_PUT_RNPR(port, pdc->dma_addr); | |
728 | UART_PUT_RNCR(port, pdc->dma_size); | |
729 | ||
730 | rx_idx = !rx_idx; | |
731 | atmel_port->pdc_rx_idx = rx_idx; | |
732 | } | |
733 | } while (head >= pdc->dma_size); | |
734 | ||
735 | /* | |
736 | * Drop the lock here since it might end up calling | |
737 | * uart_start(), which takes the lock. | |
738 | */ | |
739 | spin_unlock(&port->lock); | |
740 | tty_flip_buffer_push(tty); | |
741 | spin_lock(&port->lock); | |
742 | ||
743 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
744 | } | |
745 | ||
1ecc26bd RB |
746 | /* |
747 | * tasklet handling tty stuff outside the interrupt handler. | |
748 | */ | |
749 | static void atmel_tasklet_func(unsigned long data) | |
750 | { | |
751 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 752 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
753 | unsigned int status; |
754 | unsigned int status_change; | |
755 | ||
756 | /* The interrupt handler does not take the lock */ | |
757 | spin_lock(&port->lock); | |
758 | ||
a6670615 CC |
759 | if (atmel_use_dma_tx(port)) |
760 | atmel_tx_dma(port); | |
761 | else | |
762 | atmel_tx_chars(port); | |
1ecc26bd RB |
763 | |
764 | status = atmel_port->irq_status; | |
765 | status_change = status ^ atmel_port->irq_status_prev; | |
766 | ||
767 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR | |
768 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
769 | /* TODO: All reads to CSR will clear these interrupts! */ | |
770 | if (status_change & ATMEL_US_RI) | |
771 | port->icount.rng++; | |
772 | if (status_change & ATMEL_US_DSR) | |
773 | port->icount.dsr++; | |
774 | if (status_change & ATMEL_US_DCD) | |
775 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
776 | if (status_change & ATMEL_US_CTS) | |
777 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
778 | ||
779 | wake_up_interruptible(&port->info->delta_msr_wait); | |
780 | ||
781 | atmel_port->irq_status_prev = status; | |
782 | } | |
783 | ||
a6670615 CC |
784 | if (atmel_use_dma_rx(port)) |
785 | atmel_rx_from_dma(port); | |
786 | else | |
787 | atmel_rx_from_ring(port); | |
1ecc26bd RB |
788 | |
789 | spin_unlock(&port->lock); | |
790 | } | |
791 | ||
1e6c9c28 AV |
792 | /* |
793 | * Perform initialization and enable port for reception | |
794 | */ | |
7192f92c | 795 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 796 | { |
c811ab8c | 797 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b1d1619b | 798 | struct tty_struct *tty = port->info->port.tty; |
1e6c9c28 AV |
799 | int retval; |
800 | ||
801 | /* | |
802 | * Ensure that no interrupts are enabled otherwise when | |
803 | * request_irq() is called we could get stuck trying to | |
804 | * handle an unexpected interrupt | |
805 | */ | |
806 | UART_PUT_IDR(port, -1); | |
807 | ||
808 | /* | |
809 | * Allocate the IRQ | |
810 | */ | |
b843aa21 | 811 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, |
ae161068 | 812 | tty ? tty->name : "atmel_serial", port); |
1e6c9c28 | 813 | if (retval) { |
7192f92c | 814 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
815 | return retval; |
816 | } | |
817 | ||
a6670615 CC |
818 | /* |
819 | * Initialize DMA (if necessary) | |
820 | */ | |
821 | if (atmel_use_dma_rx(port)) { | |
822 | int i; | |
823 | ||
824 | for (i = 0; i < 2; i++) { | |
825 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
826 | ||
827 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
828 | if (pdc->buf == NULL) { | |
829 | if (i != 0) { | |
830 | dma_unmap_single(port->dev, | |
831 | atmel_port->pdc_rx[0].dma_addr, | |
832 | PDC_BUFFER_SIZE, | |
833 | DMA_FROM_DEVICE); | |
834 | kfree(atmel_port->pdc_rx[0].buf); | |
835 | } | |
836 | free_irq(port->irq, port); | |
837 | return -ENOMEM; | |
838 | } | |
839 | pdc->dma_addr = dma_map_single(port->dev, | |
840 | pdc->buf, | |
841 | PDC_BUFFER_SIZE, | |
842 | DMA_FROM_DEVICE); | |
843 | pdc->dma_size = PDC_BUFFER_SIZE; | |
844 | pdc->ofs = 0; | |
845 | } | |
846 | ||
847 | atmel_port->pdc_rx_idx = 0; | |
848 | ||
849 | UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); | |
850 | UART_PUT_RCR(port, PDC_BUFFER_SIZE); | |
851 | ||
852 | UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); | |
853 | UART_PUT_RNCR(port, PDC_BUFFER_SIZE); | |
854 | } | |
855 | if (atmel_use_dma_tx(port)) { | |
856 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
857 | struct circ_buf *xmit = &port->info->xmit; | |
858 | ||
859 | pdc->buf = xmit->buf; | |
860 | pdc->dma_addr = dma_map_single(port->dev, | |
861 | pdc->buf, | |
862 | UART_XMIT_SIZE, | |
863 | DMA_TO_DEVICE); | |
864 | pdc->dma_size = UART_XMIT_SIZE; | |
865 | pdc->ofs = 0; | |
866 | } | |
867 | ||
1e6c9c28 AV |
868 | /* |
869 | * If there is a specific "open" function (to register | |
870 | * control line interrupts) | |
871 | */ | |
71f2e2b8 HS |
872 | if (atmel_open_hook) { |
873 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
874 | if (retval) { |
875 | free_irq(port->irq, port); | |
876 | return retval; | |
877 | } | |
878 | } | |
879 | ||
1e6c9c28 AV |
880 | /* |
881 | * Finally, enable the serial port | |
882 | */ | |
7192f92c | 883 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 RB |
884 | /* enable xmit & rcvr */ |
885 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
afefc415 | 886 | |
a6670615 CC |
887 | if (atmel_use_dma_rx(port)) { |
888 | /* set UART timeout */ | |
889 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
890 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
891 | ||
892 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
893 | /* enable PDC controller */ | |
894 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
895 | } else { | |
896 | /* enable receive only */ | |
897 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
898 | } | |
afefc415 | 899 | |
1e6c9c28 AV |
900 | return 0; |
901 | } | |
902 | ||
903 | /* | |
904 | * Disable the port | |
905 | */ | |
7192f92c | 906 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 907 | { |
c811ab8c | 908 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
909 | /* |
910 | * Ensure everything is stopped. | |
911 | */ | |
912 | atmel_stop_rx(port); | |
913 | atmel_stop_tx(port); | |
914 | ||
915 | /* | |
916 | * Shut-down the DMA. | |
917 | */ | |
918 | if (atmel_use_dma_rx(port)) { | |
919 | int i; | |
920 | ||
921 | for (i = 0; i < 2; i++) { | |
922 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
923 | ||
924 | dma_unmap_single(port->dev, | |
925 | pdc->dma_addr, | |
926 | pdc->dma_size, | |
927 | DMA_FROM_DEVICE); | |
928 | kfree(pdc->buf); | |
929 | } | |
930 | } | |
931 | if (atmel_use_dma_tx(port)) { | |
932 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
933 | ||
934 | dma_unmap_single(port->dev, | |
935 | pdc->dma_addr, | |
936 | pdc->dma_size, | |
937 | DMA_TO_DEVICE); | |
938 | } | |
939 | ||
1e6c9c28 AV |
940 | /* |
941 | * Disable all interrupts, port and break condition. | |
942 | */ | |
7192f92c | 943 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
944 | UART_PUT_IDR(port, -1); |
945 | ||
946 | /* | |
947 | * Free the interrupt | |
948 | */ | |
949 | free_irq(port->irq, port); | |
950 | ||
951 | /* | |
952 | * If there is a specific "close" function (to unregister | |
953 | * control line interrupts) | |
954 | */ | |
71f2e2b8 HS |
955 | if (atmel_close_hook) |
956 | atmel_close_hook(port); | |
1e6c9c28 AV |
957 | } |
958 | ||
9afd561a HS |
959 | /* |
960 | * Flush any TX data submitted for DMA. Called when the TX circular | |
961 | * buffer is reset. | |
962 | */ | |
963 | static void atmel_flush_buffer(struct uart_port *port) | |
964 | { | |
965 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
966 | ||
967 | if (atmel_use_dma_tx(port)) { | |
968 | UART_PUT_TCR(port, 0); | |
969 | atmel_port->pdc_tx.ofs = 0; | |
970 | } | |
971 | } | |
972 | ||
1e6c9c28 AV |
973 | /* |
974 | * Power / Clock management. | |
975 | */ | |
b843aa21 RB |
976 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
977 | unsigned int oldstate) | |
1e6c9c28 | 978 | { |
c811ab8c | 979 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 980 | |
1e6c9c28 | 981 | switch (state) { |
b843aa21 RB |
982 | case 0: |
983 | /* | |
984 | * Enable the peripheral clock for this serial port. | |
985 | * This is called on uart_open() or a resume event. | |
986 | */ | |
987 | clk_enable(atmel_port->clk); | |
f05596db AS |
988 | |
989 | /* re-enable interrupts if we disabled some on suspend */ | |
990 | UART_PUT_IER(port, atmel_port->backup_imr); | |
b843aa21 RB |
991 | break; |
992 | case 3: | |
f05596db AS |
993 | /* Back up the interrupt mask and disable all interrupts */ |
994 | atmel_port->backup_imr = UART_GET_IMR(port); | |
995 | UART_PUT_IDR(port, -1); | |
996 | ||
b843aa21 RB |
997 | /* |
998 | * Disable the peripheral clock for this serial port. | |
999 | * This is called on uart_close() or a suspend event. | |
1000 | */ | |
1001 | clk_disable(atmel_port->clk); | |
1002 | break; | |
1003 | default: | |
1004 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); | |
1e6c9c28 AV |
1005 | } |
1006 | } | |
1007 | ||
1008 | /* | |
1009 | * Change the port parameters | |
1010 | */ | |
b843aa21 RB |
1011 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
1012 | struct ktermios *old) | |
1e6c9c28 AV |
1013 | { |
1014 | unsigned long flags; | |
1015 | unsigned int mode, imr, quot, baud; | |
1016 | ||
03abeac0 | 1017 | /* Get current mode register */ |
b843aa21 RB |
1018 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL |
1019 | | ATMEL_US_NBSTOP | ATMEL_US_PAR); | |
03abeac0 | 1020 | |
b843aa21 | 1021 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
1022 | quot = uart_get_divisor(port, baud); |
1023 | ||
b843aa21 | 1024 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
1025 | quot /= 8; |
1026 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
1027 | } | |
1e6c9c28 AV |
1028 | |
1029 | /* byte size */ | |
1030 | switch (termios->c_cflag & CSIZE) { | |
1031 | case CS5: | |
7192f92c | 1032 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
1033 | break; |
1034 | case CS6: | |
7192f92c | 1035 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
1036 | break; |
1037 | case CS7: | |
7192f92c | 1038 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
1039 | break; |
1040 | default: | |
7192f92c | 1041 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
1042 | break; |
1043 | } | |
1044 | ||
1045 | /* stop bits */ | |
1046 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 1047 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
1048 | |
1049 | /* parity */ | |
1050 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
1051 | /* Mark or Space parity */ |
1052 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 1053 | if (termios->c_cflag & PARODD) |
7192f92c | 1054 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 1055 | else |
7192f92c | 1056 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 1057 | } else if (termios->c_cflag & PARODD) |
7192f92c | 1058 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 1059 | else |
7192f92c | 1060 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 1061 | } else |
7192f92c | 1062 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
1063 | |
1064 | spin_lock_irqsave(&port->lock, flags); | |
1065 | ||
7192f92c | 1066 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 1067 | if (termios->c_iflag & INPCK) |
7192f92c | 1068 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1069 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 1070 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 1071 | |
a6670615 CC |
1072 | if (atmel_use_dma_rx(port)) |
1073 | /* need to enable error interrupts */ | |
1074 | UART_PUT_IER(port, port->read_status_mask); | |
1075 | ||
1e6c9c28 AV |
1076 | /* |
1077 | * Characters to ignore | |
1078 | */ | |
1079 | port->ignore_status_mask = 0; | |
1080 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1081 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1082 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 1083 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
1084 | /* |
1085 | * If we're ignoring parity and break indicators, | |
1086 | * ignore overruns too (for real raw support). | |
1087 | */ | |
1088 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1089 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 1090 | } |
b843aa21 | 1091 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
1092 | |
1093 | /* update the per-port timeout */ | |
1094 | uart_update_timeout(port, termios->c_cflag, baud); | |
1095 | ||
b843aa21 RB |
1096 | /* save/disable interrupts and drain transmitter */ |
1097 | imr = UART_GET_IMR(port); | |
1098 | UART_PUT_IDR(port, -1); | |
1099 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
829dd811 | 1100 | cpu_relax(); |
1e6c9c28 AV |
1101 | |
1102 | /* disable receiver and transmitter */ | |
7192f92c | 1103 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 AV |
1104 | |
1105 | /* set the parity, stop bits and data size */ | |
1106 | UART_PUT_MR(port, mode); | |
1107 | ||
1108 | /* set the baud rate */ | |
1109 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
1110 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1111 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1112 | |
1113 | /* restore interrupts */ | |
1114 | UART_PUT_IER(port, imr); | |
1115 | ||
1116 | /* CTS flow-control and modem-status interrupts */ | |
1117 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1118 | port->ops->enable_ms(port); | |
1119 | ||
1120 | spin_unlock_irqrestore(&port->lock, flags); | |
1121 | } | |
1122 | ||
1123 | /* | |
1124 | * Return string describing the specified port | |
1125 | */ | |
7192f92c | 1126 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 1127 | { |
9ab4f88b | 1128 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
1129 | } |
1130 | ||
1131 | /* | |
1132 | * Release the memory region(s) being used by 'port'. | |
1133 | */ | |
7192f92c | 1134 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 1135 | { |
afefc415 AV |
1136 | struct platform_device *pdev = to_platform_device(port->dev); |
1137 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1138 | ||
1139 | release_mem_region(port->mapbase, size); | |
1140 | ||
1141 | if (port->flags & UPF_IOREMAP) { | |
1142 | iounmap(port->membase); | |
1143 | port->membase = NULL; | |
1144 | } | |
1e6c9c28 AV |
1145 | } |
1146 | ||
1147 | /* | |
1148 | * Request the memory region(s) being used by 'port'. | |
1149 | */ | |
7192f92c | 1150 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 1151 | { |
afefc415 AV |
1152 | struct platform_device *pdev = to_platform_device(port->dev); |
1153 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1154 | ||
7192f92c | 1155 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
1156 | return -EBUSY; |
1157 | ||
1158 | if (port->flags & UPF_IOREMAP) { | |
1159 | port->membase = ioremap(port->mapbase, size); | |
1160 | if (port->membase == NULL) { | |
1161 | release_mem_region(port->mapbase, size); | |
1162 | return -ENOMEM; | |
1163 | } | |
1164 | } | |
1e6c9c28 | 1165 | |
afefc415 | 1166 | return 0; |
1e6c9c28 AV |
1167 | } |
1168 | ||
1169 | /* | |
1170 | * Configure/autoconfigure the port. | |
1171 | */ | |
7192f92c | 1172 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
1173 | { |
1174 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 1175 | port->type = PORT_ATMEL; |
7192f92c | 1176 | atmel_request_port(port); |
1e6c9c28 AV |
1177 | } |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * Verify the new serial_struct (for TIOCSSERIAL). | |
1182 | */ | |
7192f92c | 1183 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
1184 | { |
1185 | int ret = 0; | |
9ab4f88b | 1186 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
1187 | ret = -EINVAL; |
1188 | if (port->irq != ser->irq) | |
1189 | ret = -EINVAL; | |
1190 | if (ser->io_type != SERIAL_IO_MEM) | |
1191 | ret = -EINVAL; | |
1192 | if (port->uartclk / 16 != ser->baud_base) | |
1193 | ret = -EINVAL; | |
1194 | if ((void *)port->mapbase != ser->iomem_base) | |
1195 | ret = -EINVAL; | |
1196 | if (port->iobase != ser->port) | |
1197 | ret = -EINVAL; | |
1198 | if (ser->hub6 != 0) | |
1199 | ret = -EINVAL; | |
1200 | return ret; | |
1201 | } | |
1202 | ||
7192f92c HS |
1203 | static struct uart_ops atmel_pops = { |
1204 | .tx_empty = atmel_tx_empty, | |
1205 | .set_mctrl = atmel_set_mctrl, | |
1206 | .get_mctrl = atmel_get_mctrl, | |
1207 | .stop_tx = atmel_stop_tx, | |
1208 | .start_tx = atmel_start_tx, | |
1209 | .stop_rx = atmel_stop_rx, | |
1210 | .enable_ms = atmel_enable_ms, | |
1211 | .break_ctl = atmel_break_ctl, | |
1212 | .startup = atmel_startup, | |
1213 | .shutdown = atmel_shutdown, | |
9afd561a | 1214 | .flush_buffer = atmel_flush_buffer, |
7192f92c HS |
1215 | .set_termios = atmel_set_termios, |
1216 | .type = atmel_type, | |
1217 | .release_port = atmel_release_port, | |
1218 | .request_port = atmel_request_port, | |
1219 | .config_port = atmel_config_port, | |
1220 | .verify_port = atmel_verify_port, | |
1221 | .pm = atmel_serial_pm, | |
1e6c9c28 AV |
1222 | }; |
1223 | ||
afefc415 AV |
1224 | /* |
1225 | * Configure the port from the platform device resource info. | |
1226 | */ | |
b843aa21 RB |
1227 | static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, |
1228 | struct platform_device *pdev) | |
1e6c9c28 | 1229 | { |
7192f92c | 1230 | struct uart_port *port = &atmel_port->uart; |
73e2798b | 1231 | struct atmel_uart_data *data = pdev->dev.platform_data; |
afefc415 AV |
1232 | |
1233 | port->iotype = UPIO_MEM; | |
a14d5273 | 1234 | port->flags = UPF_BOOT_AUTOCONF; |
7192f92c | 1235 | port->ops = &atmel_pops; |
a14d5273 | 1236 | port->fifosize = 1; |
afefc415 AV |
1237 | port->line = pdev->id; |
1238 | port->dev = &pdev->dev; | |
1239 | ||
1240 | port->mapbase = pdev->resource[0].start; | |
1241 | port->irq = pdev->resource[1].start; | |
1242 | ||
1ecc26bd RB |
1243 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
1244 | (unsigned long)port); | |
1245 | ||
1246 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | |
1247 | ||
75d35213 HS |
1248 | if (data->regs) |
1249 | /* Already mapped by setup code */ | |
1250 | port->membase = data->regs; | |
afefc415 AV |
1251 | else { |
1252 | port->flags |= UPF_IOREMAP; | |
1253 | port->membase = NULL; | |
1254 | } | |
1e6c9c28 | 1255 | |
b843aa21 RB |
1256 | /* for console, the clock could already be configured */ |
1257 | if (!atmel_port->clk) { | |
7192f92c HS |
1258 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
1259 | clk_enable(atmel_port->clk); | |
1260 | port->uartclk = clk_get_rate(atmel_port->clk); | |
afefc415 | 1261 | } |
a6670615 CC |
1262 | |
1263 | atmel_port->use_dma_rx = data->use_dma_rx; | |
1264 | atmel_port->use_dma_tx = data->use_dma_tx; | |
1265 | if (atmel_use_dma_tx(port)) | |
1266 | port->fifosize = PDC_BUFFER_SIZE; | |
1e6c9c28 AV |
1267 | } |
1268 | ||
afefc415 AV |
1269 | /* |
1270 | * Register board-specific modem-control line handlers. | |
1271 | */ | |
71f2e2b8 | 1272 | void __init atmel_register_uart_fns(struct atmel_port_fns *fns) |
1e6c9c28 AV |
1273 | { |
1274 | if (fns->enable_ms) | |
7192f92c | 1275 | atmel_pops.enable_ms = fns->enable_ms; |
1e6c9c28 | 1276 | if (fns->get_mctrl) |
7192f92c | 1277 | atmel_pops.get_mctrl = fns->get_mctrl; |
1e6c9c28 | 1278 | if (fns->set_mctrl) |
7192f92c | 1279 | atmel_pops.set_mctrl = fns->set_mctrl; |
71f2e2b8 HS |
1280 | atmel_open_hook = fns->open; |
1281 | atmel_close_hook = fns->close; | |
7192f92c HS |
1282 | atmel_pops.pm = fns->pm; |
1283 | atmel_pops.set_wake = fns->set_wake; | |
1e6c9c28 AV |
1284 | } |
1285 | ||
749c4e60 | 1286 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 1287 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 1288 | { |
7192f92c | 1289 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
829dd811 | 1290 | cpu_relax(); |
d358788f RK |
1291 | UART_PUT_CHAR(port, ch); |
1292 | } | |
1e6c9c28 AV |
1293 | |
1294 | /* | |
1295 | * Interrupts are disabled on entering | |
1296 | */ | |
7192f92c | 1297 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 1298 | { |
7192f92c | 1299 | struct uart_port *port = &atmel_ports[co->index].uart; |
d358788f | 1300 | unsigned int status, imr; |
39d4c922 | 1301 | unsigned int pdc_tx; |
1e6c9c28 AV |
1302 | |
1303 | /* | |
b843aa21 | 1304 | * First, save IMR and then disable interrupts |
1e6c9c28 | 1305 | */ |
b843aa21 | 1306 | imr = UART_GET_IMR(port); |
7192f92c | 1307 | UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY); |
1e6c9c28 | 1308 | |
39d4c922 MP |
1309 | /* Store PDC transmit status and disable it */ |
1310 | pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; | |
1311 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
1312 | ||
7192f92c | 1313 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
1314 | |
1315 | /* | |
b843aa21 RB |
1316 | * Finally, wait for transmitter to become empty |
1317 | * and restore IMR | |
1e6c9c28 AV |
1318 | */ |
1319 | do { | |
1320 | status = UART_GET_CSR(port); | |
7192f92c | 1321 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
1322 | |
1323 | /* Restore PDC transmit status */ | |
1324 | if (pdc_tx) | |
1325 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
1326 | ||
b843aa21 RB |
1327 | /* set interrupts back the way they were */ |
1328 | UART_PUT_IER(port, imr); | |
1e6c9c28 AV |
1329 | } |
1330 | ||
1331 | /* | |
b843aa21 RB |
1332 | * If the port was already initialised (eg, by a boot loader), |
1333 | * try to determine the current setup. | |
1e6c9c28 | 1334 | */ |
b843aa21 RB |
1335 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
1336 | int *parity, int *bits) | |
1e6c9c28 AV |
1337 | { |
1338 | unsigned int mr, quot; | |
1339 | ||
1c0fd82f HS |
1340 | /* |
1341 | * If the baud rate generator isn't running, the port wasn't | |
1342 | * initialized by the boot loader. | |
1343 | */ | |
9c81c5c9 | 1344 | quot = UART_GET_BRGR(port) & ATMEL_US_CD; |
1c0fd82f HS |
1345 | if (!quot) |
1346 | return; | |
1e6c9c28 | 1347 | |
7192f92c HS |
1348 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
1349 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
1350 | *bits = 8; |
1351 | else | |
1352 | *bits = 7; | |
1353 | ||
7192f92c HS |
1354 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
1355 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 1356 | *parity = 'e'; |
7192f92c | 1357 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
1358 | *parity = 'o'; |
1359 | ||
4d5e392c HS |
1360 | /* |
1361 | * The serial core only rounds down when matching this to a | |
1362 | * supported baud rate. Make sure we don't end up slightly | |
1363 | * lower than one of those, as it would make us fall through | |
1364 | * to a much lower baud rate than we really want. | |
1365 | */ | |
4d5e392c | 1366 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
1367 | } |
1368 | ||
7192f92c | 1369 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 1370 | { |
7192f92c | 1371 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
1372 | int baud = 115200; |
1373 | int bits = 8; | |
1374 | int parity = 'n'; | |
1375 | int flow = 'n'; | |
1376 | ||
b843aa21 RB |
1377 | if (port->membase == NULL) { |
1378 | /* Port not initialized yet - delay setup */ | |
afefc415 | 1379 | return -ENODEV; |
b843aa21 | 1380 | } |
1e6c9c28 | 1381 | |
b843aa21 | 1382 | UART_PUT_IDR(port, -1); |
7192f92c HS |
1383 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1384 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1385 | |
1386 | if (options) | |
1387 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1388 | else | |
7192f92c | 1389 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
1390 | |
1391 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1392 | } | |
1393 | ||
7192f92c | 1394 | static struct uart_driver atmel_uart; |
1e6c9c28 | 1395 | |
7192f92c HS |
1396 | static struct console atmel_console = { |
1397 | .name = ATMEL_DEVICENAME, | |
1398 | .write = atmel_console_write, | |
1e6c9c28 | 1399 | .device = uart_console_device, |
7192f92c | 1400 | .setup = atmel_console_setup, |
1e6c9c28 AV |
1401 | .flags = CON_PRINTBUFFER, |
1402 | .index = -1, | |
7192f92c | 1403 | .data = &atmel_uart, |
1e6c9c28 AV |
1404 | }; |
1405 | ||
7192f92c | 1406 | #define ATMEL_CONSOLE_DEVICE &atmel_console |
1e6c9c28 | 1407 | |
afefc415 AV |
1408 | /* |
1409 | * Early console initialization (before VM subsystem initialized). | |
1410 | */ | |
7192f92c | 1411 | static int __init atmel_console_init(void) |
1e6c9c28 | 1412 | { |
73e2798b | 1413 | if (atmel_default_console_device) { |
b843aa21 RB |
1414 | add_preferred_console(ATMEL_DEVICENAME, |
1415 | atmel_default_console_device->id, NULL); | |
1416 | atmel_init_port(&atmel_ports[atmel_default_console_device->id], | |
1417 | atmel_default_console_device); | |
7192f92c | 1418 | register_console(&atmel_console); |
afefc415 | 1419 | } |
1e6c9c28 | 1420 | |
1e6c9c28 AV |
1421 | return 0; |
1422 | } | |
b843aa21 | 1423 | |
7192f92c | 1424 | console_initcall(atmel_console_init); |
1e6c9c28 | 1425 | |
afefc415 AV |
1426 | /* |
1427 | * Late console initialization. | |
1428 | */ | |
7192f92c | 1429 | static int __init atmel_late_console_init(void) |
afefc415 | 1430 | { |
b843aa21 RB |
1431 | if (atmel_default_console_device |
1432 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 1433 | register_console(&atmel_console); |
afefc415 AV |
1434 | |
1435 | return 0; | |
1436 | } | |
b843aa21 | 1437 | |
7192f92c | 1438 | core_initcall(atmel_late_console_init); |
afefc415 | 1439 | |
dfa7f343 HS |
1440 | static inline bool atmel_is_console_port(struct uart_port *port) |
1441 | { | |
1442 | return port->cons && port->cons->index == port->line; | |
1443 | } | |
1444 | ||
1e6c9c28 | 1445 | #else |
7192f92c | 1446 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
1447 | |
1448 | static inline bool atmel_is_console_port(struct uart_port *port) | |
1449 | { | |
1450 | return false; | |
1451 | } | |
1e6c9c28 AV |
1452 | #endif |
1453 | ||
7192f92c | 1454 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
1455 | .owner = THIS_MODULE, |
1456 | .driver_name = "atmel_serial", | |
1457 | .dev_name = ATMEL_DEVICENAME, | |
1458 | .major = SERIAL_ATMEL_MAJOR, | |
1459 | .minor = MINOR_START, | |
1460 | .nr = ATMEL_MAX_UART, | |
1461 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
1462 | }; |
1463 | ||
afefc415 | 1464 | #ifdef CONFIG_PM |
f826caa4 HS |
1465 | static bool atmel_serial_clk_will_stop(void) |
1466 | { | |
1467 | #ifdef CONFIG_ARCH_AT91 | |
1468 | return at91_suspend_entering_slow_clock(); | |
1469 | #else | |
1470 | return false; | |
1471 | #endif | |
1472 | } | |
1473 | ||
b843aa21 RB |
1474 | static int atmel_serial_suspend(struct platform_device *pdev, |
1475 | pm_message_t state) | |
1e6c9c28 | 1476 | { |
afefc415 | 1477 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 1478 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1479 | |
e1c609ef HS |
1480 | if (atmel_is_console_port(port) && console_suspend_enabled) { |
1481 | /* Drain the TX shifter */ | |
1482 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
1483 | cpu_relax(); | |
1484 | } | |
1485 | ||
f05596db AS |
1486 | /* we can not wake up if we're running on slow clock */ |
1487 | atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); | |
1488 | if (atmel_serial_clk_will_stop()) | |
1489 | device_set_wakeup_enable(&pdev->dev, 0); | |
1490 | ||
1491 | uart_suspend_port(&atmel_uart, port); | |
1e6c9c28 | 1492 | |
afefc415 AV |
1493 | return 0; |
1494 | } | |
1e6c9c28 | 1495 | |
7192f92c | 1496 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
1497 | { |
1498 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1499 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1500 | |
f05596db AS |
1501 | uart_resume_port(&atmel_uart, port); |
1502 | device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); | |
1e6c9c28 AV |
1503 | |
1504 | return 0; | |
1505 | } | |
afefc415 | 1506 | #else |
7192f92c HS |
1507 | #define atmel_serial_suspend NULL |
1508 | #define atmel_serial_resume NULL | |
afefc415 | 1509 | #endif |
1e6c9c28 | 1510 | |
7192f92c | 1511 | static int __devinit atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 1512 | { |
7192f92c | 1513 | struct atmel_uart_port *port; |
1ecc26bd | 1514 | void *data; |
afefc415 | 1515 | int ret; |
1e6c9c28 | 1516 | |
1ecc26bd RB |
1517 | BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE)); |
1518 | ||
7192f92c | 1519 | port = &atmel_ports[pdev->id]; |
f05596db AS |
1520 | port->backup_imr = 0; |
1521 | ||
7192f92c | 1522 | atmel_init_port(port, pdev); |
1e6c9c28 | 1523 | |
a6670615 CC |
1524 | if (!atmel_use_dma_rx(&port->uart)) { |
1525 | ret = -ENOMEM; | |
6433471d HS |
1526 | data = kmalloc(sizeof(struct atmel_uart_char) |
1527 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
1528 | if (!data) |
1529 | goto err_alloc_ring; | |
1530 | port->rx_ring.buf = data; | |
1531 | } | |
1ecc26bd | 1532 | |
7192f92c | 1533 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
dfa7f343 HS |
1534 | if (ret) |
1535 | goto err_add_port; | |
1536 | ||
1537 | device_init_wakeup(&pdev->dev, 1); | |
1538 | platform_set_drvdata(pdev, port); | |
1539 | ||
1540 | return 0; | |
1541 | ||
1542 | err_add_port: | |
1ecc26bd RB |
1543 | kfree(port->rx_ring.buf); |
1544 | port->rx_ring.buf = NULL; | |
1545 | err_alloc_ring: | |
dfa7f343 HS |
1546 | if (!atmel_is_console_port(&port->uart)) { |
1547 | clk_disable(port->clk); | |
1548 | clk_put(port->clk); | |
1549 | port->clk = NULL; | |
afefc415 AV |
1550 | } |
1551 | ||
1552 | return ret; | |
1553 | } | |
1554 | ||
7192f92c | 1555 | static int __devexit atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
1556 | { |
1557 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1558 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 AV |
1559 | int ret = 0; |
1560 | ||
afefc415 AV |
1561 | device_init_wakeup(&pdev->dev, 0); |
1562 | platform_set_drvdata(pdev, NULL); | |
1563 | ||
dfa7f343 HS |
1564 | ret = uart_remove_one_port(&atmel_uart, port); |
1565 | ||
1ecc26bd RB |
1566 | tasklet_kill(&atmel_port->tasklet); |
1567 | kfree(atmel_port->rx_ring.buf); | |
1568 | ||
dfa7f343 HS |
1569 | /* "port" is allocated statically, so we shouldn't free it */ |
1570 | ||
1571 | clk_disable(atmel_port->clk); | |
1572 | clk_put(atmel_port->clk); | |
afefc415 AV |
1573 | |
1574 | return ret; | |
1575 | } | |
1576 | ||
7192f92c HS |
1577 | static struct platform_driver atmel_serial_driver = { |
1578 | .probe = atmel_serial_probe, | |
1579 | .remove = __devexit_p(atmel_serial_remove), | |
1580 | .suspend = atmel_serial_suspend, | |
1581 | .resume = atmel_serial_resume, | |
afefc415 | 1582 | .driver = { |
1e8ea802 | 1583 | .name = "atmel_usart", |
afefc415 AV |
1584 | .owner = THIS_MODULE, |
1585 | }, | |
1586 | }; | |
1587 | ||
7192f92c | 1588 | static int __init atmel_serial_init(void) |
afefc415 AV |
1589 | { |
1590 | int ret; | |
1591 | ||
7192f92c | 1592 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
1593 | if (ret) |
1594 | return ret; | |
1595 | ||
7192f92c | 1596 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 1597 | if (ret) |
7192f92c | 1598 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
1599 | |
1600 | return ret; | |
1601 | } | |
1602 | ||
7192f92c | 1603 | static void __exit atmel_serial_exit(void) |
afefc415 | 1604 | { |
7192f92c HS |
1605 | platform_driver_unregister(&atmel_serial_driver); |
1606 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
1607 | } |
1608 | ||
7192f92c HS |
1609 | module_init(atmel_serial_init); |
1610 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
1611 | |
1612 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 1613 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 1614 | MODULE_LICENSE("GPL"); |
e169c139 | 1615 | MODULE_ALIAS("platform:atmel_usart"); |