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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[deliverable/linux.git] / drivers / serial / bfin_5xx.c
CommitLineData
194de561 1/*
1ba7a3ee 2 * Blackfin On-Chip Serial Driver
194de561 3 *
d273e201 4 * Copyright 2006-2008 Analog Devices Inc.
194de561 5 *
1ba7a3ee 6 * Enter bugs at http://blackfin.uclinux.org/
194de561 7 *
1ba7a3ee 8 * Licensed under the GPL-2 or later.
194de561
BW		 9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
20#include <linux/platform_device.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24
52e15f0e
SZ		 25#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
26 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
474f1a66
SZ		 27#include <linux/kgdb.h>
28#include <asm/irq_regs.h>
29#endif
30
194de561 31#include <asm/gpio.h>
639f6571 32#include <mach/bfin_serial_5xx.h>
194de561
BW		 33
34#ifdef CONFIG_SERIAL_BFIN_DMA
35#include <linux/dma-mapping.h>
36#include <asm/io.h>
37#include <asm/irq.h>
38#include <asm/cacheflush.h>
39#endif
40
607c268e
MF		 41#ifdef CONFIG_SERIAL_BFIN_MODULE
42# undef CONFIG_EARLY_PRINTK
43#endif
44
194de561
BW		 45/* UART name and device definitions */
46#define BFIN_SERIAL_NAME "ttyBF"
47#define BFIN_SERIAL_MAJOR 204
48#define BFIN_SERIAL_MINOR 64
49
c9607ecc
MF		 50static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
51static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
52
52e15f0e
SZ		 53#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
54 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
55
56# ifndef CONFIG_SERIAL_BFIN_PIO
57# error KGDB only support UART in PIO mode.
58# endif
59
60static int kgdboc_port_line;
61static int kgdboc_break_enabled;
62#endif
194de561
BW		 63/*
64 * Setup for console. Argument comes from the menuconfig
65 */
66#define DMA_RX_XCOUNT 512
67#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
68
0aef4564 69#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
194de561
BW		 70
71#ifdef CONFIG_SERIAL_BFIN_DMA
72static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
73#else
194de561 74static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
BW		 75#endif
76
80d5c474
GY		 77static void bfin_serial_reset_irda(struct uart_port *port);
78
d307d36a
SZ		 79#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
80 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
81static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
82{
83 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
84 if (uart->cts_pin < 0)
85 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
86
87 /* CTS PIN is negative assertive. */
88 if (UART_GET_CTS(uart))
89 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
90 else
91 return TIOCM_DSR | TIOCM_CAR;
92}
93
94static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
95{
96 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
97 if (uart->rts_pin < 0)
98 return;
99
100 /* RTS PIN is negative assertive. */
101 if (mctrl & TIOCM_RTS)
102 UART_ENABLE_RTS(uart);
103 else
104 UART_DISABLE_RTS(uart);
105}
106
107/*
108 * Handle any change of modem status signal.
109 */
110static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
111{
112 struct bfin_serial_port *uart = dev_id;
113 unsigned int status;
114
115 status = bfin_serial_get_mctrl(&uart->port);
116 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
117#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
118 uart->scts = 1;
119 UART_CLEAR_SCTS(uart);
120 UART_CLEAR_IER(uart, EDSSI);
121#endif
122
123 return IRQ_HANDLED;
124}
125#else
126static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
127{
128 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
129}
130
131static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
132{
133}
134#endif
135
194de561
BW		 136/*
137 * interrupts are disabled on entry
138 */
139static void bfin_serial_stop_tx(struct uart_port *port)
140{
141 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
68a784cb 142#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857 143 struct circ_buf *xmit = &uart->port.info->xmit;
68a784cb 144#endif
194de561 145
f4d640c9 146 while (!(UART_GET_LSR(uart) & TEMT))
0711d857 147 cpu_relax();
f4d640c9 148
194de561
BW		 149#ifdef CONFIG_SERIAL_BFIN_DMA
150 disable_dma(uart->tx_dma_channel);
0711d857
SZ		 151 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
152 uart->port.icount.tx += uart->tx_count;
153 uart->tx_count = 0;
154 uart->tx_done = 1;
f4d640c9
RH		 155#else
156#ifdef CONFIG_BF54x
f4d640c9
RH		 157 /* Clear TFI bit */
158 UART_PUT_LSR(uart, TFI);
194de561 159#endif
89bf6dc5 160 UART_CLEAR_IER(uart, ETBEI);
f4d640c9 161#endif
194de561
BW		 162}
163
164/*
165 * port is locked and interrupts are disabled
166 */
167static void bfin_serial_start_tx(struct uart_port *port)
168{
169 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
80d5c474
GY		 170 struct tty_struct *tty = uart->port.info->port.tty;
171
d307d36a 172#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
daba0280 173 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
d307d36a
SZ		 174 uart->scts = 0;
175 uart_handle_cts_change(&uart->port, uart->scts);
176 }
177#endif
178
80d5c474
GY		 179 /*
180 * To avoid losting RX interrupt, we reset IR function
181 * before sending data.
182 */
183 if (tty->termios->c_line == N_IRDA)
184 bfin_serial_reset_irda(port);
194de561
BW		 185
186#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857
SZ		 187 if (uart->tx_done)
188 bfin_serial_dma_tx_chars(uart);
f4d640c9 189#else
f4d640c9 190 UART_SET_IER(uart, ETBEI);
a359cca7 191 bfin_serial_tx_chars(uart);
f4d640c9 192#endif
194de561
BW		 193}
194
195/*
196 * Interrupts are enabled
197 */
198static void bfin_serial_stop_rx(struct uart_port *port)
199{
200 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
52e15f0e 201
f4d640c9 202 UART_CLEAR_IER(uart, ERBFI);
194de561
BW		 203}
204
205/*
206 * Set the modem control timer to fire immediately.
207 */
208static void bfin_serial_enable_ms(struct uart_port *port)
209{
210}
211
474f1a66 212
50e2e15a 213#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
8851c71e
MF		 214# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
215# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
216#else
217# define UART_GET_ANOMALY_THRESHOLD(uart) 0
218# define UART_SET_ANOMALY_THRESHOLD(uart, v)
219#endif
220
194de561 221#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
BW		 222static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
223{
52e15f0e 224 struct tty_struct *tty = NULL;
194de561 225 unsigned int status, ch, flg;
8851c71e 226 static struct timeval anomaly_start = { .tv_sec = 0 };
194de561 227
759eb040 228 status = UART_GET_LSR(uart);
0bcfd70e
MF		 229 UART_CLEAR_LSR(uart);
230
231 ch = UART_GET_CHAR(uart);
194de561
BW		 232 uart->port.icount.rx++;
233
52e15f0e
SZ		 234#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
235 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
236 if (kgdb_connected && kgdboc_port_line == uart->port.line)
237 if (ch == 0x3) {/* Ctrl + C */
238 kgdb_breakpoint();
474f1a66 239 return;
474f1a66 240 }
52e15f0e 241
df04baf1 242 if (!uart->port.info || !uart->port.info->port.tty)
52e15f0e 243 return;
474f1a66 244#endif
df04baf1 245 tty = uart->port.info->port.tty;
bbf275f0 246
50e2e15a 247 if (ANOMALY_05000363) {
8851c71e
MF		 248 /* The BF533 (and BF561) family of processors have a nice anomaly
249 * where they continuously generate characters for a "single" break.
bbf275f0 250 * We have to basically ignore this flood until the "next" valid
8851c71e
MF		 251 * character comes across. Due to the nature of the flood, it is
252 * not possible to reliably catch bytes that are sent too quickly
253 * after this break. So application code talking to the Blackfin
254 * which sends a break signal must allow at least 1.5 character
255 * times after the end of the break for things to stabilize. This
256 * timeout was picked as it must absolutely be larger than 1
257 * character time +/- some percent. So 1.5 sounds good. All other
258 * Blackfin families operate properly. Woo.
bbf275f0 259 */
8851c71e
MF		 260 if (anomaly_start.tv_sec) {
261 struct timeval curr;
262 suseconds_t usecs;
263
264 if ((~ch & (~ch + 1)) & 0xff)
265 goto known_good_char;
266
267 do_gettimeofday(&curr);
268 if (curr.tv_sec - anomaly_start.tv_sec > 1)
269 goto known_good_char;
270
271 usecs = 0;
272 if (curr.tv_sec != anomaly_start.tv_sec)
273 usecs += USEC_PER_SEC;
274 usecs += curr.tv_usec - anomaly_start.tv_usec;
275
276 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
277 goto known_good_char;
278
279 if (ch)
280 anomaly_start.tv_sec = 0;
281 else
282 anomaly_start = curr;
283
284 return;
285
286 known_good_char:
e482a237 287 status &= ~BI;
8851c71e 288 anomaly_start.tv_sec = 0;
bbf275f0 289 }
194de561 290 }
194de561
BW		 291
292 if (status & BI) {
50e2e15a 293 if (ANOMALY_05000363)
8851c71e
MF		 294 if (bfin_revid() < 5)
295 do_gettimeofday(&anomaly_start);
194de561
BW		 296 uart->port.icount.brk++;
297 if (uart_handle_break(&uart->port))
298 goto ignore_char;
9808901b 299 status &= ~(PE | FE);
2ac5ee47
MF		 300 }
301 if (status & PE)
194de561 302 uart->port.icount.parity++;
2ac5ee47 303 if (status & OE)
194de561 304 uart->port.icount.overrun++;
2ac5ee47 305 if (status & FE)
194de561 306 uart->port.icount.frame++;
2ac5ee47
MF		 307
308 status &= uart->port.read_status_mask;
309
310 if (status & BI)
311 flg = TTY_BREAK;
312 else if (status & PE)
313 flg = TTY_PARITY;
314 else if (status & FE)
315 flg = TTY_FRAME;
316 else
194de561
BW		 317 flg = TTY_NORMAL;
318
319 if (uart_handle_sysrq_char(&uart->port, ch))
320 goto ignore_char;
194de561 321
2ac5ee47
MF		 322 uart_insert_char(&uart->port, status, OE, ch, flg);
323
324 ignore_char:
325 tty_flip_buffer_push(tty);
194de561
BW		 326}
327
328static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
329{
330 struct circ_buf *xmit = &uart->port.info->xmit;
331
194de561 332 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
5ffdeea2
SZ		 333#ifdef CONFIG_BF54x
334 /* Clear TFI bit */
335 UART_PUT_LSR(uart, TFI);
336#endif
0efa4f2c
SZ		 337 /* Anomaly notes:
338 * 05000215 - we always clear ETBEI within last UART TX
339 * interrupt to end a string. It is always set
340 * when start a new tx.
341 */
5ffdeea2 342 UART_CLEAR_IER(uart, ETBEI);
194de561
BW		 343 return;
344 }
345
f30ac0ce
SZ		 346 if (uart->port.x_char) {
347 UART_PUT_CHAR(uart, uart->port.x_char);
348 uart->port.icount.tx++;
349 uart->port.x_char = 0;
350 }
351
759eb040
SZ		 352 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
353 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
354 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
355 uart->port.icount.tx++;
356 SSYNC();
357 }
194de561
BW		 358
359 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
360 uart_write_wakeup(&uart->port);
194de561
BW		 361}
362
5c4e472b
AL		 363static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
364{
365 struct bfin_serial_port *uart = dev_id;
366
f4d640c9 367 spin_lock(&uart->port.lock);
0bcfd70e 368 while (UART_GET_LSR(uart) & DR)
f4d640c9 369 bfin_serial_rx_chars(uart);
f4d640c9 370 spin_unlock(&uart->port.lock);
759eb040 371
5c4e472b
AL		 372 return IRQ_HANDLED;
373}
374
375static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW		 376{
377 struct bfin_serial_port *uart = dev_id;
194de561 378
d307d36a 379#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
daba0280 380 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
d307d36a
SZ		 381 uart->scts = 0;
382 uart_handle_cts_change(&uart->port, uart->scts);
383 }
384#endif
f4d640c9 385 spin_lock(&uart->port.lock);
0bcfd70e 386 if (UART_GET_LSR(uart) & THRE)
f4d640c9 387 bfin_serial_tx_chars(uart);
f4d640c9 388 spin_unlock(&uart->port.lock);
759eb040 389
194de561
BW		 390 return IRQ_HANDLED;
391}
4cb4f22b 392#endif
194de561 393
194de561
BW		 394#ifdef CONFIG_SERIAL_BFIN_DMA
395static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
396{
397 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 398
194de561
BW		 399 uart->tx_done = 0;
400
1b73351c 401 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
0711d857 402 uart->tx_count = 0;
1b73351c
SZ		 403 uart->tx_done = 1;
404 return;
405 }
406
194de561
BW		 407 if (uart->port.x_char) {
408 UART_PUT_CHAR(uart, uart->port.x_char);
409 uart->port.icount.tx++;
410 uart->port.x_char = 0;
194de561 411 }
1b73351c 412
194de561
BW		 413 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
414 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
415 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
416 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
417 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
418 set_dma_config(uart->tx_dma_channel,
419 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
420 INTR_ON_BUF,
421 DIMENSION_LINEAR,
2047e40d
MH		 422 DATA_SIZE_8,
423 DMA_SYNC_RESTART));
194de561
BW		 424 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
425 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
426 set_dma_x_modify(uart->tx_dma_channel, 1);
f9d36da9 427 SSYNC();
194de561 428 enable_dma(uart->tx_dma_channel);
99ee7b5f 429
f4d640c9 430 UART_SET_IER(uart, ETBEI);
194de561
BW		 431}
432
2ac5ee47 433static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561 434{
a88487c7 435 struct tty_struct *tty = uart->port.info->port.tty;
194de561
BW		 436 int i, flg, status;
437
438 status = UART_GET_LSR(uart);
0bcfd70e
MF		 439 UART_CLEAR_LSR(uart);
440
56f5de8f
SZ		 441 uart->port.icount.rx +=
442 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
443 UART_XMIT_SIZE);
194de561
BW		 444
445 if (status & BI) {
446 uart->port.icount.brk++;
447 if (uart_handle_break(&uart->port))
448 goto dma_ignore_char;
9808901b 449 status &= ~(PE | FE);
2ac5ee47
MF		 450 }
451 if (status & PE)
194de561 452 uart->port.icount.parity++;
2ac5ee47 453 if (status & OE)
194de561 454 uart->port.icount.overrun++;
2ac5ee47 455 if (status & FE)
194de561 456 uart->port.icount.frame++;
2ac5ee47
MF		 457
458 status &= uart->port.read_status_mask;
459
460 if (status & BI)
461 flg = TTY_BREAK;
462 else if (status & PE)
463 flg = TTY_PARITY;
464 else if (status & FE)
465 flg = TTY_FRAME;
466 else
194de561
BW		 467 flg = TTY_NORMAL;
468
8c4210e3 469 for (i = uart->rx_dma_buf.tail; ; i++) {
56f5de8f
SZ		 470 if (i >= UART_XMIT_SIZE)
471 i = 0;
8c4210e3
SZ		 472 if (i == uart->rx_dma_buf.head)
473 break;
56f5de8f
SZ		 474 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
475 uart_insert_char(&uart->port, status, OE,
476 uart->rx_dma_buf.buf[i], flg);
194de561 477 }
2ac5ee47
MF		 478
479 dma_ignore_char:
194de561
BW		 480 tty_flip_buffer_push(tty);
481}
482
483void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
484{
59e4e3e6 485 int x_pos, pos;
68a784cb 486
2860b791
SZ		 487 dma_disable_irq(uart->rx_dma_channel);
488 spin_lock_bh(&uart->port.lock);
194de561 489
8516c568
SZ		 490 /* 2D DMA RX buffer ring is used. Because curr_y_count and
491 * curr_x_count can't be read as an atomic operation,
492 * curr_y_count should be read before curr_x_count. When
493 * curr_x_count is read, curr_y_count may already indicate
494 * next buffer line. But, the position calculated here is
495 * still indicate the old line. The wrong position data may
496 * be smaller than current buffer tail, which cause garbages
497 * are received if it is not prohibit.
498 */
56f5de8f
SZ		 499 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
500 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
501 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
35ff6935 502 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
56f5de8f
SZ		 503 uart->rx_dma_nrows = 0;
504 x_pos = DMA_RX_XCOUNT - x_pos;
194de561
BW		 505 if (x_pos == DMA_RX_XCOUNT)
506 x_pos = 0;
507
508 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
8516c568
SZ		 509 /* Ignore receiving data if new position is in the same line of
510 * current buffer tail and small.
511 */
512 if (pos > uart->rx_dma_buf.tail ||
513 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
56f5de8f 514 uart->rx_dma_buf.head = pos;
194de561 515 bfin_serial_dma_rx_chars(uart);
56f5de8f 516 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
194de561 517 }
0aef4564 518
2860b791
SZ		 519 spin_unlock_bh(&uart->port.lock);
520 dma_enable_irq(uart->rx_dma_channel);
68a784cb 521
0a278423 522 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
194de561
BW		 523}
524
525static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
526{
527 struct bfin_serial_port *uart = dev_id;
528 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 529
d307d36a 530#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
daba0280 531 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
d307d36a
SZ		 532 uart->scts = 0;
533 uart_handle_cts_change(&uart->port, uart->scts);
534 }
535#endif
536
194de561
BW		 537 spin_lock(&uart->port.lock);
538 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
194de561 539 disable_dma(uart->tx_dma_channel);
0711d857 540 clear_dma_irqstat(uart->tx_dma_channel);
0efa4f2c
SZ		 541 /* Anomaly notes:
542 * 05000215 - we always clear ETBEI within last UART TX
543 * interrupt to end a string. It is always set
544 * when start a new tx.
545 */
f4d640c9 546 UART_CLEAR_IER(uart, ETBEI);
0711d857
SZ		 547 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
548 uart->port.icount.tx += uart->tx_count;
1b73351c 549
56f5de8f
SZ		 550 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
551 uart_write_wakeup(&uart->port);
552
1b73351c 553 bfin_serial_dma_tx_chars(uart);
194de561
BW		 554 }
555
556 spin_unlock(&uart->port.lock);
557 return IRQ_HANDLED;
558}
559
560static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
561{
562 struct bfin_serial_port *uart = dev_id;
563 unsigned short irqstat;
35ff6935 564 int x_pos, pos;
0711d857 565
194de561
BW		 566 spin_lock(&uart->port.lock);
567 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
568 clear_dma_irqstat(uart->rx_dma_channel);
8516c568
SZ		 569
570 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
35ff6935 571 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
8516c568 572 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
35ff6935 573 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
8516c568
SZ		 574 uart->rx_dma_nrows = 0;
575
576 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
577 if (pos > uart->rx_dma_buf.tail ||
578 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
579 uart->rx_dma_buf.head = pos;
580 bfin_serial_dma_rx_chars(uart);
581 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
582 }
583
194de561 584 spin_unlock(&uart->port.lock);
0aef4564 585
194de561
BW		 586 return IRQ_HANDLED;
587}
588#endif
589
590/*
591 * Return TIOCSER_TEMT when transmitter is not busy.
592 */
593static unsigned int bfin_serial_tx_empty(struct uart_port *port)
594{
595 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
596 unsigned short lsr;
597
598 lsr = UART_GET_LSR(uart);
599 if (lsr & TEMT)
600 return TIOCSER_TEMT;
601 else
602 return 0;
603}
604
194de561
BW		 605static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
606{
cf686762
MF		 607 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
608 u16 lcr = UART_GET_LCR(uart);
609 if (break_state)
610 lcr |= SB;
611 else
612 lcr &= ~SB;
613 UART_PUT_LCR(uart, lcr);
614 SSYNC();
194de561
BW		 615}
616
617static int bfin_serial_startup(struct uart_port *port)
618{
619 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
620
621#ifdef CONFIG_SERIAL_BFIN_DMA
622 dma_addr_t dma_handle;
623
624 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
625 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
626 return -EBUSY;
627 }
628
629 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
630 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
631 free_dma(uart->rx_dma_channel);
632 return -EBUSY;
633 }
634
635 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
636 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
637
638 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
639 uart->rx_dma_buf.head = 0;
640 uart->rx_dma_buf.tail = 0;
641 uart->rx_dma_nrows = 0;
642
643 set_dma_config(uart->rx_dma_channel,
644 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
645 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH		 646 DATA_SIZE_8,
647 DMA_SYNC_RESTART));
194de561
BW		 648 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
649 set_dma_x_modify(uart->rx_dma_channel, 1);
650 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
651 set_dma_y_modify(uart->rx_dma_channel, 1);
652 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
653 enable_dma(uart->rx_dma_channel);
654
655 uart->rx_dma_timer.data = (unsigned long)(uart);
656 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
657 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
658 add_timer(&(uart->rx_dma_timer));
659#else
6f95570e 660# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52e15f0e
SZ		 661 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
662 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
663 kgdboc_break_enabled = 0;
664 else {
665# endif
a359cca7
SZ		 666 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
667 "BFIN_UART_RX", uart)) {
194de561
BW		 668 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
669 return -EBUSY;
670 }
671
672 if (request_irq
5c4e472b 673 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW		 674 "BFIN_UART_TX", uart)) {
675 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
676 free_irq(uart->port.irq, uart);
677 return -EBUSY;
678 }
ab2375f2
SZ		 679
680# ifdef CONFIG_BF54x
681 {
682 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
683
684 switch (uart->port.irq) {
685 case IRQ_UART3_RX:
686 uart_dma_ch_rx = CH_UART3_RX;
687 uart_dma_ch_tx = CH_UART3_TX;
688 break;
689 case IRQ_UART2_RX:
690 uart_dma_ch_rx = CH_UART2_RX;
691 uart_dma_ch_tx = CH_UART2_TX;
692 break;
693 default:
694 uart_dma_ch_rx = uart_dma_ch_tx = 0;
695 break;
696 };
697
698 if (uart_dma_ch_rx &&
699 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
700 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
701 free_irq(uart->port.irq, uart);
702 free_irq(uart->port.irq + 1, uart);
703 return -EBUSY;
704 }
705 if (uart_dma_ch_tx &&
706 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
707 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
708 free_dma(uart_dma_ch_rx);
709 free_irq(uart->port.irq, uart);
710 free_irq(uart->port.irq + 1, uart);
711 return -EBUSY;
712 }
713 }
714# endif
6f95570e 715# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
52e15f0e
SZ		 716 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
717 }
718# endif
6f95570e
SZ		 719#endif
720
721#ifdef CONFIG_SERIAL_BFIN_CTSRTS
722 if (uart->cts_pin >= 0) {
723 if (request_irq(gpio_to_irq(uart->cts_pin),
724 bfin_serial_mctrl_cts_int,
725 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
726 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
727 uart->cts_pin = -1;
728 pr_info("Unable to attach BlackFin UART CTS interrupt.\
729 So, disable it.\n");
730 }
731 }
732 if (uart->rts_pin >= 0) {
733 gpio_request(uart->rts_pin, DRIVER_NAME);
734 gpio_direction_output(uart->rts_pin, 0);
735 }
194de561 736#endif
d307d36a
SZ		 737#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
738 if (request_irq(uart->status_irq,
739 bfin_serial_mctrl_cts_int,
740 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
741 pr_info("Unable to attach BlackFin UART Modem \
742 Status interrupt.\n");
743 }
744
745 if (uart->cts_pin >= 0) {
746 gpio_request(uart->cts_pin, DRIVER_NAME);
747 gpio_direction_output(uart->cts_pin, 1);
748 }
749 if (uart->rts_pin >= 0) {
750 gpio_request(uart->rts_pin, DRIVER_NAME);
751 gpio_direction_output(uart->rts_pin, 0);
752 }
753
754 /* CTS RTS PINs are negative assertive. */
755 UART_PUT_MCR(uart, ACTS);
756 UART_SET_IER(uart, EDSSI);
757#endif
758
f4d640c9 759 UART_SET_IER(uart, ERBFI);
194de561
BW		 760 return 0;
761}
762
763static void bfin_serial_shutdown(struct uart_port *port)
764{
765 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
766
767#ifdef CONFIG_SERIAL_BFIN_DMA
768 disable_dma(uart->tx_dma_channel);
769 free_dma(uart->tx_dma_channel);
770 disable_dma(uart->rx_dma_channel);
771 free_dma(uart->rx_dma_channel);
772 del_timer(&(uart->rx_dma_timer));
75b780bd 773 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 774#else
ab2375f2
SZ		 775#ifdef CONFIG_BF54x
776 switch (uart->port.irq) {
777 case IRQ_UART3_RX:
778 free_dma(CH_UART3_RX);
779 free_dma(CH_UART3_TX);
780 break;
781 case IRQ_UART2_RX:
782 free_dma(CH_UART2_RX);
783 free_dma(CH_UART2_TX);
784 break;
785 default:
786 break;
787 };
474f1a66 788#endif
194de561
BW		 789 free_irq(uart->port.irq, uart);
790 free_irq(uart->port.irq+1, uart);
791#endif
6f95570e 792
d307d36a 793#ifdef CONFIG_SERIAL_BFIN_CTSRTS
6f95570e
SZ		 794 if (uart->cts_pin >= 0)
795 free_irq(gpio_to_irq(uart->cts_pin), uart);
796 if (uart->rts_pin >= 0)
797 gpio_free(uart->rts_pin);
d307d36a
SZ		 798#endif
799#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
800 if (uart->cts_pin >= 0)
801 gpio_free(uart->cts_pin);
802 if (uart->rts_pin >= 0)
803 gpio_free(uart->rts_pin);
804 if (UART_GET_IER(uart) && EDSSI)
805 free_irq(uart->status_irq, uart);
806#endif
194de561
BW		 807}
808
809static void
810bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
811 struct ktermios *old)
812{
813 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
814 unsigned long flags;
815 unsigned int baud, quot;
0c44a86d 816 unsigned short val, ier, lcr = 0;
194de561
BW		 817
818 switch (termios->c_cflag & CSIZE) {
819 case CS8:
820 lcr = WLS(8);
821 break;
822 case CS7:
823 lcr = WLS(7);
824 break;
825 case CS6:
826 lcr = WLS(6);
827 break;
828 case CS5:
829 lcr = WLS(5);
830 break;
831 default:
832 printk(KERN_ERR "%s: word lengh not supported\n",
71cc2c21 833 __func__);
194de561
BW		 834 }
835
84507794
SZ		 836 /* Anomaly notes:
837 * 05000231 - STOP bit is always set to 1 whatever the user is set.
838 */
839 if (termios->c_cflag & CSTOPB) {
840 if (ANOMALY_05000231)
841 printk(KERN_WARNING "STOP bits other than 1 is not "
842 "supported in case of anomaly 05000231.\n");
843 else
844 lcr |= STB;
845 }
19aa6382 846 if (termios->c_cflag & PARENB)
194de561 847 lcr |= PEN;
19aa6382
MF		 848 if (!(termios->c_cflag & PARODD))
849 lcr |= EPS;
850 if (termios->c_cflag & CMSPAR)
851 lcr |= STP;
194de561 852
2ac5ee47
MF		 853 port->read_status_mask = OE;
854 if (termios->c_iflag & INPCK)
855 port->read_status_mask |= (FE | PE);
856 if (termios->c_iflag & (BRKINT | PARMRK))
857 port->read_status_mask |= BI;
194de561 858
2ac5ee47
MF		 859 /*
860 * Characters to ignore
861 */
862 port->ignore_status_mask = 0;
863 if (termios->c_iflag & IGNPAR)
864 port->ignore_status_mask |= FE | PE;
865 if (termios->c_iflag & IGNBRK) {
866 port->ignore_status_mask |= BI;
867 /*
868 * If we're ignoring parity and break indicators,
869 * ignore overruns too (for real raw support).
870 */
871 if (termios->c_iflag & IGNPAR)
872 port->ignore_status_mask |= OE;
873 }
194de561
BW		 874
875 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
f4487101 876 quot = uart_get_divisor(port, baud) - ANOMALY_05000230;
194de561
BW		 877 spin_lock_irqsave(&uart->port.lock, flags);
878
8851c71e
MF		 879 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
880
194de561
BW		 881 /* Disable UART */
882 ier = UART_GET_IER(uart);
1feaa51d 883 UART_DISABLE_INTS(uart);
194de561
BW		 884
885 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 886 UART_SET_DLAB(uart);
194de561
BW		 887
888 UART_PUT_DLL(uart, quot & 0xFF);
194de561
BW		 889 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
890 SSYNC();
891
892 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 893 UART_CLEAR_DLAB(uart);
194de561
BW		 894
895 UART_PUT_LCR(uart, lcr);
896
897 /* Enable UART */
1feaa51d 898 UART_ENABLE_INTS(uart, ier);
194de561
BW		 899
900 val = UART_GET_GCTL(uart);
901 val |= UCEN;
902 UART_PUT_GCTL(uart, val);
903
b3ef5aba
GY		 904 /* Port speed changed, update the per-port timeout. */
905 uart_update_timeout(port, termios->c_cflag, baud);
906
194de561
BW		 907 spin_unlock_irqrestore(&uart->port.lock, flags);
908}
909
910static const char *bfin_serial_type(struct uart_port *port)
911{
912 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
913
914 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
915}
916
917/*
918 * Release the memory region(s) being used by 'port'.
919 */
920static void bfin_serial_release_port(struct uart_port *port)
921{
922}
923
924/*
925 * Request the memory region(s) being used by 'port'.
926 */
927static int bfin_serial_request_port(struct uart_port *port)
928{
929 return 0;
930}
931
932/*
933 * Configure/autoconfigure the port.
934 */
935static void bfin_serial_config_port(struct uart_port *port, int flags)
936{
937 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
938
939 if (flags & UART_CONFIG_TYPE &&
940 bfin_serial_request_port(&uart->port) == 0)
941 uart->port.type = PORT_BFIN;
942}
943
944/*
945 * Verify the new serial_struct (for TIOCSSERIAL).
946 * The only change we allow are to the flags and type, and
947 * even then only between PORT_BFIN and PORT_UNKNOWN
948 */
949static int
950bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
951{
952 return 0;
953}
954
7d01b475
GY		 955/*
956 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
957 * In other cases, disable IrDA function.
958 */
3b8458a9 959static void bfin_serial_set_ldisc(struct uart_port *port)
7d01b475 960{
3b8458a9 961 int line = port->line;
7d01b475
GY		 962 unsigned short val;
963
a88487c7 964 if (line >= port->info->port.tty->driver->num)
7d01b475
GY		 965 return;
966
b1cbefe5 967 switch (port->info->port.tty->termios->c_line) {
7d01b475
GY		 968 case N_IRDA:
969 val = UART_GET_GCTL(&bfin_serial_ports[line]);
970 val |= (IREN | RPOLC);
971 UART_PUT_GCTL(&bfin_serial_ports[line], val);
972 break;
973 default:
974 val = UART_GET_GCTL(&bfin_serial_ports[line]);
975 val &= ~(IREN | RPOLC);
976 UART_PUT_GCTL(&bfin_serial_ports[line], val);
977 }
978}
979
6f95570e
SZ		 980static void bfin_serial_reset_irda(struct uart_port *port)
981{
982 int line = port->line;
983 unsigned short val;
984
985 val = UART_GET_GCTL(&bfin_serial_ports[line]);
986 val &= ~(IREN | RPOLC);
987 UART_PUT_GCTL(&bfin_serial_ports[line], val);
988 SSYNC();
989 val |= (IREN | RPOLC);
990 UART_PUT_GCTL(&bfin_serial_ports[line], val);
991 SSYNC();
992}
993
52e15f0e 994#ifdef CONFIG_CONSOLE_POLL
0efa4f2c
SZ		 995/* Anomaly notes:
996 * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
997 * losing other bits of UART_LSR is not a problem here.
998 */
52e15f0e
SZ		 999static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
1000{
1001 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1002
1003 while (!(UART_GET_LSR(uart) & THRE))
1004 cpu_relax();
1005
1006 UART_CLEAR_DLAB(uart);
1007 UART_PUT_CHAR(uart, (unsigned char)chr);
1008}
1009
1010static int bfin_serial_poll_get_char(struct uart_port *port)
1011{
1012 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1013 unsigned char chr;
1014
1015 while (!(UART_GET_LSR(uart) & DR))
1016 cpu_relax();
1017
1018 UART_CLEAR_DLAB(uart);
1019 chr = UART_GET_CHAR(uart);
1020
1021 return chr;
1022}
1023#endif
1024
1025#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1026 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1027static void bfin_kgdboc_port_shutdown(struct uart_port *port)
1028{
1029 if (kgdboc_break_enabled) {
1030 kgdboc_break_enabled = 0;
1031 bfin_serial_shutdown(port);
1032 }
1033}
1034
1035static int bfin_kgdboc_port_startup(struct uart_port *port)
1036{
1037 kgdboc_port_line = port->line;
1038 kgdboc_break_enabled = !bfin_serial_startup(port);
1039 return 0;
1040}
1041#endif
1042
194de561
BW		 1043static struct uart_ops bfin_serial_pops = {
1044 .tx_empty = bfin_serial_tx_empty,
1045 .set_mctrl = bfin_serial_set_mctrl,
1046 .get_mctrl = bfin_serial_get_mctrl,
1047 .stop_tx = bfin_serial_stop_tx,
1048 .start_tx = bfin_serial_start_tx,
1049 .stop_rx = bfin_serial_stop_rx,
1050 .enable_ms = bfin_serial_enable_ms,
1051 .break_ctl = bfin_serial_break_ctl,
1052 .startup = bfin_serial_startup,
1053 .shutdown = bfin_serial_shutdown,
1054 .set_termios = bfin_serial_set_termios,
3b8458a9 1055 .set_ldisc = bfin_serial_set_ldisc,
194de561
BW		 1056 .type = bfin_serial_type,
1057 .release_port = bfin_serial_release_port,
1058 .request_port = bfin_serial_request_port,
1059 .config_port = bfin_serial_config_port,
1060 .verify_port = bfin_serial_verify_port,
52e15f0e
SZ		 1061#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1062 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1063 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1064 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1065#endif
1066#ifdef CONFIG_CONSOLE_POLL
1067 .poll_put_char = bfin_serial_poll_put_char,
1068 .poll_get_char = bfin_serial_poll_get_char,
1069#endif
194de561
BW		 1070};
1071
6f95570e
SZ		 1072static void __init bfin_serial_hw_init(void)
1073{
1074#ifdef CONFIG_SERIAL_BFIN_UART0
1075 peripheral_request(P_UART0_TX, DRIVER_NAME);
1076 peripheral_request(P_UART0_RX, DRIVER_NAME);
1077#endif
1078
1079#ifdef CONFIG_SERIAL_BFIN_UART1
1080 peripheral_request(P_UART1_TX, DRIVER_NAME);
1081 peripheral_request(P_UART1_RX, DRIVER_NAME);
1082
1083# if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1084 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1085 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1086# endif
1087#endif
1088
1089#ifdef CONFIG_SERIAL_BFIN_UART2
1090 peripheral_request(P_UART2_TX, DRIVER_NAME);
1091 peripheral_request(P_UART2_RX, DRIVER_NAME);
1092#endif
1093
1094#ifdef CONFIG_SERIAL_BFIN_UART3
1095 peripheral_request(P_UART3_TX, DRIVER_NAME);
1096 peripheral_request(P_UART3_RX, DRIVER_NAME);
1097
1098# if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1099 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1100 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1101# endif
1102#endif
1103}
1104
194de561
BW		 1105static void __init bfin_serial_init_ports(void)
1106{
1107 static int first = 1;
1108 int i;
1109
1110 if (!first)
1111 return;
1112 first = 0;
1113
6f95570e
SZ		 1114 bfin_serial_hw_init();
1115
c9607ecc 1116 for (i = 0; i < nr_active_ports; i++) {
9c529a3d 1117 spin_lock_init(&bfin_serial_ports[i].port.lock);
194de561 1118 bfin_serial_ports[i].port.uartclk = get_sclk();
b3ef5aba 1119 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
194de561
BW		 1120 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
1121 bfin_serial_ports[i].port.line = i;
1122 bfin_serial_ports[i].port.iotype = UPIO_MEM;
1123 bfin_serial_ports[i].port.membase =
1124 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1125 bfin_serial_ports[i].port.mapbase =
1126 bfin_serial_resource[i].uart_base_addr;
1127 bfin_serial_ports[i].port.irq =
1128 bfin_serial_resource[i].uart_irq;
d307d36a
SZ		 1129 bfin_serial_ports[i].status_irq =
1130 bfin_serial_resource[i].uart_status_irq;
194de561
BW		 1131 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
1132#ifdef CONFIG_SERIAL_BFIN_DMA
1133 bfin_serial_ports[i].tx_done = 1;
1134 bfin_serial_ports[i].tx_count = 0;
1135 bfin_serial_ports[i].tx_dma_channel =
1136 bfin_serial_resource[i].uart_tx_dma_channel;
1137 bfin_serial_ports[i].rx_dma_channel =
1138 bfin_serial_resource[i].uart_rx_dma_channel;
1139 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
194de561 1140#endif
d307d36a
SZ		 1141#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1142 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
194de561
BW		 1143 bfin_serial_ports[i].cts_pin =
1144 bfin_serial_resource[i].uart_cts_pin;
1145 bfin_serial_ports[i].rts_pin =
1146 bfin_serial_resource[i].uart_rts_pin;
1147#endif
194de561
BW		 1148 }
1149}
1150
b6efa1ea 1151#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
194de561
BW		 1152/*
1153 * If the port was already initialised (eg, by a boot loader),
1154 * try to determine the current setup.
1155 */
1156static void __init
1157bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1158 int *parity, int *bits)
1159{
1160 unsigned short status;
1161
1162 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1163 if (status == (ERBFI | ETBEI)) {
1164 /* ok, the port was enabled */
45828b81 1165 u16 lcr, dlh, dll;
194de561
BW		 1166
1167 lcr = UART_GET_LCR(uart);
1168
1169 *parity = 'n';
1170 if (lcr & PEN) {
1171 if (lcr & EPS)
1172 *parity = 'e';
1173 else
1174 *parity = 'o';
1175 }
1176 switch (lcr & 0x03) {
1177 case 0: *bits = 5; break;
1178 case 1: *bits = 6; break;
1179 case 2: *bits = 7; break;
1180 case 3: *bits = 8; break;
1181 }
1182 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 1183 UART_SET_DLAB(uart);
194de561
BW		 1184
1185 dll = UART_GET_DLL(uart);
1186 dlh = UART_GET_DLH(uart);
1187
1188 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 1189 UART_CLEAR_DLAB(uart);
194de561
BW		 1190
1191 *baud = get_sclk() / (16*(dll | dlh << 8));
1192 }
71cc2c21 1193 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
194de561 1194}
0ae53640 1195
0ae53640 1196static struct uart_driver bfin_serial_reg;
194de561
BW		 1197
1198static int __init
1199bfin_serial_console_setup(struct console *co, char *options)
1200{
1201 struct bfin_serial_port *uart;
1202 int baud = 57600;
1203 int bits = 8;
1204 int parity = 'n';
d307d36a
SZ		 1205# if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1206 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
194de561 1207 int flow = 'r';
b6efa1ea 1208# else
194de561 1209 int flow = 'n';
0ae53640 1210# endif
194de561
BW		 1211
1212 /*
1213 * Check whether an invalid uart number has been specified, and
1214 * if so, search for the first available port that does have
1215 * console support.
1216 */
c9607ecc 1217 if (co->index == -1 || co->index >= nr_active_ports)
194de561
BW		 1218 co->index = 0;
1219 uart = &bfin_serial_ports[co->index];
1220
1221 if (options)
1222 uart_parse_options(options, &baud, &parity, &bits, &flow);
1223 else
1224 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1225
1226 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG		 1227}
1228#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1229 defined (CONFIG_EARLY_PRINTK) */
1230
1231#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1232static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1233{
1234 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1235 while (!(UART_GET_LSR(uart) & THRE))
1236 barrier();
1237 UART_PUT_CHAR(uart, ch);
1238 SSYNC();
1239}
1240
1241/*
1242 * Interrupts are disabled on entering
1243 */
1244static void
1245bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1246{
1247 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
59e4e3e6 1248 unsigned long flags;
0ae53640
RG		 1249
1250 spin_lock_irqsave(&uart->port.lock, flags);
1251 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1252 spin_unlock_irqrestore(&uart->port.lock, flags);
1253
194de561
BW		 1254}
1255
194de561
BW		 1256static struct console bfin_serial_console = {
1257 .name = BFIN_SERIAL_NAME,
1258 .write = bfin_serial_console_write,
1259 .device = uart_console_device,
1260 .setup = bfin_serial_console_setup,
1261 .flags = CON_PRINTBUFFER,
1262 .index = -1,
1263 .data = &bfin_serial_reg,
1264};
1265
1266static int __init bfin_serial_rs_console_init(void)
1267{
1268 bfin_serial_init_ports();
1269 register_console(&bfin_serial_console);
52e15f0e 1270
194de561
BW		 1271 return 0;
1272}
1273console_initcall(bfin_serial_rs_console_init);
1274
1275#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1276#else
1277#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG		 1278#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1279
1280
1281#ifdef CONFIG_EARLY_PRINTK
1282static __init void early_serial_putc(struct uart_port *port, int ch)
1283{
1284 unsigned timeout = 0xffff;
1285 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1286
1287 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1288 cpu_relax();
1289 UART_PUT_CHAR(uart, ch);
1290}
1291
1292static __init void early_serial_write(struct console *con, const char *s,
1293 unsigned int n)
1294{
1295 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1296 unsigned int i;
1297
1298 for (i = 0; i < n; i++, s++) {
1299 if (*s == '\n')
1300 early_serial_putc(&uart->port, '\r');
1301 early_serial_putc(&uart->port, *s);
1302 }
1303}
1304
7de7c55b
RG		 1305/*
1306 * This should have a .setup or .early_setup in it, but then things get called
1307 * without the command line options, and the baud rate gets messed up - so
1308 * don't let the common infrastructure play with things. (see calls to setup
1309 * & earlysetup in ./kernel/printk.c:register_console()
1310 */
c1113400 1311static struct __initdata console bfin_early_serial_console = {
0ae53640
RG		 1312 .name = "early_BFuart",
1313 .write = early_serial_write,
1314 .device = uart_console_device,
1315 .flags = CON_PRINTBUFFER,
0ae53640
RG		 1316 .index = -1,
1317 .data = &bfin_serial_reg,
1318};
1319
1320struct console __init *bfin_earlyserial_init(unsigned int port,
1321 unsigned int cflag)
1322{
1323 struct bfin_serial_port *uart;
1324 struct ktermios t;
1325
c9607ecc 1326 if (port == -1 || port >= nr_active_ports)
0ae53640
RG		 1327 port = 0;
1328 bfin_serial_init_ports();
1329 bfin_early_serial_console.index = port;
0ae53640
RG		 1330 uart = &bfin_serial_ports[port];
1331 t.c_cflag = cflag;
1332 t.c_iflag = 0;
1333 t.c_oflag = 0;
1334 t.c_lflag = ICANON;
1335 t.c_line = port;
1336 bfin_serial_set_termios(&uart->port, &t, &t);
1337 return &bfin_early_serial_console;
1338}
1339
b6efa1ea 1340#endif /* CONFIG_EARLY_PRINTK */
194de561
BW		 1341
1342static struct uart_driver bfin_serial_reg = {
1343 .owner = THIS_MODULE,
1344 .driver_name = "bfin-uart",
1345 .dev_name = BFIN_SERIAL_NAME,
1346 .major = BFIN_SERIAL_MAJOR,
1347 .minor = BFIN_SERIAL_MINOR,
2ade9729 1348 .nr = BFIN_UART_NR_PORTS,
194de561
BW		 1349 .cons = BFIN_SERIAL_CONSOLE,
1350};
1351
1352static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1353{
ccfbc3e1 1354 int i;
194de561 1355
c9607ecc 1356 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1357 if (bfin_serial_ports[i].port.dev != &dev->dev)
1358 continue;
1359 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1360 }
194de561
BW		 1361
1362 return 0;
1363}
1364
1365static int bfin_serial_resume(struct platform_device *dev)
1366{
ccfbc3e1 1367 int i;
194de561 1368
c9607ecc 1369 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1370 if (bfin_serial_ports[i].port.dev != &dev->dev)
1371 continue;
1372 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1373 }
194de561
BW		 1374
1375 return 0;
1376}
1377
1378static int bfin_serial_probe(struct platform_device *dev)
1379{
1380 struct resource *res = dev->resource;
1381 int i;
1382
1383 for (i = 0; i < dev->num_resources; i++, res++)
1384 if (res->flags & IORESOURCE_MEM)
1385 break;
1386
1387 if (i < dev->num_resources) {
c9607ecc 1388 for (i = 0; i < nr_active_ports; i++, res++) {
194de561
BW		 1389 if (bfin_serial_ports[i].port.mapbase != res->start)
1390 continue;
1391 bfin_serial_ports[i].port.dev = &dev->dev;
1392 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
194de561
BW		 1393 }
1394 }
1395
1396 return 0;
1397}
1398
ccfbc3e1 1399static int bfin_serial_remove(struct platform_device *dev)
194de561 1400{
ccfbc3e1 1401 int i;
194de561 1402
c9607ecc 1403 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1404 if (bfin_serial_ports[i].port.dev != &dev->dev)
1405 continue;
1406 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1407 bfin_serial_ports[i].port.dev = NULL;
d307d36a
SZ		 1408#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1409 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
ccfbc3e1
SZ		 1410 gpio_free(bfin_serial_ports[i].cts_pin);
1411 gpio_free(bfin_serial_ports[i].rts_pin);
194de561 1412#endif
ccfbc3e1 1413 }
194de561
BW		 1414
1415 return 0;
1416}
1417
1418static struct platform_driver bfin_serial_driver = {
1419 .probe = bfin_serial_probe,
1420 .remove = bfin_serial_remove,
1421 .suspend = bfin_serial_suspend,
1422 .resume = bfin_serial_resume,
1423 .driver = {
1424 .name = "bfin-uart",
e169c139 1425 .owner = THIS_MODULE,
194de561
BW		 1426 },
1427};
1428
1429static int __init bfin_serial_init(void)
1430{
1431 int ret;
1432
1433 pr_info("Serial: Blackfin serial driver\n");
1434
1435 bfin_serial_init_ports();
1436
1437 ret = uart_register_driver(&bfin_serial_reg);
1438 if (ret == 0) {
1439 ret = platform_driver_register(&bfin_serial_driver);
1440 if (ret) {
1441 pr_debug("uart register failed\n");
1442 uart_unregister_driver(&bfin_serial_reg);
1443 }
1444 }
1445 return ret;
1446}
1447
1448static void __exit bfin_serial_exit(void)
1449{
1450 platform_driver_unregister(&bfin_serial_driver);
1451 uart_unregister_driver(&bfin_serial_reg);
1452}
1453
52e15f0e 1454
194de561
BW		 1455module_init(bfin_serial_init);
1456module_exit(bfin_serial_exit);
1457
1458MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1459MODULE_DESCRIPTION("Blackfin generic serial port driver");
1460MODULE_LICENSE("GPL");
1461MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
e169c139 1462MODULE_ALIAS("platform:bfin-uart");
Linux kernel - Deliverables
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