[deliverable/linux.git] / drivers / serial / cpm_uart / cpm_uart.h

/*
 *  linux/drivers/serial/cpm_uart.h
 *
 *  Driver for CPM (SCC/SMC) serial ports
 *
 *  Copyright (C) 2004 Freescale Semiconductor, Inc.
 *
 *  2006 (c) MontaVista Software, Inc.
 *	Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 *
 */
#ifndef CPM_UART_H
#define CPM_UART_H

#include <linux/platform_device.h>
#include <linux/fs_uart_pd.h>

#if defined(CONFIG_CPM2)
#include "cpm_uart_cpm2.h"
#elif defined(CONFIG_8xx)
#include "cpm_uart_cpm1.h"
#endif

#define SERIAL_CPM_MAJOR	204
#define SERIAL_CPM_MINOR	46

#define IS_SMC(pinfo)		(pinfo->flags & FLAG_SMC)
#define IS_DISCARDING(pinfo)	(pinfo->flags & FLAG_DISCARDING)
#define FLAG_DISCARDING	0x00000004	/* when set, don't discard */
#define FLAG_SMC	0x00000002
#define FLAG_CONSOLE	0x00000001

#define UART_SMC1	fsid_smc1_uart
#define UART_SMC2	fsid_smc2_uart
#define UART_SCC1	fsid_scc1_uart
#define UART_SCC2	fsid_scc2_uart
#define UART_SCC3	fsid_scc3_uart
#define UART_SCC4	fsid_scc4_uart

#define UART_NR		fs_uart_nr

#define RX_NUM_FIFO	4
#define RX_BUF_SIZE	32
#define TX_NUM_FIFO	4
#define TX_BUF_SIZE	32

#define SCC_WAIT_CLOSING 100

#define GPIO_CTS	0
#define GPIO_RTS	1
#define GPIO_DCD	2
#define GPIO_DSR	3
#define GPIO_DTR	4
#define GPIO_RI		5

#define NUM_GPIOS	(GPIO_RI+1)

struct uart_cpm_port {
	struct uart_port	port;
	u16			rx_nrfifos;
	u16			rx_fifosize;
	u16			tx_nrfifos;
	u16			tx_fifosize;
	smc_t __iomem		*smcp;
	smc_uart_t __iomem	*smcup;
	scc_t __iomem		*sccp;
	scc_uart_t __iomem	*sccup;
	cbd_t __iomem		*rx_bd_base;
	cbd_t __iomem		*rx_cur;
	cbd_t __iomem		*tx_bd_base;
	cbd_t __iomem		*tx_cur;
	unsigned char		*tx_buf;
	unsigned char		*rx_buf;
	u32			flags;
	struct clk		*clk;
	u8			brg;
	uint			 dp_addr;
	void			*mem_addr;
	dma_addr_t		 dma_addr;
	u32			mem_size;
	/* wait on close if needed */
	int			wait_closing;
	/* value to combine with opcode to form cpm command */
	u32			command;
	int			gpios[NUM_GPIOS];
};

extern int cpm_uart_nr;
extern struct uart_cpm_port cpm_uart_ports[UART_NR];

/* these are located in their respective files */
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
				struct device_node *np);
void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
int cpm_uart_init_portdesc(void);
int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
void cpm_uart_freebuf(struct uart_cpm_port *pinfo);

void smc1_lineif(struct uart_cpm_port *pinfo);
void smc2_lineif(struct uart_cpm_port *pinfo);
void scc1_lineif(struct uart_cpm_port *pinfo);
void scc2_lineif(struct uart_cpm_port *pinfo);
void scc3_lineif(struct uart_cpm_port *pinfo);
void scc4_lineif(struct uart_cpm_port *pinfo);

/*
   virtual to phys transtalion
*/
static inline unsigned long cpu2cpm_addr(void *addr,
                                         struct uart_cpm_port *pinfo)
{
	int offset;
	u32 val = (u32)addr;
	u32 mem = (u32)pinfo->mem_addr;
	/* sane check */
	if (likely(val >= mem && val < mem + pinfo->mem_size)) {
		offset = val - mem;
		return pinfo->dma_addr + offset;
	}
	/* something nasty happened */
	BUG();
	return 0;
}

static inline void *cpm2cpu_addr(unsigned long addr,
                                 struct uart_cpm_port *pinfo)
{
	int offset;
	u32 val = addr;
	u32 dma = (u32)pinfo->dma_addr;
	/* sane check */
	if (likely(val >= dma && val < dma + pinfo->mem_size)) {
		offset = val - dma;
		return pinfo->mem_addr + offset;
	}
	/* something nasty happened */
	BUG();
	return NULL;
}


#endif /* CPM_UART_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/serial/cpm_uart.h
	3	*
	4	* Driver for CPM (SCC/SMC) serial ports
	5	*
	6	* Copyright (C) 2004 Freescale Semiconductor, Inc.
	7	*
6e197696	8	* 2006 (c) MontaVista Software, Inc.
0d844065	9	* Vitaly Bordug <vbordug@ru.mvista.com>
6e197696 VB	10	*
	11	* This file is licensed under the terms of the GNU General Public License
	12	* version 2. This program is licensed "as is" without any warranty of any
	13	* kind, whether express or implied.
	14	*
1da177e4 LT	15	*/
	16	#ifndef CPM_UART_H
	17	#define CPM_UART_H
	18
e27987cd VB	19	#include <linux/platform_device.h>
e27987cd VB	20	#include <linux/fs_uart_pd.h>
1da177e4 LT	21
	22	#if defined(CONFIG_CPM2)
	23	#include "cpm_uart_cpm2.h"
	24	#elif defined(CONFIG_8xx)
	25	#include "cpm_uart_cpm1.h"
	26	#endif
	27
	28	#define SERIAL_CPM_MAJOR 204
	29	#define SERIAL_CPM_MINOR 46
	30
0d844065	31	#define IS_SMC(pinfo) (pinfo->flags & FLAG_SMC)
1da177e4 LT	32	#define IS_DISCARDING(pinfo) (pinfo->flags & FLAG_DISCARDING)
	33	#define FLAG_DISCARDING 0x00000004 /* when set, don't discard */
	34	#define FLAG_SMC 0x00000002
	35	#define FLAG_CONSOLE 0x00000001
	36
e27987cd VB	37	#define UART_SMC1 fsid_smc1_uart
	38	#define UART_SMC2 fsid_smc2_uart
	39	#define UART_SCC1 fsid_scc1_uart
	40	#define UART_SCC2 fsid_scc2_uart
	41	#define UART_SCC3 fsid_scc3_uart
	42	#define UART_SCC4 fsid_scc4_uart
1da177e4	43
e27987cd	44	#define UART_NR fs_uart_nr
1da177e4 LT	45
	46	#define RX_NUM_FIFO 4
	47	#define RX_BUF_SIZE 32
	48	#define TX_NUM_FIFO 4
	49	#define TX_BUF_SIZE 32
	50
311c4627 KG	51	#define SCC_WAIT_CLOSING 100
311c4627 KG	52
7485d26b LP	53	#define GPIO_CTS 0
	54	#define GPIO_RTS 1
	55	#define GPIO_DCD 2
	56	#define GPIO_DSR 3
	57	#define GPIO_DTR 4
	58	#define GPIO_RI 5
	59
	60	#define NUM_GPIOS (GPIO_RI+1)
	61
1da177e4 LT	62	struct uart_cpm_port {
1da177e4 LT	63	struct uart_port port;
311c4627	64	u16 rx_nrfifos;
1da177e4	65	u16 rx_fifosize;
311c4627	66	u16 tx_nrfifos;
1da177e4	67	u16 tx_fifosize;
c1dcfd9d SW	68	smc_t __iomem *smcp;
	69	smc_uart_t __iomem *smcup;
	70	scc_t __iomem *sccp;
	71	scc_uart_t __iomem *sccup;
	72	cbd_t __iomem *rx_bd_base;
	73	cbd_t __iomem *rx_cur;
	74	cbd_t __iomem *tx_bd_base;
	75	cbd_t __iomem *tx_cur;
1da177e4 LT	76	unsigned char *tx_buf;
	77	unsigned char *rx_buf;
	78	u32 flags;
80776554	79	struct clk *clk;
1da177e4 LT	80	u8 brg;
1da177e4 LT	81	uint dp_addr;
0d844065	82	void *mem_addr;
1da177e4	83	dma_addr_t dma_addr;
09b03b6c	84	u32 mem_size;
311c4627	85	/* wait on close if needed */
0d844065	86	int wait_closing;
7ae87036 SW	87	/* value to combine with opcode to form cpm command */
7ae87036 SW	88	u32 command;
7485d26b	89	int gpios[NUM_GPIOS];
1da177e4 LT	90	};
1da177e4 LT	91
1da177e4 LT	92	extern int cpm_uart_nr;
	93	extern struct uart_cpm_port cpm_uart_ports[UART_NR];
	94
	95	/* these are located in their respective files */
7ae87036	96	void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
d464df26 LP	97	void __iomem cpm_uart_map_pram(struct uart_cpm_port port,
	98	struct device_node *np);
	99	void cpm_uart_unmap_pram(struct uart_cpm_port port, void __iomem pram);
32a56ebb	100	int cpm_uart_init_portdesc(void);
1da177e4 LT	101	int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
	102	void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
	103
	104	void smc1_lineif(struct uart_cpm_port *pinfo);
	105	void smc2_lineif(struct uart_cpm_port *pinfo);
	106	void scc1_lineif(struct uart_cpm_port *pinfo);
	107	void scc2_lineif(struct uart_cpm_port *pinfo);
	108	void scc3_lineif(struct uart_cpm_port *pinfo);
	109	void scc4_lineif(struct uart_cpm_port *pinfo);
	110
09b03b6c VB	111	/*
	112	virtual to phys transtalion
	113	*/
c1dcfd9d SW	114	static inline unsigned long cpu2cpm_addr(void *addr,
c1dcfd9d SW	115	struct uart_cpm_port *pinfo)
09b03b6c VB	116	{
	117	int offset;
	118	u32 val = (u32)addr;
c1dcfd9d	119	u32 mem = (u32)pinfo->mem_addr;
09b03b6c	120	/* sane check */
c1dcfd9d SW	121	if (likely(val >= mem && val < mem + pinfo->mem_size)) {
	122	offset = val - mem;
	123	return pinfo->dma_addr + offset;
09b03b6c	124	}
6e197696 VB	125	/* something nasty happened */
6e197696 VB	126	BUG();
09b03b6c VB	127	return 0;
	128	}
	129
c1dcfd9d SW	130	static inline void *cpm2cpu_addr(unsigned long addr,
c1dcfd9d SW	131	struct uart_cpm_port *pinfo)
09b03b6c VB	132	{
	133	int offset;
	134	u32 val = addr;
c1dcfd9d	135	u32 dma = (u32)pinfo->dma_addr;
09b03b6c	136	/* sane check */
c1dcfd9d SW	137	if (likely(val >= dma && val < dma + pinfo->mem_size)) {
	138	offset = val - dma;
	139	return pinfo->mem_addr + offset;
09b03b6c	140	}
6e197696 VB	141	/* something nasty happened */
6e197696 VB	142	BUG();
c1dcfd9d	143	return NULL;
09b03b6c VB	144	}
	145
	146
1da177e4	147	#endif /* CPM_UART_H */