[deliverable/linux.git] / drivers / serial / cpm_uart / cpm_uart_cpm2.c

/*
 *  linux/drivers/serial/cpm_uart_cpm2.c
 *
 *  Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
 *
 *  Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
 *              Pantelis Antoniou (panto@intracom.gr) (CPM1)
 * 
 *  Copyright (C) 2004 Freescale Semiconductor, Inc.
 *            (C) 2004 Intracom, S.A.
 *            (C) 2006 MontaVista Software, Inc.
 * 		Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/module.h>
#include <linux/tty.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/device.h>
#include <linux/bootmem.h>
#include <linux/dma-mapping.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/fs_pd.h>

#include <linux/serial_core.h>
#include <linux/kernel.h>

#include "cpm_uart.h"

/**************************************************************/

void cpm_line_cr_cmd(int line, int cmd)
{
	ulong val;
	volatile cpm_cpm2_t *cp = cpm2_map(im_cpm);


	switch (line) {
	case UART_SMC1:
		val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
				cmd) | CPM_CR_FLG;
		break;
	case UART_SMC2:
		val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
				cmd) | CPM_CR_FLG;
		break;
	case UART_SCC1:
		val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
				cmd) | CPM_CR_FLG;
		break;
	case UART_SCC2:
		val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
				cmd) | CPM_CR_FLG;
		break;
	case UART_SCC3:
		val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
				cmd) | CPM_CR_FLG;
		break;
	case UART_SCC4:
		val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
				cmd) | CPM_CR_FLG;
		break;
	default:
		return;

	}
	cp->cp_cpcr = val;
	while (cp->cp_cpcr & CPM_CR_FLG) ;

	cpm2_unmap(cp);
}

void smc1_lineif(struct uart_cpm_port *pinfo)
{
	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);

	/* SMC1 is only on port D */
	io->iop_ppard |= 0x00c00000;
	io->iop_pdird |= 0x00400000;
	io->iop_pdird &= ~0x00800000;
	io->iop_psord &= ~0x00c00000;

	/* Wire BRG1 to SMC1 */
	cpmux->cmx_smr &= 0x0f;
	pinfo->brg = 1;

	cpm2_unmap(cpmux);
	cpm2_unmap(io);
}

void smc2_lineif(struct uart_cpm_port *pinfo)
{
	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);

	/* SMC2 is only on port A */
	io->iop_ppara |= 0x00c00000;
	io->iop_pdira |= 0x00400000;
	io->iop_pdira &= ~0x00800000;
	io->iop_psora &= ~0x00c00000;

	/* Wire BRG2 to SMC2 */
	cpmux->cmx_smr &= 0xf0;
	pinfo->brg = 2;

	cpm2_unmap(cpmux);
	cpm2_unmap(io);
}

void scc1_lineif(struct uart_cpm_port *pinfo)
{
	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);

	/* Use Port D for SCC1 instead of other functions.  */
	io->iop_ppard |= 0x00000003;
	io->iop_psord &= ~0x00000001;	/* Rx */
	io->iop_psord |= 0x00000002;	/* Tx */
	io->iop_pdird &= ~0x00000001;	/* Rx */
	io->iop_pdird |= 0x00000002;	/* Tx */

	/* Wire BRG1 to SCC1 */
	cpmux->cmx_scr &= 0x00ffffff;
	cpmux->cmx_scr |= 0x00000000;
	pinfo->brg = 1;

	cpm2_unmap(cpmux);
	cpm2_unmap(io);
}

void scc2_lineif(struct uart_cpm_port *pinfo)
{
	/*
	 * STx GP3 uses the SCC2 secondary option pin assignment
	 * which this driver doesn't account for in the static
	 * pin assignments. This kind of board specific info
	 * really has to get out of the driver so boards can
	 * be supported in a sane fashion.
	 */
#ifndef CONFIG_STX_GP3
	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);

	io->iop_pparb |= 0x008b0000;
	io->iop_pdirb |= 0x00880000;
	io->iop_psorb |= 0x00880000;
	io->iop_pdirb &= ~0x00030000;
	io->iop_psorb &= ~0x00030000;
#endif
	cpmux->cmx_scr &= 0xff00ffff;
	cpmux->cmx_scr |= 0x00090000;
	pinfo->brg = 2;

	cpm2_unmap(cpmux);
	cpm2_unmap(io);
}

void scc3_lineif(struct uart_cpm_port *pinfo)
{
	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);

	io->iop_pparb |= 0x008b0000;
	io->iop_pdirb |= 0x00880000;
	io->iop_psorb |= 0x00880000;
	io->iop_pdirb &= ~0x00030000;
	io->iop_psorb &= ~0x00030000;
	cpmux->cmx_scr &= 0xffff00ff;
	cpmux->cmx_scr |= 0x00001200;
	pinfo->brg = 3;

	cpm2_unmap(cpmux);
	cpm2_unmap(io);
}

void scc4_lineif(struct uart_cpm_port *pinfo)
{
	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);

	io->iop_ppard |= 0x00000600;
	io->iop_psord &= ~0x00000600;	/* Tx/Rx */
	io->iop_pdird &= ~0x00000200;	/* Rx */
	io->iop_pdird |= 0x00000400;	/* Tx */

	cpmux->cmx_scr &= 0xffffff00;
	cpmux->cmx_scr |= 0x0000001b;
	pinfo->brg = 4;

	cpm2_unmap(cpmux);
	cpm2_unmap(io);
}

/*
 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and 
 * receive buffer descriptors from dual port ram, and a character
 * buffer area from host mem. If we are allocating for the console we need
 * to do it from bootmem
 */
int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
{
	int dpmemsz, memsz;
	u8 *dp_mem;
	uint dp_offset;
	u8 *mem_addr;
	dma_addr_t dma_addr = 0;

	pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);

	dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
	dp_offset = cpm_dpalloc(dpmemsz, 8);
	if (IS_DPERR(dp_offset)) {
		printk(KERN_ERR
		       "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
		return -ENOMEM;
	}

	dp_mem = cpm_dpram_addr(dp_offset);

	memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
	    L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
	if (is_con) {
		mem_addr = alloc_bootmem(memsz);
		dma_addr = virt_to_bus(mem_addr);
	}
	else
		mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
					      GFP_KERNEL);

	if (mem_addr == NULL) {
		cpm_dpfree(dp_offset);
		printk(KERN_ERR
		       "cpm_uart_cpm.c: could not allocate coherent memory\n");
		return -ENOMEM;
	}

	pinfo->dp_addr = dp_offset;
	pinfo->mem_addr = mem_addr;
	pinfo->dma_addr = dma_addr;
	pinfo->mem_size = memsz;

	pinfo->rx_buf = mem_addr;
	pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
						       * pinfo->rx_fifosize);

	pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
	pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;

	return 0;
}

void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
{
	dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
					       pinfo->rx_fifosize) +
			  L1_CACHE_ALIGN(pinfo->tx_nrfifos *
					 pinfo->tx_fifosize), pinfo->mem_addr,
			  pinfo->dma_addr);

	cpm_dpfree(pinfo->dp_addr);
}

/* Setup any dynamic params in the uart desc */
int __init cpm_uart_init_portdesc(void)
{
#if defined(CONFIG_SERIAL_CPM_SMC1) || defined(CONFIG_SERIAL_CPM_SMC2)
	u32 addr;
#endif
	pr_debug("CPM uart[-]:init portdesc\n");

	cpm_uart_nr = 0;
#ifdef CONFIG_SERIAL_CPM_SMC1
	cpm_uart_ports[UART_SMC1].smcp = (smc_t *) cpm2_map(im_smc[0]);
	cpm_uart_ports[UART_SMC1].port.mapbase =
	    (unsigned long)cpm_uart_ports[UART_SMC1].smcp;

	cpm_uart_ports[UART_SMC1].smcup =
	    (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC1], PROFF_SMC_SIZE);
	addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC1_BASE], 2);
	*addr = PROFF_SMC1;
	cpm2_unmap(addr);

	cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
	cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
	cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
	cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
#endif

#ifdef CONFIG_SERIAL_CPM_SMC2
	cpm_uart_ports[UART_SMC2].smcp = (smc_t *) cpm2_map(im_smc[1]);
	cpm_uart_ports[UART_SMC2].port.mapbase =
	    (unsigned long)cpm_uart_ports[UART_SMC2].smcp;

	cpm_uart_ports[UART_SMC2].smcup =
	    (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC2], PROFF_SMC_SIZE);
	addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC2_BASE], 2);
	*addr = PROFF_SMC2;
	cpm2_unmap(addr);

	cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
	cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
	cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
	cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
#endif

#ifdef CONFIG_SERIAL_CPM_SCC1
	cpm_uart_ports[UART_SCC1].sccp = (scc_t *) cpm2_map(im_scc[0]);
	cpm_uart_ports[UART_SCC1].port.mapbase =
	    (unsigned long)cpm_uart_ports[UART_SCC1].sccp;
	cpm_uart_ports[UART_SCC1].sccup =
	    (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC1], PROFF_SCC_SIZE);

	cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
	    ~(UART_SCCM_TX | UART_SCCM_RX);
	cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
	    ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
	cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
	cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
#endif

#ifdef CONFIG_SERIAL_CPM_SCC2
	cpm_uart_ports[UART_SCC2].sccp = (scc_t *) cpm2_map(im_scc[1]);
	cpm_uart_ports[UART_SCC2].port.mapbase =
	    (unsigned long)cpm_uart_ports[UART_SCC2].sccp;
	cpm_uart_ports[UART_SCC2].sccup =
	    (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC2], PROFF_SCC_SIZE);

	cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
	    ~(UART_SCCM_TX | UART_SCCM_RX);
	cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
	    ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
	cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
	cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
#endif

#ifdef CONFIG_SERIAL_CPM_SCC3
	cpm_uart_ports[UART_SCC3].sccp = (scc_t *) cpm2_map(im_scc[2]);
	cpm_uart_ports[UART_SCC3].port.mapbase =
	    (unsigned long)cpm_uart_ports[UART_SCC3].sccp;
	cpm_uart_ports[UART_SCC3].sccup =
	    (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC3], PROFF_SCC_SIZE);

	cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
	    ~(UART_SCCM_TX | UART_SCCM_RX);
	cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
	    ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
	cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
	cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
#endif

#ifdef CONFIG_SERIAL_CPM_SCC4
	cpm_uart_ports[UART_SCC4].sccp = (scc_t *) cpm2_map(im_scc[3]);
	cpm_uart_ports[UART_SCC4].port.mapbase =
	    (unsigned long)cpm_uart_ports[UART_SCC4].sccp;
	cpm_uart_ports[UART_SCC4].sccup =
	    (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC4], PROFF_SCC_SIZE);

	cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
	    ~(UART_SCCM_TX | UART_SCCM_RX);
	cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
	    ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
	cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
	cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
#endif

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/serial/cpm_uart_cpm2.c
	3	*
	4	* Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
	5	*
4c8d3d99	6	* Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
1da177e4 LT	7	* Pantelis Antoniou (panto@intracom.gr) (CPM1)
	8	*
	9	* Copyright (C) 2004 Freescale Semiconductor, Inc.
	10	* (C) 2004 Intracom, S.A.
6e197696 VB	11	* (C) 2006 MontaVista Software, Inc.
6e197696 VB	12	* Vitaly Bordug <vbordug@ru.mvista.com>
1da177e4 LT	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	27	*
	28	*/
	29
1da177e4 LT	30	#include <linux/module.h>
	31	#include <linux/tty.h>
	32	#include <linux/ioport.h>
	33	#include <linux/init.h>
	34	#include <linux/serial.h>
	35	#include <linux/console.h>
	36	#include <linux/sysrq.h>
	37	#include <linux/device.h>
	38	#include <linux/bootmem.h>
	39	#include <linux/dma-mapping.h>
	40
	41	#include <asm/io.h>
	42	#include <asm/irq.h>
3dd0dcbe	43	#include <asm/fs_pd.h>
1da177e4 LT	44
	45	#include <linux/serial_core.h>
	46	#include <linux/kernel.h>
	47
	48	#include "cpm_uart.h"
	49
	50	/**************************************************************/
	51
	52	void cpm_line_cr_cmd(int line, int cmd)
	53	{
1da177e4	54	ulong val;
fc8e50e3 VB	55	volatile cpm_cpm2_t *cp = cpm2_map(im_cpm);
fc8e50e3 VB	56
1da177e4 LT	57
	58	switch (line) {
	59	case UART_SMC1:
	60	val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
	61	cmd) \| CPM_CR_FLG;
	62	break;
	63	case UART_SMC2:
	64	val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
	65	cmd) \| CPM_CR_FLG;
	66	break;
	67	case UART_SCC1:
	68	val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
	69	cmd) \| CPM_CR_FLG;
	70	break;
	71	case UART_SCC2:
	72	val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
	73	cmd) \| CPM_CR_FLG;
	74	break;
	75	case UART_SCC3:
	76	val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
	77	cmd) \| CPM_CR_FLG;
	78	break;
	79	case UART_SCC4:
	80	val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
	81	cmd) \| CPM_CR_FLG;
	82	break;
	83	default:
	84	return;
	85
	86	}
	87	cp->cp_cpcr = val;
	88	while (cp->cp_cpcr & CPM_CR_FLG) ;
fc8e50e3 VB	89
fc8e50e3 VB	90	cpm2_unmap(cp);
1da177e4 LT	91	}
	92
	93	void smc1_lineif(struct uart_cpm_port *pinfo)
	94	{
fc8e50e3 VB	95	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
fc8e50e3 VB	96	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
1da177e4 LT	97
	98	/* SMC1 is only on port D */
	99	io->iop_ppard \|= 0x00c00000;
	100	io->iop_pdird \|= 0x00400000;
	101	io->iop_pdird &= ~0x00800000;
	102	io->iop_psord &= ~0x00c00000;
	103
	104	/* Wire BRG1 to SMC1 */
fc8e50e3	105	cpmux->cmx_smr &= 0x0f;
1da177e4	106	pinfo->brg = 1;
fc8e50e3 VB	107
	108	cpm2_unmap(cpmux);
	109	cpm2_unmap(io);
1da177e4 LT	110	}
	111
	112	void smc2_lineif(struct uart_cpm_port *pinfo)
	113	{
fc8e50e3 VB	114	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
fc8e50e3 VB	115	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
1da177e4 LT	116
	117	/* SMC2 is only on port A */
	118	io->iop_ppara \|= 0x00c00000;
	119	io->iop_pdira \|= 0x00400000;
	120	io->iop_pdira &= ~0x00800000;
	121	io->iop_psora &= ~0x00c00000;
	122
	123	/* Wire BRG2 to SMC2 */
fc8e50e3	124	cpmux->cmx_smr &= 0xf0;
1da177e4	125	pinfo->brg = 2;
fc8e50e3 VB	126
	127	cpm2_unmap(cpmux);
	128	cpm2_unmap(io);
1da177e4 LT	129	}
	130
	131	void scc1_lineif(struct uart_cpm_port *pinfo)
	132	{
fc8e50e3 VB	133	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
fc8e50e3 VB	134	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
1da177e4 LT	135
	136	/* Use Port D for SCC1 instead of other functions. */
	137	io->iop_ppard \|= 0x00000003;
	138	io->iop_psord &= ~0x00000001; /* Rx */
	139	io->iop_psord \|= 0x00000002; /* Tx */
	140	io->iop_pdird &= ~0x00000001; /* Rx */
	141	io->iop_pdird \|= 0x00000002; /* Tx */
	142
	143	/* Wire BRG1 to SCC1 */
fc8e50e3 VB	144	cpmux->cmx_scr &= 0x00ffffff;
fc8e50e3 VB	145	cpmux->cmx_scr \|= 0x00000000;
1da177e4	146	pinfo->brg = 1;
fc8e50e3 VB	147
	148	cpm2_unmap(cpmux);
	149	cpm2_unmap(io);
1da177e4 LT	150	}
	151
	152	void scc2_lineif(struct uart_cpm_port *pinfo)
	153	{
a1604f91 MP	154	/*
	155	* STx GP3 uses the SCC2 secondary option pin assignment
	156	* which this driver doesn't account for in the static
	157	* pin assignments. This kind of board specific info
	158	* really has to get out of the driver so boards can
	159	* be supported in a sane fashion.
	160	*/
	161	#ifndef CONFIG_STX_GP3
fc8e50e3 VB	162	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
	163	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
	164
1da177e4 LT	165	io->iop_pparb \|= 0x008b0000;
	166	io->iop_pdirb \|= 0x00880000;
	167	io->iop_psorb \|= 0x00880000;
	168	io->iop_pdirb &= ~0x00030000;
	169	io->iop_psorb &= ~0x00030000;
a1604f91	170	#endif
fc8e50e3 VB	171	cpmux->cmx_scr &= 0xff00ffff;
fc8e50e3 VB	172	cpmux->cmx_scr \|= 0x00090000;
1da177e4	173	pinfo->brg = 2;
fc8e50e3 VB	174
	175	cpm2_unmap(cpmux);
	176	cpm2_unmap(io);
1da177e4 LT	177	}
	178
	179	void scc3_lineif(struct uart_cpm_port *pinfo)
	180	{
fc8e50e3 VB	181	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
	182	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
	183
1da177e4 LT	184	io->iop_pparb \|= 0x008b0000;
	185	io->iop_pdirb \|= 0x00880000;
	186	io->iop_psorb \|= 0x00880000;
	187	io->iop_pdirb &= ~0x00030000;
	188	io->iop_psorb &= ~0x00030000;
fc8e50e3 VB	189	cpmux->cmx_scr &= 0xffff00ff;
fc8e50e3 VB	190	cpmux->cmx_scr \|= 0x00001200;
1da177e4	191	pinfo->brg = 3;
fc8e50e3 VB	192
	193	cpm2_unmap(cpmux);
	194	cpm2_unmap(io);
1da177e4 LT	195	}
	196
	197	void scc4_lineif(struct uart_cpm_port *pinfo)
	198	{
fc8e50e3 VB	199	volatile iop_cpm2_t *io = cpm2_map(im_ioport);
fc8e50e3 VB	200	volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
1da177e4 LT	201
	202	io->iop_ppard \|= 0x00000600;
	203	io->iop_psord &= ~0x00000600; /* Tx/Rx */
	204	io->iop_pdird &= ~0x00000200; /* Rx */
	205	io->iop_pdird \|= 0x00000400; /* Tx */
	206
fc8e50e3 VB	207	cpmux->cmx_scr &= 0xffffff00;
fc8e50e3 VB	208	cpmux->cmx_scr \|= 0x0000001b;
1da177e4	209	pinfo->brg = 4;
fc8e50e3 VB	210
	211	cpm2_unmap(cpmux);
	212	cpm2_unmap(io);
1da177e4 LT	213	}
	214
	215	/*
	216	* Allocate DP-Ram and memory buffers. We need to allocate a transmit and
	217	* receive buffer descriptors from dual port ram, and a character
	218	* buffer area from host mem. If we are allocating for the console we need
	219	* to do it from bootmem
	220	*/
	221	int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
	222	{
	223	int dpmemsz, memsz;
	224	u8 *dp_mem;
	225	uint dp_offset;
	226	u8 *mem_addr;
	227	dma_addr_t dma_addr = 0;
	228
	229	pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
	230
	231	dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
	232	dp_offset = cpm_dpalloc(dpmemsz, 8);
	233	if (IS_DPERR(dp_offset)) {
	234	printk(KERN_ERR
	235	"cpm_uart_cpm.c: could not allocate buffer descriptors\n");
	236	return -ENOMEM;
	237	}
	238
	239	dp_mem = cpm_dpram_addr(dp_offset);
	240
	241	memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
	242	L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
09b03b6c	243	if (is_con) {
1da177e4	244	mem_addr = alloc_bootmem(memsz);
8e30a9a2	245	dma_addr = virt_to_bus(mem_addr);
09b03b6c	246	}
1da177e4 LT	247	else
	248	mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
	249	GFP_KERNEL);
	250
	251	if (mem_addr == NULL) {
	252	cpm_dpfree(dp_offset);
	253	printk(KERN_ERR
	254	"cpm_uart_cpm.c: could not allocate coherent memory\n");
	255	return -ENOMEM;
	256	}
	257
	258	pinfo->dp_addr = dp_offset;
	259	pinfo->mem_addr = mem_addr;
	260	pinfo->dma_addr = dma_addr;
09b03b6c	261	pinfo->mem_size = memsz;
1da177e4 LT	262
	263	pinfo->rx_buf = mem_addr;
	264	pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
	265	* pinfo->rx_fifosize);
	266
	267	pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
	268	pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
	269
	270	return 0;
	271	}
	272
	273	void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
	274	{
	275	dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
	276	pinfo->rx_fifosize) +
	277	L1_CACHE_ALIGN(pinfo->tx_nrfifos *
	278	pinfo->tx_fifosize), pinfo->mem_addr,
	279	pinfo->dma_addr);
	280
	281	cpm_dpfree(pinfo->dp_addr);
	282	}
	283
	284	/* Setup any dynamic params in the uart desc */
533462df	285	int __init cpm_uart_init_portdesc(void)
1da177e4	286	{
fc8e50e3 VB	287	#if defined(CONFIG_SERIAL_CPM_SMC1) \|\| defined(CONFIG_SERIAL_CPM_SMC2)
	288	u32 addr;
	289	#endif
1da177e4 LT	290	pr_debug("CPM uart[-]:init portdesc\n");
	291
	292	cpm_uart_nr = 0;
	293	#ifdef CONFIG_SERIAL_CPM_SMC1
fc8e50e3	294	cpm_uart_ports[UART_SMC1].smcp = (smc_t *) cpm2_map(im_smc[0]);
1da177e4	295	cpm_uart_ports[UART_SMC1].port.mapbase =
fc8e50e3 VB	296	(unsigned long)cpm_uart_ports[UART_SMC1].smcp;
	297
	298	cpm_uart_ports[UART_SMC1].smcup =
	299	(smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC1], PROFF_SMC_SIZE);
	300	addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC1_BASE], 2);
	301	*addr = PROFF_SMC1;
	302	cpm2_unmap(addr);
	303
1da177e4 LT	304	cpm_uart_ports[UART_SMC1].smcp->smc_smcm \|= (SMCM_RX \| SMCM_TX);
1da177e4 LT	305	cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN \| SMCMR_TEN);
3dd0dcbe	306	cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
1da177e4 LT	307	cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
	308	#endif
	309
	310	#ifdef CONFIG_SERIAL_CPM_SMC2
fc8e50e3	311	cpm_uart_ports[UART_SMC2].smcp = (smc_t *) cpm2_map(im_smc[1]);
1da177e4	312	cpm_uart_ports[UART_SMC2].port.mapbase =
fc8e50e3 VB	313	(unsigned long)cpm_uart_ports[UART_SMC2].smcp;
	314
	315	cpm_uart_ports[UART_SMC2].smcup =
	316	(smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC2], PROFF_SMC_SIZE);
	317	addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC2_BASE], 2);
	318	*addr = PROFF_SMC2;
	319	cpm2_unmap(addr);
	320
1da177e4 LT	321	cpm_uart_ports[UART_SMC2].smcp->smc_smcm \|= (SMCM_RX \| SMCM_TX);
1da177e4 LT	322	cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN \| SMCMR_TEN);
3dd0dcbe	323	cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
1da177e4 LT	324	cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
	325	#endif
	326
	327	#ifdef CONFIG_SERIAL_CPM_SCC1
fc8e50e3	328	cpm_uart_ports[UART_SCC1].sccp = (scc_t *) cpm2_map(im_scc[0]);
1da177e4	329	cpm_uart_ports[UART_SCC1].port.mapbase =
fc8e50e3 VB	330	(unsigned long)cpm_uart_ports[UART_SCC1].sccp;
	331	cpm_uart_ports[UART_SCC1].sccup =
	332	(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC1], PROFF_SCC_SIZE);
	333
1da177e4 LT	334	cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
	335	~(UART_SCCM_TX \| UART_SCCM_RX);
	336	cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
	337	~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
3dd0dcbe	338	cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
1da177e4 LT	339	cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
	340	#endif
	341
	342	#ifdef CONFIG_SERIAL_CPM_SCC2
fc8e50e3	343	cpm_uart_ports[UART_SCC2].sccp = (scc_t *) cpm2_map(im_scc[1]);
1da177e4	344	cpm_uart_ports[UART_SCC2].port.mapbase =
fc8e50e3 VB	345	(unsigned long)cpm_uart_ports[UART_SCC2].sccp;
	346	cpm_uart_ports[UART_SCC2].sccup =
	347	(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC2], PROFF_SCC_SIZE);
	348
1da177e4 LT	349	cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
	350	~(UART_SCCM_TX \| UART_SCCM_RX);
	351	cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
	352	~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
3dd0dcbe	353	cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
1da177e4 LT	354	cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
	355	#endif
	356
	357	#ifdef CONFIG_SERIAL_CPM_SCC3
fc8e50e3	358	cpm_uart_ports[UART_SCC3].sccp = (scc_t *) cpm2_map(im_scc[2]);
1da177e4	359	cpm_uart_ports[UART_SCC3].port.mapbase =
fc8e50e3 VB	360	(unsigned long)cpm_uart_ports[UART_SCC3].sccp;
	361	cpm_uart_ports[UART_SCC3].sccup =
	362	(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC3], PROFF_SCC_SIZE);
	363
1da177e4 LT	364	cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
	365	~(UART_SCCM_TX \| UART_SCCM_RX);
	366	cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
	367	~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
3dd0dcbe	368	cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
1da177e4 LT	369	cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
	370	#endif
	371
	372	#ifdef CONFIG_SERIAL_CPM_SCC4
fc8e50e3	373	cpm_uart_ports[UART_SCC4].sccp = (scc_t *) cpm2_map(im_scc[3]);
1da177e4	374	cpm_uart_ports[UART_SCC4].port.mapbase =
fc8e50e3 VB	375	(unsigned long)cpm_uart_ports[UART_SCC4].sccp;
	376	cpm_uart_ports[UART_SCC4].sccup =
	377	(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC4], PROFF_SCC_SIZE);
	378
1da177e4 LT	379	cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
	380	~(UART_SCCM_TX \| UART_SCCM_RX);
	381	cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
	382	~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
3dd0dcbe	383	cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
1da177e4 LT	384	cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
	385	#endif
	386
	387	return 0;
	388	}