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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/cpm_uart_cpm2.c | |
3 | * | |
4 | * Driver for CPM (SCC/SMC) serial ports; CPM2 definitions | |
5 | * | |
6 | * Maintainer: Kumar Gala (kumar.gala@freescale.com) (CPM2) | |
7 | * Pantelis Antoniou (panto@intracom.gr) (CPM1) | |
8 | * | |
9 | * Copyright (C) 2004 Freescale Semiconductor, Inc. | |
10 | * (C) 2004 Intracom, S.A. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/config.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/tty.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/serial.h> | |
34 | #include <linux/console.h> | |
35 | #include <linux/sysrq.h> | |
36 | #include <linux/device.h> | |
37 | #include <linux/bootmem.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | ||
40 | #include <asm/io.h> | |
41 | #include <asm/irq.h> | |
42 | ||
43 | #include <linux/serial_core.h> | |
44 | #include <linux/kernel.h> | |
45 | ||
46 | #include "cpm_uart.h" | |
47 | ||
48 | /**************************************************************/ | |
49 | ||
50 | void cpm_line_cr_cmd(int line, int cmd) | |
51 | { | |
52 | volatile cpm_cpm2_t *cp = cpmp; | |
53 | ulong val; | |
54 | ||
55 | switch (line) { | |
56 | case UART_SMC1: | |
57 | val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0, | |
58 | cmd) | CPM_CR_FLG; | |
59 | break; | |
60 | case UART_SMC2: | |
61 | val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0, | |
62 | cmd) | CPM_CR_FLG; | |
63 | break; | |
64 | case UART_SCC1: | |
65 | val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0, | |
66 | cmd) | CPM_CR_FLG; | |
67 | break; | |
68 | case UART_SCC2: | |
69 | val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0, | |
70 | cmd) | CPM_CR_FLG; | |
71 | break; | |
72 | case UART_SCC3: | |
73 | val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0, | |
74 | cmd) | CPM_CR_FLG; | |
75 | break; | |
76 | case UART_SCC4: | |
77 | val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0, | |
78 | cmd) | CPM_CR_FLG; | |
79 | break; | |
80 | default: | |
81 | return; | |
82 | ||
83 | } | |
84 | cp->cp_cpcr = val; | |
85 | while (cp->cp_cpcr & CPM_CR_FLG) ; | |
86 | } | |
87 | ||
88 | void smc1_lineif(struct uart_cpm_port *pinfo) | |
89 | { | |
90 | volatile iop_cpm2_t *io = &cpm2_immr->im_ioport; | |
91 | ||
92 | /* SMC1 is only on port D */ | |
93 | io->iop_ppard |= 0x00c00000; | |
94 | io->iop_pdird |= 0x00400000; | |
95 | io->iop_pdird &= ~0x00800000; | |
96 | io->iop_psord &= ~0x00c00000; | |
97 | ||
98 | /* Wire BRG1 to SMC1 */ | |
99 | cpm2_immr->im_cpmux.cmx_smr &= 0x0f; | |
100 | pinfo->brg = 1; | |
101 | } | |
102 | ||
103 | void smc2_lineif(struct uart_cpm_port *pinfo) | |
104 | { | |
105 | volatile iop_cpm2_t *io = &cpm2_immr->im_ioport; | |
106 | ||
107 | /* SMC2 is only on port A */ | |
108 | io->iop_ppara |= 0x00c00000; | |
109 | io->iop_pdira |= 0x00400000; | |
110 | io->iop_pdira &= ~0x00800000; | |
111 | io->iop_psora &= ~0x00c00000; | |
112 | ||
113 | /* Wire BRG2 to SMC2 */ | |
114 | cpm2_immr->im_cpmux.cmx_smr &= 0xf0; | |
115 | pinfo->brg = 2; | |
116 | } | |
117 | ||
118 | void scc1_lineif(struct uart_cpm_port *pinfo) | |
119 | { | |
120 | volatile iop_cpm2_t *io = &cpm2_immr->im_ioport; | |
121 | ||
122 | /* Use Port D for SCC1 instead of other functions. */ | |
123 | io->iop_ppard |= 0x00000003; | |
124 | io->iop_psord &= ~0x00000001; /* Rx */ | |
125 | io->iop_psord |= 0x00000002; /* Tx */ | |
126 | io->iop_pdird &= ~0x00000001; /* Rx */ | |
127 | io->iop_pdird |= 0x00000002; /* Tx */ | |
128 | ||
129 | /* Wire BRG1 to SCC1 */ | |
130 | cpm2_immr->im_cpmux.cmx_scr &= 0x00ffffff; | |
131 | cpm2_immr->im_cpmux.cmx_scr |= 0x00000000; | |
132 | pinfo->brg = 1; | |
133 | } | |
134 | ||
135 | void scc2_lineif(struct uart_cpm_port *pinfo) | |
136 | { | |
a1604f91 MP |
137 | /* |
138 | * STx GP3 uses the SCC2 secondary option pin assignment | |
139 | * which this driver doesn't account for in the static | |
140 | * pin assignments. This kind of board specific info | |
141 | * really has to get out of the driver so boards can | |
142 | * be supported in a sane fashion. | |
143 | */ | |
144 | #ifndef CONFIG_STX_GP3 | |
0d8ba1a9 KG |
145 | #ifdef CONFIG_MPC8560_ADS |
146 | volatile iop_cpm2_t *io = &cpm2_immr->im_ioport; | |
147 | io->iop_ppard |= 0x00000018; | |
148 | io->iop_psord &= ~0x00000008; /* Rx */ | |
149 | io->iop_psord &= ~0x00000010; /* Tx */ | |
150 | io->iop_pdird &= ~0x00000008; /* Rx */ | |
151 | io->iop_pdird |= 0x00000010; /* Tx */ | |
152 | #else | |
1da177e4 LT |
153 | volatile iop_cpm2_t *io = &cpm2_immr->im_ioport; |
154 | io->iop_pparb |= 0x008b0000; | |
155 | io->iop_pdirb |= 0x00880000; | |
156 | io->iop_psorb |= 0x00880000; | |
157 | io->iop_pdirb &= ~0x00030000; | |
158 | io->iop_psorb &= ~0x00030000; | |
0d8ba1a9 | 159 | #endif |
a1604f91 | 160 | #endif |
1da177e4 LT |
161 | cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff; |
162 | cpm2_immr->im_cpmux.cmx_scr |= 0x00090000; | |
163 | pinfo->brg = 2; | |
164 | } | |
165 | ||
166 | void scc3_lineif(struct uart_cpm_port *pinfo) | |
167 | { | |
168 | volatile iop_cpm2_t *io = &cpm2_immr->im_ioport; | |
169 | io->iop_pparb |= 0x008b0000; | |
170 | io->iop_pdirb |= 0x00880000; | |
171 | io->iop_psorb |= 0x00880000; | |
172 | io->iop_pdirb &= ~0x00030000; | |
173 | io->iop_psorb &= ~0x00030000; | |
174 | cpm2_immr->im_cpmux.cmx_scr &= 0xffff00ff; | |
175 | cpm2_immr->im_cpmux.cmx_scr |= 0x00001200; | |
176 | pinfo->brg = 3; | |
177 | } | |
178 | ||
179 | void scc4_lineif(struct uart_cpm_port *pinfo) | |
180 | { | |
181 | volatile iop_cpm2_t *io = &cpm2_immr->im_ioport; | |
182 | ||
183 | io->iop_ppard |= 0x00000600; | |
184 | io->iop_psord &= ~0x00000600; /* Tx/Rx */ | |
185 | io->iop_pdird &= ~0x00000200; /* Rx */ | |
186 | io->iop_pdird |= 0x00000400; /* Tx */ | |
187 | ||
188 | cpm2_immr->im_cpmux.cmx_scr &= 0xffffff00; | |
189 | cpm2_immr->im_cpmux.cmx_scr |= 0x0000001b; | |
190 | pinfo->brg = 4; | |
191 | } | |
192 | ||
193 | /* | |
194 | * Allocate DP-Ram and memory buffers. We need to allocate a transmit and | |
195 | * receive buffer descriptors from dual port ram, and a character | |
196 | * buffer area from host mem. If we are allocating for the console we need | |
197 | * to do it from bootmem | |
198 | */ | |
199 | int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con) | |
200 | { | |
201 | int dpmemsz, memsz; | |
202 | u8 *dp_mem; | |
203 | uint dp_offset; | |
204 | u8 *mem_addr; | |
205 | dma_addr_t dma_addr = 0; | |
206 | ||
207 | pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line); | |
208 | ||
209 | dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos); | |
210 | dp_offset = cpm_dpalloc(dpmemsz, 8); | |
211 | if (IS_DPERR(dp_offset)) { | |
212 | printk(KERN_ERR | |
213 | "cpm_uart_cpm.c: could not allocate buffer descriptors\n"); | |
214 | return -ENOMEM; | |
215 | } | |
216 | ||
217 | dp_mem = cpm_dpram_addr(dp_offset); | |
218 | ||
219 | memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) + | |
220 | L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize); | |
221 | if (is_con) | |
222 | mem_addr = alloc_bootmem(memsz); | |
223 | else | |
224 | mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr, | |
225 | GFP_KERNEL); | |
226 | ||
227 | if (mem_addr == NULL) { | |
228 | cpm_dpfree(dp_offset); | |
229 | printk(KERN_ERR | |
230 | "cpm_uart_cpm.c: could not allocate coherent memory\n"); | |
231 | return -ENOMEM; | |
232 | } | |
233 | ||
234 | pinfo->dp_addr = dp_offset; | |
235 | pinfo->mem_addr = mem_addr; | |
236 | pinfo->dma_addr = dma_addr; | |
237 | ||
238 | pinfo->rx_buf = mem_addr; | |
239 | pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos | |
240 | * pinfo->rx_fifosize); | |
241 | ||
242 | pinfo->rx_bd_base = (volatile cbd_t *)dp_mem; | |
243 | pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos; | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | void cpm_uart_freebuf(struct uart_cpm_port *pinfo) | |
249 | { | |
250 | dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos * | |
251 | pinfo->rx_fifosize) + | |
252 | L1_CACHE_ALIGN(pinfo->tx_nrfifos * | |
253 | pinfo->tx_fifosize), pinfo->mem_addr, | |
254 | pinfo->dma_addr); | |
255 | ||
256 | cpm_dpfree(pinfo->dp_addr); | |
257 | } | |
258 | ||
259 | /* Setup any dynamic params in the uart desc */ | |
260 | int cpm_uart_init_portdesc(void) | |
261 | { | |
262 | pr_debug("CPM uart[-]:init portdesc\n"); | |
263 | ||
264 | cpm_uart_nr = 0; | |
265 | #ifdef CONFIG_SERIAL_CPM_SMC1 | |
266 | cpm_uart_ports[UART_SMC1].smcp = (smc_t *) & cpm2_immr->im_smc[0]; | |
267 | cpm_uart_ports[UART_SMC1].smcup = | |
268 | (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC1]; | |
b0531b9b | 269 | *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1; |
1da177e4 LT |
270 | cpm_uart_ports[UART_SMC1].port.mapbase = |
271 | (unsigned long)&cpm2_immr->im_smc[0]; | |
272 | cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX); | |
273 | cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); | |
274 | cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
275 | cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1; | |
276 | #endif | |
277 | ||
278 | #ifdef CONFIG_SERIAL_CPM_SMC2 | |
279 | cpm_uart_ports[UART_SMC2].smcp = (smc_t *) & cpm2_immr->im_smc[1]; | |
280 | cpm_uart_ports[UART_SMC2].smcup = | |
281 | (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC2]; | |
b0531b9b | 282 | *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC2_BASE]) = PROFF_SMC2; |
1da177e4 LT |
283 | cpm_uart_ports[UART_SMC2].port.mapbase = |
284 | (unsigned long)&cpm2_immr->im_smc[1]; | |
285 | cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX); | |
286 | cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); | |
287 | cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
288 | cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2; | |
289 | #endif | |
290 | ||
291 | #ifdef CONFIG_SERIAL_CPM_SCC1 | |
292 | cpm_uart_ports[UART_SCC1].sccp = (scc_t *) & cpm2_immr->im_scc[0]; | |
293 | cpm_uart_ports[UART_SCC1].sccup = | |
294 | (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC1]; | |
295 | cpm_uart_ports[UART_SCC1].port.mapbase = | |
296 | (unsigned long)&cpm2_immr->im_scc[0]; | |
297 | cpm_uart_ports[UART_SCC1].sccp->scc_sccm &= | |
298 | ~(UART_SCCM_TX | UART_SCCM_RX); | |
299 | cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &= | |
300 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
301 | cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
302 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1; | |
303 | #endif | |
304 | ||
305 | #ifdef CONFIG_SERIAL_CPM_SCC2 | |
306 | cpm_uart_ports[UART_SCC2].sccp = (scc_t *) & cpm2_immr->im_scc[1]; | |
307 | cpm_uart_ports[UART_SCC2].sccup = | |
308 | (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC2]; | |
309 | cpm_uart_ports[UART_SCC2].port.mapbase = | |
310 | (unsigned long)&cpm2_immr->im_scc[1]; | |
311 | cpm_uart_ports[UART_SCC2].sccp->scc_sccm &= | |
312 | ~(UART_SCCM_TX | UART_SCCM_RX); | |
313 | cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &= | |
314 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
315 | cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
316 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2; | |
317 | #endif | |
318 | ||
319 | #ifdef CONFIG_SERIAL_CPM_SCC3 | |
320 | cpm_uart_ports[UART_SCC3].sccp = (scc_t *) & cpm2_immr->im_scc[2]; | |
321 | cpm_uart_ports[UART_SCC3].sccup = | |
322 | (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC3]; | |
323 | cpm_uart_ports[UART_SCC3].port.mapbase = | |
324 | (unsigned long)&cpm2_immr->im_scc[2]; | |
325 | cpm_uart_ports[UART_SCC3].sccp->scc_sccm &= | |
326 | ~(UART_SCCM_TX | UART_SCCM_RX); | |
327 | cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &= | |
328 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
329 | cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
330 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3; | |
331 | #endif | |
332 | ||
333 | #ifdef CONFIG_SERIAL_CPM_SCC4 | |
334 | cpm_uart_ports[UART_SCC4].sccp = (scc_t *) & cpm2_immr->im_scc[3]; | |
335 | cpm_uart_ports[UART_SCC4].sccup = | |
336 | (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC4]; | |
337 | cpm_uart_ports[UART_SCC4].port.mapbase = | |
338 | (unsigned long)&cpm2_immr->im_scc[3]; | |
339 | cpm_uart_ports[UART_SCC4].sccp->scc_sccm &= | |
340 | ~(UART_SCCM_TX | UART_SCCM_RX); | |
341 | cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &= | |
342 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
343 | cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
344 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4; | |
345 | #endif | |
346 | ||
347 | return 0; | |
348 | } |