Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/pxa.c | |
3 | * | |
4 | * Based on drivers/serial/8250.c by Russell King. | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Feb 20, 2003 | |
8 | * Copyright: (C) 2003 Monta Vista Software, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * Note 1: This driver is made separate from the already too overloaded | |
16 | * 8250.c because it needs some kirks of its own and that'll make it | |
17 | * easier to add DMA support. | |
18 | * | |
19 | * Note 2: I'm too sick of device allocation policies for serial ports. | |
20 | * If someone else wants to request an "official" allocation of major/minor | |
21 | * for this driver please be my guest. And don't forget that new hardware | |
22 | * to come from Intel might have more than 3 or 4 of those UARTs. Let's | |
23 | * hope for a better port registration and dynamic device allocation scheme | |
24 | * with the serial core maintainer satisfaction to appear soon. | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | |
28 | #if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
29 | #define SUPPORT_SYSRQ | |
30 | #endif | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/console.h> | |
36 | #include <linux/sysrq.h> | |
37 | #include <linux/serial_reg.h> | |
38 | #include <linux/circ_buf.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
d052d1be | 41 | #include <linux/platform_device.h> |
1da177e4 LT |
42 | #include <linux/tty.h> |
43 | #include <linux/tty_flip.h> | |
44 | #include <linux/serial_core.h> | |
45 | ||
46 | #include <asm/io.h> | |
47 | #include <asm/hardware.h> | |
48 | #include <asm/irq.h> | |
49 | #include <asm/arch/pxa-regs.h> | |
50 | ||
51 | ||
52 | struct uart_pxa_port { | |
53 | struct uart_port port; | |
54 | unsigned char ier; | |
55 | unsigned char lcr; | |
56 | unsigned char mcr; | |
57 | unsigned int lsr_break_flag; | |
58 | unsigned int cken; | |
59 | char *name; | |
60 | }; | |
61 | ||
62 | static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) | |
63 | { | |
64 | offset <<= 2; | |
65 | return readl(up->port.membase + offset); | |
66 | } | |
67 | ||
68 | static inline void serial_out(struct uart_pxa_port *up, int offset, int value) | |
69 | { | |
70 | offset <<= 2; | |
71 | writel(value, up->port.membase + offset); | |
72 | } | |
73 | ||
74 | static void serial_pxa_enable_ms(struct uart_port *port) | |
75 | { | |
76 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
77 | ||
78 | up->ier |= UART_IER_MSI; | |
79 | serial_out(up, UART_IER, up->ier); | |
80 | } | |
81 | ||
b129a8cc | 82 | static void serial_pxa_stop_tx(struct uart_port *port) |
1da177e4 LT |
83 | { |
84 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
85 | ||
86 | if (up->ier & UART_IER_THRI) { | |
87 | up->ier &= ~UART_IER_THRI; | |
88 | serial_out(up, UART_IER, up->ier); | |
89 | } | |
90 | } | |
91 | ||
92 | static void serial_pxa_stop_rx(struct uart_port *port) | |
93 | { | |
94 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
95 | ||
96 | up->ier &= ~UART_IER_RLSI; | |
97 | up->port.read_status_mask &= ~UART_LSR_DR; | |
98 | serial_out(up, UART_IER, up->ier); | |
99 | } | |
100 | ||
7d12e780 | 101 | static inline void receive_chars(struct uart_pxa_port *up, int *status) |
1da177e4 LT |
102 | { |
103 | struct tty_struct *tty = up->port.info->tty; | |
104 | unsigned int ch, flag; | |
105 | int max_count = 256; | |
106 | ||
107 | do { | |
1da177e4 LT |
108 | ch = serial_in(up, UART_RX); |
109 | flag = TTY_NORMAL; | |
110 | up->port.icount.rx++; | |
111 | ||
112 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
113 | UART_LSR_FE | UART_LSR_OE))) { | |
114 | /* | |
115 | * For statistics only | |
116 | */ | |
117 | if (*status & UART_LSR_BI) { | |
118 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
119 | up->port.icount.brk++; | |
120 | /* | |
121 | * We do the SysRQ and SAK checking | |
122 | * here because otherwise the break | |
123 | * may get masked by ignore_status_mask | |
124 | * or read_status_mask. | |
125 | */ | |
126 | if (uart_handle_break(&up->port)) | |
127 | goto ignore_char; | |
128 | } else if (*status & UART_LSR_PE) | |
129 | up->port.icount.parity++; | |
130 | else if (*status & UART_LSR_FE) | |
131 | up->port.icount.frame++; | |
132 | if (*status & UART_LSR_OE) | |
133 | up->port.icount.overrun++; | |
134 | ||
135 | /* | |
136 | * Mask off conditions which should be ignored. | |
137 | */ | |
138 | *status &= up->port.read_status_mask; | |
139 | ||
140 | #ifdef CONFIG_SERIAL_PXA_CONSOLE | |
141 | if (up->port.line == up->port.cons->index) { | |
142 | /* Recover the break flag from console xmit */ | |
143 | *status |= up->lsr_break_flag; | |
144 | up->lsr_break_flag = 0; | |
145 | } | |
146 | #endif | |
147 | if (*status & UART_LSR_BI) { | |
148 | flag = TTY_BREAK; | |
149 | } else if (*status & UART_LSR_PE) | |
150 | flag = TTY_PARITY; | |
151 | else if (*status & UART_LSR_FE) | |
152 | flag = TTY_FRAME; | |
153 | } | |
05ab3014 | 154 | |
7d12e780 | 155 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 156 | goto ignore_char; |
05ab3014 RK |
157 | |
158 | uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); | |
159 | ||
1da177e4 LT |
160 | ignore_char: |
161 | *status = serial_in(up, UART_LSR); | |
162 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
163 | tty_flip_buffer_push(tty); | |
164 | } | |
165 | ||
166 | static void transmit_chars(struct uart_pxa_port *up) | |
167 | { | |
168 | struct circ_buf *xmit = &up->port.info->xmit; | |
169 | int count; | |
170 | ||
171 | if (up->port.x_char) { | |
172 | serial_out(up, UART_TX, up->port.x_char); | |
173 | up->port.icount.tx++; | |
174 | up->port.x_char = 0; | |
175 | return; | |
176 | } | |
177 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
b129a8cc | 178 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
179 | return; |
180 | } | |
181 | ||
182 | count = up->port.fifosize / 2; | |
183 | do { | |
184 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
185 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
186 | up->port.icount.tx++; | |
187 | if (uart_circ_empty(xmit)) | |
188 | break; | |
189 | } while (--count > 0); | |
190 | ||
191 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
192 | uart_write_wakeup(&up->port); | |
193 | ||
194 | ||
195 | if (uart_circ_empty(xmit)) | |
b129a8cc | 196 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
197 | } |
198 | ||
b129a8cc | 199 | static void serial_pxa_start_tx(struct uart_port *port) |
1da177e4 LT |
200 | { |
201 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
202 | ||
203 | if (!(up->ier & UART_IER_THRI)) { | |
204 | up->ier |= UART_IER_THRI; | |
205 | serial_out(up, UART_IER, up->ier); | |
206 | } | |
207 | } | |
208 | ||
209 | static inline void check_modem_status(struct uart_pxa_port *up) | |
210 | { | |
211 | int status; | |
212 | ||
213 | status = serial_in(up, UART_MSR); | |
214 | ||
215 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
216 | return; | |
217 | ||
218 | if (status & UART_MSR_TERI) | |
219 | up->port.icount.rng++; | |
220 | if (status & UART_MSR_DDSR) | |
221 | up->port.icount.dsr++; | |
222 | if (status & UART_MSR_DDCD) | |
223 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
224 | if (status & UART_MSR_DCTS) | |
225 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
226 | ||
227 | wake_up_interruptible(&up->port.info->delta_msr_wait); | |
228 | } | |
229 | ||
230 | /* | |
231 | * This handles the interrupt from one port. | |
232 | */ | |
7d12e780 | 233 | static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) |
1da177e4 | 234 | { |
c7bec5ab | 235 | struct uart_pxa_port *up = dev_id; |
1da177e4 LT |
236 | unsigned int iir, lsr; |
237 | ||
238 | iir = serial_in(up, UART_IIR); | |
239 | if (iir & UART_IIR_NO_INT) | |
240 | return IRQ_NONE; | |
241 | lsr = serial_in(up, UART_LSR); | |
242 | if (lsr & UART_LSR_DR) | |
7d12e780 | 243 | receive_chars(up, &lsr); |
1da177e4 LT |
244 | check_modem_status(up); |
245 | if (lsr & UART_LSR_THRE) | |
246 | transmit_chars(up); | |
247 | return IRQ_HANDLED; | |
248 | } | |
249 | ||
250 | static unsigned int serial_pxa_tx_empty(struct uart_port *port) | |
251 | { | |
252 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
253 | unsigned long flags; | |
254 | unsigned int ret; | |
255 | ||
256 | spin_lock_irqsave(&up->port.lock, flags); | |
257 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
258 | spin_unlock_irqrestore(&up->port.lock, flags); | |
259 | ||
260 | return ret; | |
261 | } | |
262 | ||
263 | static unsigned int serial_pxa_get_mctrl(struct uart_port *port) | |
264 | { | |
265 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
1da177e4 LT |
266 | unsigned char status; |
267 | unsigned int ret; | |
268 | ||
1da177e4 | 269 | status = serial_in(up, UART_MSR); |
1da177e4 LT |
270 | |
271 | ret = 0; | |
272 | if (status & UART_MSR_DCD) | |
273 | ret |= TIOCM_CAR; | |
274 | if (status & UART_MSR_RI) | |
275 | ret |= TIOCM_RNG; | |
276 | if (status & UART_MSR_DSR) | |
277 | ret |= TIOCM_DSR; | |
278 | if (status & UART_MSR_CTS) | |
279 | ret |= TIOCM_CTS; | |
280 | return ret; | |
281 | } | |
282 | ||
283 | static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
284 | { | |
285 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
286 | unsigned char mcr = 0; | |
287 | ||
288 | if (mctrl & TIOCM_RTS) | |
289 | mcr |= UART_MCR_RTS; | |
290 | if (mctrl & TIOCM_DTR) | |
291 | mcr |= UART_MCR_DTR; | |
292 | if (mctrl & TIOCM_OUT1) | |
293 | mcr |= UART_MCR_OUT1; | |
294 | if (mctrl & TIOCM_OUT2) | |
295 | mcr |= UART_MCR_OUT2; | |
296 | if (mctrl & TIOCM_LOOP) | |
297 | mcr |= UART_MCR_LOOP; | |
298 | ||
299 | mcr |= up->mcr; | |
300 | ||
301 | serial_out(up, UART_MCR, mcr); | |
302 | } | |
303 | ||
304 | static void serial_pxa_break_ctl(struct uart_port *port, int break_state) | |
305 | { | |
306 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
307 | unsigned long flags; | |
308 | ||
309 | spin_lock_irqsave(&up->port.lock, flags); | |
310 | if (break_state == -1) | |
311 | up->lcr |= UART_LCR_SBC; | |
312 | else | |
313 | up->lcr &= ~UART_LCR_SBC; | |
314 | serial_out(up, UART_LCR, up->lcr); | |
315 | spin_unlock_irqrestore(&up->port.lock, flags); | |
316 | } | |
317 | ||
318 | #if 0 | |
319 | static void serial_pxa_dma_init(struct pxa_uart *up) | |
320 | { | |
321 | up->rxdma = | |
322 | pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up); | |
323 | if (up->rxdma < 0) | |
324 | goto out; | |
325 | up->txdma = | |
326 | pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up); | |
327 | if (up->txdma < 0) | |
328 | goto err_txdma; | |
329 | up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL); | |
330 | if (!up->dmadesc) | |
331 | goto err_alloc; | |
332 | ||
333 | /* ... */ | |
334 | err_alloc: | |
335 | pxa_free_dma(up->txdma); | |
336 | err_rxdma: | |
337 | pxa_free_dma(up->rxdma); | |
338 | out: | |
339 | return; | |
340 | } | |
341 | #endif | |
342 | ||
343 | static int serial_pxa_startup(struct uart_port *port) | |
344 | { | |
345 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
346 | unsigned long flags; | |
347 | int retval; | |
348 | ||
d9e29649 MR |
349 | if (port->line == 3) /* HWUART */ |
350 | up->mcr |= UART_MCR_AFE; | |
351 | else | |
f02aa3f9 | 352 | up->mcr = 0; |
1da177e4 LT |
353 | |
354 | /* | |
355 | * Allocate the IRQ | |
356 | */ | |
357 | retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); | |
358 | if (retval) | |
359 | return retval; | |
360 | ||
361 | /* | |
362 | * Clear the FIFO buffers and disable them. | |
363 | * (they will be reenabled in set_termios()) | |
364 | */ | |
365 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
366 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
367 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
368 | serial_out(up, UART_FCR, 0); | |
369 | ||
370 | /* | |
371 | * Clear the interrupt registers. | |
372 | */ | |
373 | (void) serial_in(up, UART_LSR); | |
374 | (void) serial_in(up, UART_RX); | |
375 | (void) serial_in(up, UART_IIR); | |
376 | (void) serial_in(up, UART_MSR); | |
377 | ||
378 | /* | |
379 | * Now, initialize the UART | |
380 | */ | |
381 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
382 | ||
383 | spin_lock_irqsave(&up->port.lock, flags); | |
384 | up->port.mctrl |= TIOCM_OUT2; | |
385 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
386 | spin_unlock_irqrestore(&up->port.lock, flags); | |
387 | ||
388 | /* | |
389 | * Finally, enable interrupts. Note: Modem status interrupts | |
80f7228b | 390 | * are set via set_termios(), which will be occurring imminently |
1da177e4 LT |
391 | * anyway, so we don't enable them here. |
392 | */ | |
393 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; | |
394 | serial_out(up, UART_IER, up->ier); | |
395 | ||
396 | /* | |
397 | * And clear the interrupt registers again for luck. | |
398 | */ | |
399 | (void) serial_in(up, UART_LSR); | |
400 | (void) serial_in(up, UART_RX); | |
401 | (void) serial_in(up, UART_IIR); | |
402 | (void) serial_in(up, UART_MSR); | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | static void serial_pxa_shutdown(struct uart_port *port) | |
408 | { | |
409 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
410 | unsigned long flags; | |
411 | ||
412 | free_irq(up->port.irq, up); | |
413 | ||
414 | /* | |
415 | * Disable interrupts from this port | |
416 | */ | |
417 | up->ier = 0; | |
418 | serial_out(up, UART_IER, 0); | |
419 | ||
420 | spin_lock_irqsave(&up->port.lock, flags); | |
421 | up->port.mctrl &= ~TIOCM_OUT2; | |
422 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
423 | spin_unlock_irqrestore(&up->port.lock, flags); | |
424 | ||
425 | /* | |
426 | * Disable break condition and FIFOs | |
427 | */ | |
428 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
429 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
430 | UART_FCR_CLEAR_RCVR | | |
431 | UART_FCR_CLEAR_XMIT); | |
432 | serial_out(up, UART_FCR, 0); | |
433 | } | |
434 | ||
435 | static void | |
606d099c AC |
436 | serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, |
437 | struct ktermios *old) | |
1da177e4 LT |
438 | { |
439 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
440 | unsigned char cval, fcr = 0; | |
441 | unsigned long flags; | |
442 | unsigned int baud, quot; | |
443 | ||
444 | switch (termios->c_cflag & CSIZE) { | |
445 | case CS5: | |
0a8b80c5 | 446 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
447 | break; |
448 | case CS6: | |
0a8b80c5 | 449 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
450 | break; |
451 | case CS7: | |
0a8b80c5 | 452 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
453 | break; |
454 | default: | |
455 | case CS8: | |
0a8b80c5 | 456 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
457 | break; |
458 | } | |
459 | ||
460 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 461 | cval |= UART_LCR_STOP; |
1da177e4 LT |
462 | if (termios->c_cflag & PARENB) |
463 | cval |= UART_LCR_PARITY; | |
464 | if (!(termios->c_cflag & PARODD)) | |
465 | cval |= UART_LCR_EPAR; | |
466 | ||
467 | /* | |
468 | * Ask the core to calculate the divisor for us. | |
469 | */ | |
470 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
471 | quot = uart_get_divisor(port, baud); | |
472 | ||
473 | if ((up->port.uartclk / quot) < (2400 * 16)) | |
474 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; | |
d9e29649 | 475 | else if ((up->port.uartclk / quot) < (230400 * 16)) |
1da177e4 | 476 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; |
d9e29649 MR |
477 | else |
478 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; | |
1da177e4 LT |
479 | |
480 | /* | |
481 | * Ok, we're now changing the port state. Do it with | |
482 | * interrupts disabled. | |
483 | */ | |
484 | spin_lock_irqsave(&up->port.lock, flags); | |
485 | ||
486 | /* | |
487 | * Ensure the port will be enabled. | |
488 | * This is required especially for serial console. | |
489 | */ | |
490 | up->ier |= IER_UUE; | |
491 | ||
492 | /* | |
493 | * Update the per-port timeout. | |
494 | */ | |
e6158b4a | 495 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 LT |
496 | |
497 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
498 | if (termios->c_iflag & INPCK) | |
499 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
500 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
501 | up->port.read_status_mask |= UART_LSR_BI; | |
502 | ||
503 | /* | |
504 | * Characters to ignore | |
505 | */ | |
506 | up->port.ignore_status_mask = 0; | |
507 | if (termios->c_iflag & IGNPAR) | |
508 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
509 | if (termios->c_iflag & IGNBRK) { | |
510 | up->port.ignore_status_mask |= UART_LSR_BI; | |
511 | /* | |
512 | * If we're ignoring parity and break indicators, | |
513 | * ignore overruns too (for real raw support). | |
514 | */ | |
515 | if (termios->c_iflag & IGNPAR) | |
516 | up->port.ignore_status_mask |= UART_LSR_OE; | |
517 | } | |
518 | ||
519 | /* | |
520 | * ignore all characters if CREAD is not set | |
521 | */ | |
522 | if ((termios->c_cflag & CREAD) == 0) | |
523 | up->port.ignore_status_mask |= UART_LSR_DR; | |
524 | ||
525 | /* | |
526 | * CTS flow control flag and modem status interrupts | |
527 | */ | |
528 | up->ier &= ~UART_IER_MSI; | |
529 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
530 | up->ier |= UART_IER_MSI; | |
531 | ||
532 | serial_out(up, UART_IER, up->ier); | |
533 | ||
534 | serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ | |
535 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ | |
536 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ | |
537 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | |
538 | up->lcr = cval; /* Save LCR */ | |
539 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
540 | serial_out(up, UART_FCR, fcr); | |
541 | spin_unlock_irqrestore(&up->port.lock, flags); | |
542 | } | |
543 | ||
544 | static void | |
545 | serial_pxa_pm(struct uart_port *port, unsigned int state, | |
546 | unsigned int oldstate) | |
547 | { | |
548 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
549 | pxa_set_cken(up->cken, !state); | |
550 | if (!state) | |
551 | udelay(1); | |
552 | } | |
553 | ||
554 | static void serial_pxa_release_port(struct uart_port *port) | |
555 | { | |
556 | } | |
557 | ||
558 | static int serial_pxa_request_port(struct uart_port *port) | |
559 | { | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static void serial_pxa_config_port(struct uart_port *port, int flags) | |
564 | { | |
565 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
566 | up->port.type = PORT_PXA; | |
567 | } | |
568 | ||
569 | static int | |
570 | serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) | |
571 | { | |
572 | /* we don't want the core code to modify any port params */ | |
573 | return -EINVAL; | |
574 | } | |
575 | ||
576 | static const char * | |
577 | serial_pxa_type(struct uart_port *port) | |
578 | { | |
579 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
580 | return up->name; | |
581 | } | |
582 | ||
583 | #ifdef CONFIG_SERIAL_PXA_CONSOLE | |
584 | ||
2d93486c VS |
585 | static struct uart_pxa_port serial_pxa_ports[]; |
586 | static struct uart_driver serial_pxa_reg; | |
1da177e4 LT |
587 | |
588 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) | |
589 | ||
590 | /* | |
591 | * Wait for transmitter & holding register to empty | |
592 | */ | |
593 | static inline void wait_for_xmitr(struct uart_pxa_port *up) | |
594 | { | |
595 | unsigned int status, tmout = 10000; | |
596 | ||
597 | /* Wait up to 10ms for the character(s) to be sent. */ | |
598 | do { | |
599 | status = serial_in(up, UART_LSR); | |
600 | ||
601 | if (status & UART_LSR_BI) | |
602 | up->lsr_break_flag = UART_LSR_BI; | |
603 | ||
604 | if (--tmout == 0) | |
605 | break; | |
606 | udelay(1); | |
607 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
608 | ||
609 | /* Wait up to 1s for flow control if necessary */ | |
610 | if (up->port.flags & UPF_CONS_FLOW) { | |
611 | tmout = 1000000; | |
612 | while (--tmout && | |
613 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | |
614 | udelay(1); | |
615 | } | |
616 | } | |
617 | ||
d358788f RK |
618 | static void serial_pxa_console_putchar(struct uart_port *port, int ch) |
619 | { | |
620 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
621 | ||
622 | wait_for_xmitr(up); | |
623 | serial_out(up, UART_TX, ch); | |
624 | } | |
625 | ||
1da177e4 LT |
626 | /* |
627 | * Print a string to the serial port trying not to disturb | |
628 | * any possible real use of the port... | |
629 | * | |
630 | * The console_lock must be held when we get here. | |
631 | */ | |
632 | static void | |
633 | serial_pxa_console_write(struct console *co, const char *s, unsigned int count) | |
634 | { | |
635 | struct uart_pxa_port *up = &serial_pxa_ports[co->index]; | |
636 | unsigned int ier; | |
1da177e4 LT |
637 | |
638 | /* | |
f02aa3f9 | 639 | * First save the IER then disable the interrupts |
1da177e4 LT |
640 | */ |
641 | ier = serial_in(up, UART_IER); | |
642 | serial_out(up, UART_IER, UART_IER_UUE); | |
643 | ||
d358788f | 644 | uart_console_write(&up->port, s, count, serial_pxa_console_putchar); |
1da177e4 LT |
645 | |
646 | /* | |
647 | * Finally, wait for transmitter to become empty | |
648 | * and restore the IER | |
649 | */ | |
650 | wait_for_xmitr(up); | |
651 | serial_out(up, UART_IER, ier); | |
652 | } | |
653 | ||
654 | static int __init | |
655 | serial_pxa_console_setup(struct console *co, char *options) | |
656 | { | |
657 | struct uart_pxa_port *up; | |
658 | int baud = 9600; | |
659 | int bits = 8; | |
660 | int parity = 'n'; | |
661 | int flow = 'n'; | |
662 | ||
663 | if (co->index == -1 || co->index >= serial_pxa_reg.nr) | |
664 | co->index = 0; | |
665 | up = &serial_pxa_ports[co->index]; | |
666 | ||
667 | if (options) | |
668 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
669 | ||
670 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
671 | } | |
672 | ||
673 | static struct console serial_pxa_console = { | |
674 | .name = "ttyS", | |
675 | .write = serial_pxa_console_write, | |
676 | .device = uart_console_device, | |
677 | .setup = serial_pxa_console_setup, | |
678 | .flags = CON_PRINTBUFFER, | |
679 | .index = -1, | |
680 | .data = &serial_pxa_reg, | |
681 | }; | |
682 | ||
683 | static int __init | |
684 | serial_pxa_console_init(void) | |
685 | { | |
686 | register_console(&serial_pxa_console); | |
687 | return 0; | |
688 | } | |
689 | ||
690 | console_initcall(serial_pxa_console_init); | |
691 | ||
692 | #define PXA_CONSOLE &serial_pxa_console | |
693 | #else | |
694 | #define PXA_CONSOLE NULL | |
695 | #endif | |
696 | ||
697 | struct uart_ops serial_pxa_pops = { | |
698 | .tx_empty = serial_pxa_tx_empty, | |
699 | .set_mctrl = serial_pxa_set_mctrl, | |
700 | .get_mctrl = serial_pxa_get_mctrl, | |
701 | .stop_tx = serial_pxa_stop_tx, | |
702 | .start_tx = serial_pxa_start_tx, | |
703 | .stop_rx = serial_pxa_stop_rx, | |
704 | .enable_ms = serial_pxa_enable_ms, | |
705 | .break_ctl = serial_pxa_break_ctl, | |
706 | .startup = serial_pxa_startup, | |
707 | .shutdown = serial_pxa_shutdown, | |
708 | .set_termios = serial_pxa_set_termios, | |
709 | .pm = serial_pxa_pm, | |
710 | .type = serial_pxa_type, | |
711 | .release_port = serial_pxa_release_port, | |
712 | .request_port = serial_pxa_request_port, | |
713 | .config_port = serial_pxa_config_port, | |
714 | .verify_port = serial_pxa_verify_port, | |
715 | }; | |
716 | ||
717 | static struct uart_pxa_port serial_pxa_ports[] = { | |
718 | { /* FFUART */ | |
719 | .name = "FFUART", | |
7053acbd | 720 | .cken = CKEN_FFUART, |
1da177e4 LT |
721 | .port = { |
722 | .type = PORT_PXA, | |
723 | .iotype = UPIO_MEM, | |
724 | .membase = (void *)&FFUART, | |
725 | .mapbase = __PREG(FFUART), | |
726 | .irq = IRQ_FFUART, | |
727 | .uartclk = 921600 * 16, | |
728 | .fifosize = 64, | |
729 | .ops = &serial_pxa_pops, | |
730 | .line = 0, | |
731 | }, | |
732 | }, { /* BTUART */ | |
733 | .name = "BTUART", | |
7053acbd | 734 | .cken = CKEN_BTUART, |
1da177e4 LT |
735 | .port = { |
736 | .type = PORT_PXA, | |
737 | .iotype = UPIO_MEM, | |
738 | .membase = (void *)&BTUART, | |
739 | .mapbase = __PREG(BTUART), | |
740 | .irq = IRQ_BTUART, | |
741 | .uartclk = 921600 * 16, | |
742 | .fifosize = 64, | |
743 | .ops = &serial_pxa_pops, | |
744 | .line = 1, | |
745 | }, | |
746 | }, { /* STUART */ | |
747 | .name = "STUART", | |
7053acbd | 748 | .cken = CKEN_STUART, |
1da177e4 LT |
749 | .port = { |
750 | .type = PORT_PXA, | |
751 | .iotype = UPIO_MEM, | |
752 | .membase = (void *)&STUART, | |
753 | .mapbase = __PREG(STUART), | |
754 | .irq = IRQ_STUART, | |
755 | .uartclk = 921600 * 16, | |
756 | .fifosize = 64, | |
757 | .ops = &serial_pxa_pops, | |
758 | .line = 2, | |
759 | }, | |
d9e29649 MR |
760 | }, { /* HWUART */ |
761 | .name = "HWUART", | |
7053acbd | 762 | .cken = CKEN_HWUART, |
d9e29649 MR |
763 | .port = { |
764 | .type = PORT_PXA, | |
765 | .iotype = UPIO_MEM, | |
766 | .membase = (void *)&HWUART, | |
767 | .mapbase = __PREG(HWUART), | |
768 | .irq = IRQ_HWUART, | |
769 | .uartclk = 921600 * 16, | |
770 | .fifosize = 64, | |
771 | .ops = &serial_pxa_pops, | |
772 | .line = 3, | |
773 | }, | |
1da177e4 LT |
774 | } |
775 | }; | |
776 | ||
777 | static struct uart_driver serial_pxa_reg = { | |
778 | .owner = THIS_MODULE, | |
779 | .driver_name = "PXA serial", | |
1da177e4 LT |
780 | .dev_name = "ttyS", |
781 | .major = TTY_MAJOR, | |
782 | .minor = 64, | |
783 | .nr = ARRAY_SIZE(serial_pxa_ports), | |
784 | .cons = PXA_CONSOLE, | |
785 | }; | |
786 | ||
3ae5eaec | 787 | static int serial_pxa_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 788 | { |
3ae5eaec | 789 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 790 | |
9480e307 | 791 | if (sport) |
1da177e4 LT |
792 | uart_suspend_port(&serial_pxa_reg, &sport->port); |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
3ae5eaec | 797 | static int serial_pxa_resume(struct platform_device *dev) |
1da177e4 | 798 | { |
3ae5eaec | 799 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 800 | |
9480e307 | 801 | if (sport) |
1da177e4 LT |
802 | uart_resume_port(&serial_pxa_reg, &sport->port); |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
3ae5eaec | 807 | static int serial_pxa_probe(struct platform_device *dev) |
1da177e4 | 808 | { |
3ae5eaec | 809 | serial_pxa_ports[dev->id].port.dev = &dev->dev; |
1da177e4 | 810 | uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port); |
3ae5eaec | 811 | platform_set_drvdata(dev, &serial_pxa_ports[dev->id]); |
1da177e4 LT |
812 | return 0; |
813 | } | |
814 | ||
3ae5eaec | 815 | static int serial_pxa_remove(struct platform_device *dev) |
1da177e4 | 816 | { |
3ae5eaec | 817 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 818 | |
3ae5eaec | 819 | platform_set_drvdata(dev, NULL); |
1da177e4 LT |
820 | |
821 | if (sport) | |
822 | uart_remove_one_port(&serial_pxa_reg, &sport->port); | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
3ae5eaec | 827 | static struct platform_driver serial_pxa_driver = { |
1da177e4 LT |
828 | .probe = serial_pxa_probe, |
829 | .remove = serial_pxa_remove, | |
830 | ||
831 | .suspend = serial_pxa_suspend, | |
832 | .resume = serial_pxa_resume, | |
3ae5eaec RK |
833 | .driver = { |
834 | .name = "pxa2xx-uart", | |
835 | }, | |
1da177e4 LT |
836 | }; |
837 | ||
838 | int __init serial_pxa_init(void) | |
839 | { | |
840 | int ret; | |
841 | ||
842 | ret = uart_register_driver(&serial_pxa_reg); | |
843 | if (ret != 0) | |
844 | return ret; | |
845 | ||
3ae5eaec | 846 | ret = platform_driver_register(&serial_pxa_driver); |
1da177e4 LT |
847 | if (ret != 0) |
848 | uart_unregister_driver(&serial_pxa_reg); | |
849 | ||
850 | return ret; | |
851 | } | |
852 | ||
853 | void __exit serial_pxa_exit(void) | |
854 | { | |
3ae5eaec | 855 | platform_driver_unregister(&serial_pxa_driver); |
1da177e4 LT |
856 | uart_unregister_driver(&serial_pxa_reg); |
857 | } | |
858 | ||
859 | module_init(serial_pxa_init); | |
860 | module_exit(serial_pxa_exit); | |
861 | ||
862 | MODULE_LICENSE("GPL"); | |
863 |