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Create platform_device.h to contain all the platform device details.
[deliverable/linux.git] / drivers / serial / pxa.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/serial/pxa.c
3 *
4 * Based on drivers/serial/8250.c by Russell King.
5 *
6 * Author: Nicolas Pitre
7 * Created: Feb 20, 2003
8 * Copyright: (C) 2003 Monta Vista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * Note 1: This driver is made separate from the already too overloaded
16 * 8250.c because it needs some kirks of its own and that'll make it
17 * easier to add DMA support.
18 *
19 * Note 2: I'm too sick of device allocation policies for serial ports.
20 * If someone else wants to request an "official" allocation of major/minor
21 * for this driver please be my guest. And don't forget that new hardware
22 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
23 * hope for a better port registration and dynamic device allocation scheme
24 * with the serial core maintainer satisfaction to appear soon.
25 */
26
27#include <linux/config.h>
28
29#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/ioport.h>
35#include <linux/init.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
38#include <linux/serial_reg.h>
39#include <linux/circ_buf.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
d052d1be 42#include <linux/platform_device.h>
1da177e4
LT		 43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46
47#include <asm/io.h>
48#include <asm/hardware.h>
49#include <asm/irq.h>
50#include <asm/arch/pxa-regs.h>
51
52
53struct uart_pxa_port {
54 struct uart_port port;
55 unsigned char ier;
56 unsigned char lcr;
57 unsigned char mcr;
58 unsigned int lsr_break_flag;
59 unsigned int cken;
60 char *name;
61};
62
63static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
64{
65 offset <<= 2;
66 return readl(up->port.membase + offset);
67}
68
69static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
70{
71 offset <<= 2;
72 writel(value, up->port.membase + offset);
73}
74
75static void serial_pxa_enable_ms(struct uart_port *port)
76{
77 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
78
79 up->ier |= UART_IER_MSI;
80 serial_out(up, UART_IER, up->ier);
81}
82
b129a8cc 83static void serial_pxa_stop_tx(struct uart_port *port)
1da177e4
LT		 84{
85 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
86
87 if (up->ier & UART_IER_THRI) {
88 up->ier &= ~UART_IER_THRI;
89 serial_out(up, UART_IER, up->ier);
90 }
91}
92
93static void serial_pxa_stop_rx(struct uart_port *port)
94{
95 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
96
97 up->ier &= ~UART_IER_RLSI;
98 up->port.read_status_mask &= ~UART_LSR_DR;
99 serial_out(up, UART_IER, up->ier);
100}
101
102static inline void
103receive_chars(struct uart_pxa_port *up, int *status, struct pt_regs *regs)
104{
105 struct tty_struct *tty = up->port.info->tty;
106 unsigned int ch, flag;
107 int max_count = 256;
108
109 do {
110 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
111 if (tty->low_latency)
112 tty_flip_buffer_push(tty);
113 /*
114 * If this failed then we will throw away the
115 * bytes but must do so to clear interrupts
116 */
117 }
118 ch = serial_in(up, UART_RX);
119 flag = TTY_NORMAL;
120 up->port.icount.rx++;
121
122 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
123 UART_LSR_FE | UART_LSR_OE))) {
124 /*
125 * For statistics only
126 */
127 if (*status & UART_LSR_BI) {
128 *status &= ~(UART_LSR_FE | UART_LSR_PE);
129 up->port.icount.brk++;
130 /*
131 * We do the SysRQ and SAK checking
132 * here because otherwise the break
133 * may get masked by ignore_status_mask
134 * or read_status_mask.
135 */
136 if (uart_handle_break(&up->port))
137 goto ignore_char;
138 } else if (*status & UART_LSR_PE)
139 up->port.icount.parity++;
140 else if (*status & UART_LSR_FE)
141 up->port.icount.frame++;
142 if (*status & UART_LSR_OE)
143 up->port.icount.overrun++;
144
145 /*
146 * Mask off conditions which should be ignored.
147 */
148 *status &= up->port.read_status_mask;
149
150#ifdef CONFIG_SERIAL_PXA_CONSOLE
151 if (up->port.line == up->port.cons->index) {
152 /* Recover the break flag from console xmit */
153 *status |= up->lsr_break_flag;
154 up->lsr_break_flag = 0;
155 }
156#endif
157 if (*status & UART_LSR_BI) {
158 flag = TTY_BREAK;
159 } else if (*status & UART_LSR_PE)
160 flag = TTY_PARITY;
161 else if (*status & UART_LSR_FE)
162 flag = TTY_FRAME;
163 }
05ab3014 164
1da177e4
LT		 165 if (uart_handle_sysrq_char(&up->port, ch, regs))
166 goto ignore_char;
05ab3014
RK		 167
168 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
169
1da177e4
LT		 170 ignore_char:
171 *status = serial_in(up, UART_LSR);
172 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
173 tty_flip_buffer_push(tty);
174}
175
176static void transmit_chars(struct uart_pxa_port *up)
177{
178 struct circ_buf *xmit = &up->port.info->xmit;
179 int count;
180
181 if (up->port.x_char) {
182 serial_out(up, UART_TX, up->port.x_char);
183 up->port.icount.tx++;
184 up->port.x_char = 0;
185 return;
186 }
187 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
b129a8cc 188 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 189 return;
190 }
191
192 count = up->port.fifosize / 2;
193 do {
194 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
195 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
196 up->port.icount.tx++;
197 if (uart_circ_empty(xmit))
198 break;
199 } while (--count > 0);
200
201 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
202 uart_write_wakeup(&up->port);
203
204
205 if (uart_circ_empty(xmit))
b129a8cc 206 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 207}
208
b129a8cc 209static void serial_pxa_start_tx(struct uart_port *port)
1da177e4
LT		 210{
211 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
212
213 if (!(up->ier & UART_IER_THRI)) {
214 up->ier |= UART_IER_THRI;
215 serial_out(up, UART_IER, up->ier);
216 }
217}
218
219static inline void check_modem_status(struct uart_pxa_port *up)
220{
221 int status;
222
223 status = serial_in(up, UART_MSR);
224
225 if ((status & UART_MSR_ANY_DELTA) == 0)
226 return;
227
228 if (status & UART_MSR_TERI)
229 up->port.icount.rng++;
230 if (status & UART_MSR_DDSR)
231 up->port.icount.dsr++;
232 if (status & UART_MSR_DDCD)
233 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
234 if (status & UART_MSR_DCTS)
235 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
236
237 wake_up_interruptible(&up->port.info->delta_msr_wait);
238}
239
240/*
241 * This handles the interrupt from one port.
242 */
243static inline irqreturn_t
244serial_pxa_irq(int irq, void *dev_id, struct pt_regs *regs)
245{
246 struct uart_pxa_port *up = (struct uart_pxa_port *)dev_id;
247 unsigned int iir, lsr;
248
249 iir = serial_in(up, UART_IIR);
250 if (iir & UART_IIR_NO_INT)
251 return IRQ_NONE;
252 lsr = serial_in(up, UART_LSR);
253 if (lsr & UART_LSR_DR)
254 receive_chars(up, &lsr, regs);
255 check_modem_status(up);
256 if (lsr & UART_LSR_THRE)
257 transmit_chars(up);
258 return IRQ_HANDLED;
259}
260
261static unsigned int serial_pxa_tx_empty(struct uart_port *port)
262{
263 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
264 unsigned long flags;
265 unsigned int ret;
266
267 spin_lock_irqsave(&up->port.lock, flags);
268 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
269 spin_unlock_irqrestore(&up->port.lock, flags);
270
271 return ret;
272}
273
274static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
275{
276 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
1da177e4
LT		 277 unsigned char status;
278 unsigned int ret;
279
280return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1da177e4 281 status = serial_in(up, UART_MSR);
1da177e4
LT		 282
283 ret = 0;
284 if (status & UART_MSR_DCD)
285 ret |= TIOCM_CAR;
286 if (status & UART_MSR_RI)
287 ret |= TIOCM_RNG;
288 if (status & UART_MSR_DSR)
289 ret |= TIOCM_DSR;
290 if (status & UART_MSR_CTS)
291 ret |= TIOCM_CTS;
292 return ret;
293}
294
295static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
296{
297 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
298 unsigned char mcr = 0;
299
300 if (mctrl & TIOCM_RTS)
301 mcr |= UART_MCR_RTS;
302 if (mctrl & TIOCM_DTR)
303 mcr |= UART_MCR_DTR;
304 if (mctrl & TIOCM_OUT1)
305 mcr |= UART_MCR_OUT1;
306 if (mctrl & TIOCM_OUT2)
307 mcr |= UART_MCR_OUT2;
308 if (mctrl & TIOCM_LOOP)
309 mcr |= UART_MCR_LOOP;
310
311 mcr |= up->mcr;
312
313 serial_out(up, UART_MCR, mcr);
314}
315
316static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
317{
318 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
319 unsigned long flags;
320
321 spin_lock_irqsave(&up->port.lock, flags);
322 if (break_state == -1)
323 up->lcr |= UART_LCR_SBC;
324 else
325 up->lcr &= ~UART_LCR_SBC;
326 serial_out(up, UART_LCR, up->lcr);
327 spin_unlock_irqrestore(&up->port.lock, flags);
328}
329
330#if 0
331static void serial_pxa_dma_init(struct pxa_uart *up)
332{
333 up->rxdma =
334 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up);
335 if (up->rxdma < 0)
336 goto out;
337 up->txdma =
338 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up);
339 if (up->txdma < 0)
340 goto err_txdma;
341 up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL);
342 if (!up->dmadesc)
343 goto err_alloc;
344
345 /* ... */
346err_alloc:
347 pxa_free_dma(up->txdma);
348err_rxdma:
349 pxa_free_dma(up->rxdma);
350out:
351 return;
352}
353#endif
354
355static int serial_pxa_startup(struct uart_port *port)
356{
357 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
358 unsigned long flags;
359 int retval;
360
d9e29649
MR		 361 if (port->line == 3) /* HWUART */
362 up->mcr |= UART_MCR_AFE;
363 else
1da177e4
LT		 364 up->mcr = 0;
365
366 /*
367 * Allocate the IRQ
368 */
369 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
370 if (retval)
371 return retval;
372
373 /*
374 * Clear the FIFO buffers and disable them.
375 * (they will be reenabled in set_termios())
376 */
377 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
378 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
379 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
380 serial_out(up, UART_FCR, 0);
381
382 /*
383 * Clear the interrupt registers.
384 */
385 (void) serial_in(up, UART_LSR);
386 (void) serial_in(up, UART_RX);
387 (void) serial_in(up, UART_IIR);
388 (void) serial_in(up, UART_MSR);
389
390 /*
391 * Now, initialize the UART
392 */
393 serial_out(up, UART_LCR, UART_LCR_WLEN8);
394
395 spin_lock_irqsave(&up->port.lock, flags);
396 up->port.mctrl |= TIOCM_OUT2;
397 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
398 spin_unlock_irqrestore(&up->port.lock, flags);
399
400 /*
401 * Finally, enable interrupts. Note: Modem status interrupts
402 * are set via set_termios(), which will be occuring imminently
403 * anyway, so we don't enable them here.
404 */
405 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
406 serial_out(up, UART_IER, up->ier);
407
408 /*
409 * And clear the interrupt registers again for luck.
410 */
411 (void) serial_in(up, UART_LSR);
412 (void) serial_in(up, UART_RX);
413 (void) serial_in(up, UART_IIR);
414 (void) serial_in(up, UART_MSR);
415
416 return 0;
417}
418
419static void serial_pxa_shutdown(struct uart_port *port)
420{
421 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
422 unsigned long flags;
423
424 free_irq(up->port.irq, up);
425
426 /*
427 * Disable interrupts from this port
428 */
429 up->ier = 0;
430 serial_out(up, UART_IER, 0);
431
432 spin_lock_irqsave(&up->port.lock, flags);
433 up->port.mctrl &= ~TIOCM_OUT2;
434 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
435 spin_unlock_irqrestore(&up->port.lock, flags);
436
437 /*
438 * Disable break condition and FIFOs
439 */
440 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
441 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
442 UART_FCR_CLEAR_RCVR |
443 UART_FCR_CLEAR_XMIT);
444 serial_out(up, UART_FCR, 0);
445}
446
447static void
448serial_pxa_set_termios(struct uart_port *port, struct termios *termios,
449 struct termios *old)
450{
451 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
452 unsigned char cval, fcr = 0;
453 unsigned long flags;
454 unsigned int baud, quot;
455
456 switch (termios->c_cflag & CSIZE) {
457 case CS5:
0a8b80c5 458 cval = UART_LCR_WLEN5;
1da177e4
LT		 459 break;
460 case CS6:
0a8b80c5 461 cval = UART_LCR_WLEN6;
1da177e4
LT		 462 break;
463 case CS7:
0a8b80c5 464 cval = UART_LCR_WLEN7;
1da177e4
LT		 465 break;
466 default:
467 case CS8:
0a8b80c5 468 cval = UART_LCR_WLEN8;
1da177e4
LT		 469 break;
470 }
471
472 if (termios->c_cflag & CSTOPB)
0a8b80c5 473 cval |= UART_LCR_STOP;
1da177e4
LT		 474 if (termios->c_cflag & PARENB)
475 cval |= UART_LCR_PARITY;
476 if (!(termios->c_cflag & PARODD))
477 cval |= UART_LCR_EPAR;
478
479 /*
480 * Ask the core to calculate the divisor for us.
481 */
482 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
483 quot = uart_get_divisor(port, baud);
484
485 if ((up->port.uartclk / quot) < (2400 * 16))
486 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
d9e29649 487 else if ((up->port.uartclk / quot) < (230400 * 16))
1da177e4 488 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
d9e29649
MR		 489 else
490 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
1da177e4
LT		 491
492 /*
493 * Ok, we're now changing the port state. Do it with
494 * interrupts disabled.
495 */
496 spin_lock_irqsave(&up->port.lock, flags);
497
498 /*
499 * Ensure the port will be enabled.
500 * This is required especially for serial console.
501 */
502 up->ier |= IER_UUE;
503
504 /*
505 * Update the per-port timeout.
506 */
e6158b4a 507 uart_update_timeout(port, termios->c_cflag, baud);
1da177e4
LT		 508
509 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
510 if (termios->c_iflag & INPCK)
511 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
512 if (termios->c_iflag & (BRKINT | PARMRK))
513 up->port.read_status_mask |= UART_LSR_BI;
514
515 /*
516 * Characters to ignore
517 */
518 up->port.ignore_status_mask = 0;
519 if (termios->c_iflag & IGNPAR)
520 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
521 if (termios->c_iflag & IGNBRK) {
522 up->port.ignore_status_mask |= UART_LSR_BI;
523 /*
524 * If we're ignoring parity and break indicators,
525 * ignore overruns too (for real raw support).
526 */
527 if (termios->c_iflag & IGNPAR)
528 up->port.ignore_status_mask |= UART_LSR_OE;
529 }
530
531 /*
532 * ignore all characters if CREAD is not set
533 */
534 if ((termios->c_cflag & CREAD) == 0)
535 up->port.ignore_status_mask |= UART_LSR_DR;
536
537 /*
538 * CTS flow control flag and modem status interrupts
539 */
540 up->ier &= ~UART_IER_MSI;
541 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
542 up->ier |= UART_IER_MSI;
543
544 serial_out(up, UART_IER, up->ier);
545
546 serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
547 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
548 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
549 serial_out(up, UART_LCR, cval); /* reset DLAB */
550 up->lcr = cval; /* Save LCR */
551 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
552 serial_out(up, UART_FCR, fcr);
553 spin_unlock_irqrestore(&up->port.lock, flags);
554}
555
556static void
557serial_pxa_pm(struct uart_port *port, unsigned int state,
558 unsigned int oldstate)
559{
560 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
561 pxa_set_cken(up->cken, !state);
562 if (!state)
563 udelay(1);
564}
565
566static void serial_pxa_release_port(struct uart_port *port)
567{
568}
569
570static int serial_pxa_request_port(struct uart_port *port)
571{
572 return 0;
573}
574
575static void serial_pxa_config_port(struct uart_port *port, int flags)
576{
577 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
578 up->port.type = PORT_PXA;
579}
580
581static int
582serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
583{
584 /* we don't want the core code to modify any port params */
585 return -EINVAL;
586}
587
588static const char *
589serial_pxa_type(struct uart_port *port)
590{
591 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
592 return up->name;
593}
594
595#ifdef CONFIG_SERIAL_PXA_CONSOLE
596
2d93486c
VS		 597static struct uart_pxa_port serial_pxa_ports[];
598static struct uart_driver serial_pxa_reg;
1da177e4
LT		 599
600#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
601
602/*
603 * Wait for transmitter & holding register to empty
604 */
605static inline void wait_for_xmitr(struct uart_pxa_port *up)
606{
607 unsigned int status, tmout = 10000;
608
609 /* Wait up to 10ms for the character(s) to be sent. */
610 do {
611 status = serial_in(up, UART_LSR);
612
613 if (status & UART_LSR_BI)
614 up->lsr_break_flag = UART_LSR_BI;
615
616 if (--tmout == 0)
617 break;
618 udelay(1);
619 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
620
621 /* Wait up to 1s for flow control if necessary */
622 if (up->port.flags & UPF_CONS_FLOW) {
623 tmout = 1000000;
624 while (--tmout &&
625 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
626 udelay(1);
627 }
628}
629
630/*
631 * Print a string to the serial port trying not to disturb
632 * any possible real use of the port...
633 *
634 * The console_lock must be held when we get here.
635 */
636static void
637serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
638{
639 struct uart_pxa_port *up = &serial_pxa_ports[co->index];
640 unsigned int ier;
641 int i;
642
643 /*
644 * First save the UER then disable the interrupts
645 */
646 ier = serial_in(up, UART_IER);
647 serial_out(up, UART_IER, UART_IER_UUE);
648
649 /*
650 * Now, do each character
651 */
652 for (i = 0; i < count; i++, s++) {
653 wait_for_xmitr(up);
654
655 /*
656 * Send the character out.
657 * If a LF, also do CR...
658 */
659 serial_out(up, UART_TX, *s);
660 if (*s == 10) {
661 wait_for_xmitr(up);
662 serial_out(up, UART_TX, 13);
663 }
664 }
665
666 /*
667 * Finally, wait for transmitter to become empty
668 * and restore the IER
669 */
670 wait_for_xmitr(up);
671 serial_out(up, UART_IER, ier);
672}
673
674static int __init
675serial_pxa_console_setup(struct console *co, char *options)
676{
677 struct uart_pxa_port *up;
678 int baud = 9600;
679 int bits = 8;
680 int parity = 'n';
681 int flow = 'n';
682
683 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
684 co->index = 0;
685 up = &serial_pxa_ports[co->index];
686
687 if (options)
688 uart_parse_options(options, &baud, &parity, &bits, &flow);
689
690 return uart_set_options(&up->port, co, baud, parity, bits, flow);
691}
692
693static struct console serial_pxa_console = {
694 .name = "ttyS",
695 .write = serial_pxa_console_write,
696 .device = uart_console_device,
697 .setup = serial_pxa_console_setup,
698 .flags = CON_PRINTBUFFER,
699 .index = -1,
700 .data = &serial_pxa_reg,
701};
702
703static int __init
704serial_pxa_console_init(void)
705{
706 register_console(&serial_pxa_console);
707 return 0;
708}
709
710console_initcall(serial_pxa_console_init);
711
712#define PXA_CONSOLE &serial_pxa_console
713#else
714#define PXA_CONSOLE NULL
715#endif
716
717struct uart_ops serial_pxa_pops = {
718 .tx_empty = serial_pxa_tx_empty,
719 .set_mctrl = serial_pxa_set_mctrl,
720 .get_mctrl = serial_pxa_get_mctrl,
721 .stop_tx = serial_pxa_stop_tx,
722 .start_tx = serial_pxa_start_tx,
723 .stop_rx = serial_pxa_stop_rx,
724 .enable_ms = serial_pxa_enable_ms,
725 .break_ctl = serial_pxa_break_ctl,
726 .startup = serial_pxa_startup,
727 .shutdown = serial_pxa_shutdown,
728 .set_termios = serial_pxa_set_termios,
729 .pm = serial_pxa_pm,
730 .type = serial_pxa_type,
731 .release_port = serial_pxa_release_port,
732 .request_port = serial_pxa_request_port,
733 .config_port = serial_pxa_config_port,
734 .verify_port = serial_pxa_verify_port,
735};
736
737static struct uart_pxa_port serial_pxa_ports[] = {
738 { /* FFUART */
739 .name = "FFUART",
740 .cken = CKEN6_FFUART,
741 .port = {
742 .type = PORT_PXA,
743 .iotype = UPIO_MEM,
744 .membase = (void *)&FFUART,
745 .mapbase = __PREG(FFUART),
746 .irq = IRQ_FFUART,
747 .uartclk = 921600 * 16,
748 .fifosize = 64,
749 .ops = &serial_pxa_pops,
750 .line = 0,
751 },
752 }, { /* BTUART */
753 .name = "BTUART",
754 .cken = CKEN7_BTUART,
755 .port = {
756 .type = PORT_PXA,
757 .iotype = UPIO_MEM,
758 .membase = (void *)&BTUART,
759 .mapbase = __PREG(BTUART),
760 .irq = IRQ_BTUART,
761 .uartclk = 921600 * 16,
762 .fifosize = 64,
763 .ops = &serial_pxa_pops,
764 .line = 1,
765 },
766 }, { /* STUART */
767 .name = "STUART",
768 .cken = CKEN5_STUART,
769 .port = {
770 .type = PORT_PXA,
771 .iotype = UPIO_MEM,
772 .membase = (void *)&STUART,
773 .mapbase = __PREG(STUART),
774 .irq = IRQ_STUART,
775 .uartclk = 921600 * 16,
776 .fifosize = 64,
777 .ops = &serial_pxa_pops,
778 .line = 2,
779 },
d9e29649
MR		 780 }, { /* HWUART */
781 .name = "HWUART",
782 .cken = CKEN4_HWUART,
783 .port = {
784 .type = PORT_PXA,
785 .iotype = UPIO_MEM,
786 .membase = (void *)&HWUART,
787 .mapbase = __PREG(HWUART),
788 .irq = IRQ_HWUART,
789 .uartclk = 921600 * 16,
790 .fifosize = 64,
791 .ops = &serial_pxa_pops,
792 .line = 3,
793 },
1da177e4
LT		 794 }
795};
796
797static struct uart_driver serial_pxa_reg = {
798 .owner = THIS_MODULE,
799 .driver_name = "PXA serial",
800 .devfs_name = "tts/",
801 .dev_name = "ttyS",
802 .major = TTY_MAJOR,
803 .minor = 64,
804 .nr = ARRAY_SIZE(serial_pxa_ports),
805 .cons = PXA_CONSOLE,
806};
807
9480e307 808static int serial_pxa_suspend(struct device *_dev, pm_message_t state)
1da177e4
LT		 809{
810 struct uart_pxa_port *sport = dev_get_drvdata(_dev);
811
9480e307 812 if (sport)
1da177e4
LT		 813 uart_suspend_port(&serial_pxa_reg, &sport->port);
814
815 return 0;
816}
817
9480e307 818static int serial_pxa_resume(struct device *_dev)
1da177e4
LT		 819{
820 struct uart_pxa_port *sport = dev_get_drvdata(_dev);
821
9480e307 822 if (sport)
1da177e4
LT		 823 uart_resume_port(&serial_pxa_reg, &sport->port);
824
825 return 0;
826}
827
828static int serial_pxa_probe(struct device *_dev)
829{
830 struct platform_device *dev = to_platform_device(_dev);
831
832 serial_pxa_ports[dev->id].port.dev = _dev;
833 uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port);
834 dev_set_drvdata(_dev, &serial_pxa_ports[dev->id]);
835 return 0;
836}
837
838static int serial_pxa_remove(struct device *_dev)
839{
840 struct uart_pxa_port *sport = dev_get_drvdata(_dev);
841
842 dev_set_drvdata(_dev, NULL);
843
844 if (sport)
845 uart_remove_one_port(&serial_pxa_reg, &sport->port);
846
847 return 0;
848}
849
850static struct device_driver serial_pxa_driver = {
851 .name = "pxa2xx-uart",
852 .bus = &platform_bus_type,
853 .probe = serial_pxa_probe,
854 .remove = serial_pxa_remove,
855
856 .suspend = serial_pxa_suspend,
857 .resume = serial_pxa_resume,
858};
859
860int __init serial_pxa_init(void)
861{
862 int ret;
863
864 ret = uart_register_driver(&serial_pxa_reg);
865 if (ret != 0)
866 return ret;
867
868 ret = driver_register(&serial_pxa_driver);
869 if (ret != 0)
870 uart_unregister_driver(&serial_pxa_reg);
871
872 return ret;
873}
874
875void __exit serial_pxa_exit(void)
876{
877 driver_unregister(&serial_pxa_driver);
878 uart_unregister_driver(&serial_pxa_reg);
879}
880
881module_init(serial_pxa_init);
882module_exit(serial_pxa_exit);
883
884MODULE_LICENSE("GPL");
885
Linux kernel - Deliverables
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