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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/sa1100.c | |
3 | * | |
4 | * Driver for SA11x0 serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * $Id: sa1100.c,v 1.50 2002/07/29 14:41:04 rmk Exp $ | |
25 | * | |
26 | */ | |
27 | #include <linux/config.h> | |
28 | ||
29 | #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
30 | #define SUPPORT_SYSRQ | |
31 | #endif | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <linux/ioport.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/console.h> | |
37 | #include <linux/sysrq.h> | |
d052d1be | 38 | #include <linux/platform_device.h> |
1da177e4 LT |
39 | #include <linux/tty.h> |
40 | #include <linux/tty_flip.h> | |
41 | #include <linux/serial_core.h> | |
42 | #include <linux/serial.h> | |
43 | ||
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
46 | #include <asm/hardware.h> | |
47 | #include <asm/mach/serial_sa1100.h> | |
48 | ||
49 | /* We've been assigned a range on the "Low-density serial ports" major */ | |
50 | #define SERIAL_SA1100_MAJOR 204 | |
51 | #define MINOR_START 5 | |
52 | ||
53 | #define NR_PORTS 3 | |
54 | ||
55 | #define SA1100_ISR_PASS_LIMIT 256 | |
56 | ||
57 | /* | |
58 | * Convert from ignore_status_mask or read_status_mask to UTSR[01] | |
59 | */ | |
60 | #define SM_TO_UTSR0(x) ((x) & 0xff) | |
61 | #define SM_TO_UTSR1(x) ((x) >> 8) | |
62 | #define UTSR0_TO_SM(x) ((x)) | |
63 | #define UTSR1_TO_SM(x) ((x) << 8) | |
64 | ||
65 | #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0) | |
66 | #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1) | |
67 | #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2) | |
68 | #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3) | |
69 | #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0) | |
70 | #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1) | |
71 | #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR) | |
72 | ||
73 | #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0) | |
74 | #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1) | |
75 | #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2) | |
76 | #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3) | |
77 | #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0) | |
78 | #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1) | |
79 | #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR) | |
80 | ||
81 | /* | |
82 | * This is the size of our serial port register set. | |
83 | */ | |
84 | #define UART_PORT_SIZE 0x24 | |
85 | ||
86 | /* | |
87 | * This determines how often we check the modem status signals | |
88 | * for any change. They generally aren't connected to an IRQ | |
89 | * so we have to poll them. We also check immediately before | |
90 | * filling the TX fifo incase CTS has been dropped. | |
91 | */ | |
92 | #define MCTRL_TIMEOUT (250*HZ/1000) | |
93 | ||
94 | struct sa1100_port { | |
95 | struct uart_port port; | |
96 | struct timer_list timer; | |
97 | unsigned int old_status; | |
98 | }; | |
99 | ||
100 | /* | |
101 | * Handle any change of modem status signal since we were last called. | |
102 | */ | |
103 | static void sa1100_mctrl_check(struct sa1100_port *sport) | |
104 | { | |
105 | unsigned int status, changed; | |
106 | ||
107 | status = sport->port.ops->get_mctrl(&sport->port); | |
108 | changed = status ^ sport->old_status; | |
109 | ||
110 | if (changed == 0) | |
111 | return; | |
112 | ||
113 | sport->old_status = status; | |
114 | ||
115 | if (changed & TIOCM_RI) | |
116 | sport->port.icount.rng++; | |
117 | if (changed & TIOCM_DSR) | |
118 | sport->port.icount.dsr++; | |
119 | if (changed & TIOCM_CAR) | |
120 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | |
121 | if (changed & TIOCM_CTS) | |
122 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | |
123 | ||
124 | wake_up_interruptible(&sport->port.info->delta_msr_wait); | |
125 | } | |
126 | ||
127 | /* | |
128 | * This is our per-port timeout handler, for checking the | |
129 | * modem status signals. | |
130 | */ | |
131 | static void sa1100_timeout(unsigned long data) | |
132 | { | |
133 | struct sa1100_port *sport = (struct sa1100_port *)data; | |
134 | unsigned long flags; | |
135 | ||
136 | if (sport->port.info) { | |
137 | spin_lock_irqsave(&sport->port.lock, flags); | |
138 | sa1100_mctrl_check(sport); | |
139 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
140 | ||
141 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | |
142 | } | |
143 | } | |
144 | ||
145 | /* | |
146 | * interrupts disabled on entry | |
147 | */ | |
b129a8cc | 148 | static void sa1100_stop_tx(struct uart_port *port) |
1da177e4 LT |
149 | { |
150 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
151 | u32 utcr3; | |
152 | ||
153 | utcr3 = UART_GET_UTCR3(sport); | |
154 | UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE); | |
155 | sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS); | |
156 | } | |
157 | ||
158 | /* | |
270c7a72 | 159 | * port locked and interrupts disabled |
1da177e4 | 160 | */ |
b129a8cc | 161 | static void sa1100_start_tx(struct uart_port *port) |
1da177e4 LT |
162 | { |
163 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
1da177e4 LT |
164 | u32 utcr3; |
165 | ||
1da177e4 LT |
166 | utcr3 = UART_GET_UTCR3(sport); |
167 | sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS); | |
168 | UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE); | |
1da177e4 LT |
169 | } |
170 | ||
171 | /* | |
172 | * Interrupts enabled | |
173 | */ | |
174 | static void sa1100_stop_rx(struct uart_port *port) | |
175 | { | |
176 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
177 | u32 utcr3; | |
178 | ||
179 | utcr3 = UART_GET_UTCR3(sport); | |
180 | UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE); | |
181 | } | |
182 | ||
183 | /* | |
184 | * Set the modem control timer to fire immediately. | |
185 | */ | |
186 | static void sa1100_enable_ms(struct uart_port *port) | |
187 | { | |
188 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
189 | ||
190 | mod_timer(&sport->timer, jiffies); | |
191 | } | |
192 | ||
193 | static void | |
194 | sa1100_rx_chars(struct sa1100_port *sport, struct pt_regs *regs) | |
195 | { | |
196 | struct tty_struct *tty = sport->port.info->tty; | |
ff39bc77 | 197 | unsigned int status, ch, flg; |
1da177e4 LT |
198 | |
199 | status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | | |
200 | UTSR0_TO_SM(UART_GET_UTSR0(sport)); | |
201 | while (status & UTSR1_TO_SM(UTSR1_RNE)) { | |
202 | ch = UART_GET_CHAR(sport); | |
203 | ||
1da177e4 LT |
204 | sport->port.icount.rx++; |
205 | ||
206 | flg = TTY_NORMAL; | |
207 | ||
208 | /* | |
209 | * note that the error handling code is | |
210 | * out of the main execution path | |
211 | */ | |
2a9604b8 RK |
212 | if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) { |
213 | if (status & UTSR1_TO_SM(UTSR1_PRE)) | |
214 | sport->port.icount.parity++; | |
215 | else if (status & UTSR1_TO_SM(UTSR1_FRE)) | |
216 | sport->port.icount.frame++; | |
217 | if (status & UTSR1_TO_SM(UTSR1_ROR)) | |
218 | sport->port.icount.overrun++; | |
219 | ||
220 | status &= sport->port.read_status_mask; | |
221 | ||
222 | if (status & UTSR1_TO_SM(UTSR1_PRE)) | |
223 | flg = TTY_PARITY; | |
224 | else if (status & UTSR1_TO_SM(UTSR1_FRE)) | |
225 | flg = TTY_FRAME; | |
226 | ||
227 | #ifdef SUPPORT_SYSRQ | |
228 | sport->port.sysrq = 0; | |
229 | #endif | |
230 | } | |
1da177e4 LT |
231 | |
232 | if (uart_handle_sysrq_char(&sport->port, ch, regs)) | |
233 | goto ignore_char; | |
234 | ||
05ab3014 | 235 | uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg); |
2a9604b8 | 236 | |
1da177e4 LT |
237 | ignore_char: |
238 | status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | | |
239 | UTSR0_TO_SM(UART_GET_UTSR0(sport)); | |
240 | } | |
1da177e4 | 241 | tty_flip_buffer_push(tty); |
1da177e4 LT |
242 | } |
243 | ||
244 | static void sa1100_tx_chars(struct sa1100_port *sport) | |
245 | { | |
246 | struct circ_buf *xmit = &sport->port.info->xmit; | |
247 | ||
248 | if (sport->port.x_char) { | |
249 | UART_PUT_CHAR(sport, sport->port.x_char); | |
250 | sport->port.icount.tx++; | |
251 | sport->port.x_char = 0; | |
252 | return; | |
253 | } | |
254 | ||
255 | /* | |
256 | * Check the modem control lines before | |
257 | * transmitting anything. | |
258 | */ | |
259 | sa1100_mctrl_check(sport); | |
260 | ||
261 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
b129a8cc | 262 | sa1100_stop_tx(&sport->port); |
1da177e4 LT |
263 | return; |
264 | } | |
265 | ||
266 | /* | |
267 | * Tried using FIFO (not checking TNF) for fifo fill: | |
268 | * still had the '4 bytes repeated' problem. | |
269 | */ | |
270 | while (UART_GET_UTSR1(sport) & UTSR1_TNF) { | |
271 | UART_PUT_CHAR(sport, xmit->buf[xmit->tail]); | |
272 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
273 | sport->port.icount.tx++; | |
274 | if (uart_circ_empty(xmit)) | |
275 | break; | |
276 | } | |
277 | ||
278 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
279 | uart_write_wakeup(&sport->port); | |
280 | ||
281 | if (uart_circ_empty(xmit)) | |
b129a8cc | 282 | sa1100_stop_tx(&sport->port); |
1da177e4 LT |
283 | } |
284 | ||
285 | static irqreturn_t sa1100_int(int irq, void *dev_id, struct pt_regs *regs) | |
286 | { | |
287 | struct sa1100_port *sport = dev_id; | |
288 | unsigned int status, pass_counter = 0; | |
289 | ||
290 | spin_lock(&sport->port.lock); | |
291 | status = UART_GET_UTSR0(sport); | |
292 | status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS; | |
293 | do { | |
294 | if (status & (UTSR0_RFS | UTSR0_RID)) { | |
295 | /* Clear the receiver idle bit, if set */ | |
296 | if (status & UTSR0_RID) | |
297 | UART_PUT_UTSR0(sport, UTSR0_RID); | |
298 | sa1100_rx_chars(sport, regs); | |
299 | } | |
300 | ||
301 | /* Clear the relevant break bits */ | |
302 | if (status & (UTSR0_RBB | UTSR0_REB)) | |
303 | UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB)); | |
304 | ||
305 | if (status & UTSR0_RBB) | |
306 | sport->port.icount.brk++; | |
307 | ||
308 | if (status & UTSR0_REB) | |
309 | uart_handle_break(&sport->port); | |
310 | ||
311 | if (status & UTSR0_TFS) | |
312 | sa1100_tx_chars(sport); | |
313 | if (pass_counter++ > SA1100_ISR_PASS_LIMIT) | |
314 | break; | |
315 | status = UART_GET_UTSR0(sport); | |
316 | status &= SM_TO_UTSR0(sport->port.read_status_mask) | | |
317 | ~UTSR0_TFS; | |
318 | } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID)); | |
319 | spin_unlock(&sport->port.lock); | |
320 | ||
321 | return IRQ_HANDLED; | |
322 | } | |
323 | ||
324 | /* | |
325 | * Return TIOCSER_TEMT when transmitter is not busy. | |
326 | */ | |
327 | static unsigned int sa1100_tx_empty(struct uart_port *port) | |
328 | { | |
329 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
330 | ||
331 | return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT; | |
332 | } | |
333 | ||
334 | static unsigned int sa1100_get_mctrl(struct uart_port *port) | |
335 | { | |
336 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
337 | } | |
338 | ||
339 | static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
340 | { | |
341 | } | |
342 | ||
343 | /* | |
344 | * Interrupts always disabled. | |
345 | */ | |
346 | static void sa1100_break_ctl(struct uart_port *port, int break_state) | |
347 | { | |
348 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
349 | unsigned long flags; | |
350 | unsigned int utcr3; | |
351 | ||
352 | spin_lock_irqsave(&sport->port.lock, flags); | |
353 | utcr3 = UART_GET_UTCR3(sport); | |
354 | if (break_state == -1) | |
355 | utcr3 |= UTCR3_BRK; | |
356 | else | |
357 | utcr3 &= ~UTCR3_BRK; | |
358 | UART_PUT_UTCR3(sport, utcr3); | |
359 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
360 | } | |
361 | ||
362 | static int sa1100_startup(struct uart_port *port) | |
363 | { | |
364 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
365 | int retval; | |
366 | ||
367 | /* | |
368 | * Allocate the IRQ | |
369 | */ | |
370 | retval = request_irq(sport->port.irq, sa1100_int, 0, | |
371 | "sa11x0-uart", sport); | |
372 | if (retval) | |
373 | return retval; | |
374 | ||
375 | /* | |
376 | * Finally, clear and enable interrupts | |
377 | */ | |
378 | UART_PUT_UTSR0(sport, -1); | |
379 | UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE); | |
380 | ||
381 | /* | |
382 | * Enable modem status interrupts | |
383 | */ | |
384 | spin_lock_irq(&sport->port.lock); | |
385 | sa1100_enable_ms(&sport->port); | |
386 | spin_unlock_irq(&sport->port.lock); | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | static void sa1100_shutdown(struct uart_port *port) | |
392 | { | |
393 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
394 | ||
395 | /* | |
396 | * Stop our timer. | |
397 | */ | |
398 | del_timer_sync(&sport->timer); | |
399 | ||
400 | /* | |
401 | * Free the interrupt | |
402 | */ | |
403 | free_irq(sport->port.irq, sport); | |
404 | ||
405 | /* | |
406 | * Disable all interrupts, port and break condition. | |
407 | */ | |
408 | UART_PUT_UTCR3(sport, 0); | |
409 | } | |
410 | ||
411 | static void | |
412 | sa1100_set_termios(struct uart_port *port, struct termios *termios, | |
413 | struct termios *old) | |
414 | { | |
415 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
416 | unsigned long flags; | |
417 | unsigned int utcr0, old_utcr3, baud, quot; | |
418 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
419 | ||
420 | /* | |
421 | * We only support CS7 and CS8. | |
422 | */ | |
423 | while ((termios->c_cflag & CSIZE) != CS7 && | |
424 | (termios->c_cflag & CSIZE) != CS8) { | |
425 | termios->c_cflag &= ~CSIZE; | |
426 | termios->c_cflag |= old_csize; | |
427 | old_csize = CS8; | |
428 | } | |
429 | ||
430 | if ((termios->c_cflag & CSIZE) == CS8) | |
431 | utcr0 = UTCR0_DSS; | |
432 | else | |
433 | utcr0 = 0; | |
434 | ||
435 | if (termios->c_cflag & CSTOPB) | |
436 | utcr0 |= UTCR0_SBS; | |
437 | if (termios->c_cflag & PARENB) { | |
438 | utcr0 |= UTCR0_PE; | |
439 | if (!(termios->c_cflag & PARODD)) | |
440 | utcr0 |= UTCR0_OES; | |
441 | } | |
442 | ||
443 | /* | |
444 | * Ask the core to calculate the divisor for us. | |
445 | */ | |
446 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
447 | quot = uart_get_divisor(port, baud); | |
448 | ||
449 | spin_lock_irqsave(&sport->port.lock, flags); | |
450 | ||
451 | sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS); | |
452 | sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR); | |
453 | if (termios->c_iflag & INPCK) | |
454 | sport->port.read_status_mask |= | |
455 | UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); | |
456 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
457 | sport->port.read_status_mask |= | |
458 | UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); | |
459 | ||
460 | /* | |
461 | * Characters to ignore | |
462 | */ | |
463 | sport->port.ignore_status_mask = 0; | |
464 | if (termios->c_iflag & IGNPAR) | |
465 | sport->port.ignore_status_mask |= | |
466 | UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); | |
467 | if (termios->c_iflag & IGNBRK) { | |
468 | sport->port.ignore_status_mask |= | |
469 | UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); | |
470 | /* | |
471 | * If we're ignoring parity and break indicators, | |
472 | * ignore overruns too (for real raw support). | |
473 | */ | |
474 | if (termios->c_iflag & IGNPAR) | |
475 | sport->port.ignore_status_mask |= | |
476 | UTSR1_TO_SM(UTSR1_ROR); | |
477 | } | |
478 | ||
479 | del_timer_sync(&sport->timer); | |
480 | ||
481 | /* | |
482 | * Update the per-port timeout. | |
483 | */ | |
484 | uart_update_timeout(port, termios->c_cflag, baud); | |
485 | ||
486 | /* | |
487 | * disable interrupts and drain transmitter | |
488 | */ | |
489 | old_utcr3 = UART_GET_UTCR3(sport); | |
490 | UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)); | |
491 | ||
492 | while (UART_GET_UTSR1(sport) & UTSR1_TBY) | |
493 | barrier(); | |
494 | ||
495 | /* then, disable everything */ | |
496 | UART_PUT_UTCR3(sport, 0); | |
497 | ||
498 | /* set the parity, stop bits and data size */ | |
499 | UART_PUT_UTCR0(sport, utcr0); | |
500 | ||
501 | /* set the baud rate */ | |
502 | quot -= 1; | |
503 | UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8)); | |
504 | UART_PUT_UTCR2(sport, (quot & 0xff)); | |
505 | ||
506 | UART_PUT_UTSR0(sport, -1); | |
507 | ||
508 | UART_PUT_UTCR3(sport, old_utcr3); | |
509 | ||
510 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | |
511 | sa1100_enable_ms(&sport->port); | |
512 | ||
513 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
514 | } | |
515 | ||
516 | static const char *sa1100_type(struct uart_port *port) | |
517 | { | |
518 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
519 | ||
520 | return sport->port.type == PORT_SA1100 ? "SA1100" : NULL; | |
521 | } | |
522 | ||
523 | /* | |
524 | * Release the memory region(s) being used by 'port'. | |
525 | */ | |
526 | static void sa1100_release_port(struct uart_port *port) | |
527 | { | |
528 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
529 | ||
530 | release_mem_region(sport->port.mapbase, UART_PORT_SIZE); | |
531 | } | |
532 | ||
533 | /* | |
534 | * Request the memory region(s) being used by 'port'. | |
535 | */ | |
536 | static int sa1100_request_port(struct uart_port *port) | |
537 | { | |
538 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
539 | ||
540 | return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, | |
541 | "sa11x0-uart") != NULL ? 0 : -EBUSY; | |
542 | } | |
543 | ||
544 | /* | |
545 | * Configure/autoconfigure the port. | |
546 | */ | |
547 | static void sa1100_config_port(struct uart_port *port, int flags) | |
548 | { | |
549 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
550 | ||
551 | if (flags & UART_CONFIG_TYPE && | |
552 | sa1100_request_port(&sport->port) == 0) | |
553 | sport->port.type = PORT_SA1100; | |
554 | } | |
555 | ||
556 | /* | |
557 | * Verify the new serial_struct (for TIOCSSERIAL). | |
558 | * The only change we allow are to the flags and type, and | |
559 | * even then only between PORT_SA1100 and PORT_UNKNOWN | |
560 | */ | |
561 | static int | |
562 | sa1100_verify_port(struct uart_port *port, struct serial_struct *ser) | |
563 | { | |
564 | struct sa1100_port *sport = (struct sa1100_port *)port; | |
565 | int ret = 0; | |
566 | ||
567 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100) | |
568 | ret = -EINVAL; | |
569 | if (sport->port.irq != ser->irq) | |
570 | ret = -EINVAL; | |
571 | if (ser->io_type != SERIAL_IO_MEM) | |
572 | ret = -EINVAL; | |
573 | if (sport->port.uartclk / 16 != ser->baud_base) | |
574 | ret = -EINVAL; | |
575 | if ((void *)sport->port.mapbase != ser->iomem_base) | |
576 | ret = -EINVAL; | |
577 | if (sport->port.iobase != ser->port) | |
578 | ret = -EINVAL; | |
579 | if (ser->hub6 != 0) | |
580 | ret = -EINVAL; | |
581 | return ret; | |
582 | } | |
583 | ||
584 | static struct uart_ops sa1100_pops = { | |
585 | .tx_empty = sa1100_tx_empty, | |
586 | .set_mctrl = sa1100_set_mctrl, | |
587 | .get_mctrl = sa1100_get_mctrl, | |
588 | .stop_tx = sa1100_stop_tx, | |
589 | .start_tx = sa1100_start_tx, | |
590 | .stop_rx = sa1100_stop_rx, | |
591 | .enable_ms = sa1100_enable_ms, | |
592 | .break_ctl = sa1100_break_ctl, | |
593 | .startup = sa1100_startup, | |
594 | .shutdown = sa1100_shutdown, | |
595 | .set_termios = sa1100_set_termios, | |
596 | .type = sa1100_type, | |
597 | .release_port = sa1100_release_port, | |
598 | .request_port = sa1100_request_port, | |
599 | .config_port = sa1100_config_port, | |
600 | .verify_port = sa1100_verify_port, | |
601 | }; | |
602 | ||
603 | static struct sa1100_port sa1100_ports[NR_PORTS]; | |
604 | ||
605 | /* | |
606 | * Setup the SA1100 serial ports. Note that we don't include the IrDA | |
607 | * port here since we have our own SIR/FIR driver (see drivers/net/irda) | |
608 | * | |
609 | * Note also that we support "console=ttySAx" where "x" is either 0 or 1. | |
610 | * Which serial port this ends up being depends on the machine you're | |
611 | * running this kernel on. I'm not convinced that this is a good idea, | |
612 | * but that's the way it traditionally works. | |
613 | * | |
614 | * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer | |
615 | * used here. | |
616 | */ | |
617 | static void __init sa1100_init_ports(void) | |
618 | { | |
619 | static int first = 1; | |
620 | int i; | |
621 | ||
622 | if (!first) | |
623 | return; | |
624 | first = 0; | |
625 | ||
626 | for (i = 0; i < NR_PORTS; i++) { | |
627 | sa1100_ports[i].port.uartclk = 3686400; | |
628 | sa1100_ports[i].port.ops = &sa1100_pops; | |
629 | sa1100_ports[i].port.fifosize = 8; | |
630 | sa1100_ports[i].port.line = i; | |
9b4a1617 | 631 | sa1100_ports[i].port.iotype = UPIO_MEM; |
1da177e4 LT |
632 | init_timer(&sa1100_ports[i].timer); |
633 | sa1100_ports[i].timer.function = sa1100_timeout; | |
634 | sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i]; | |
635 | } | |
636 | ||
637 | /* | |
638 | * make transmit lines outputs, so that when the port | |
639 | * is closed, the output is in the MARK state. | |
640 | */ | |
641 | PPDR |= PPC_TXD1 | PPC_TXD3; | |
642 | PPSR |= PPC_TXD1 | PPC_TXD3; | |
643 | } | |
644 | ||
645 | void __init sa1100_register_uart_fns(struct sa1100_port_fns *fns) | |
646 | { | |
647 | if (fns->get_mctrl) | |
648 | sa1100_pops.get_mctrl = fns->get_mctrl; | |
649 | if (fns->set_mctrl) | |
650 | sa1100_pops.set_mctrl = fns->set_mctrl; | |
651 | ||
652 | sa1100_pops.pm = fns->pm; | |
653 | sa1100_pops.set_wake = fns->set_wake; | |
654 | } | |
655 | ||
656 | void __init sa1100_register_uart(int idx, int port) | |
657 | { | |
658 | if (idx >= NR_PORTS) { | |
659 | printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx); | |
660 | return; | |
661 | } | |
662 | ||
663 | switch (port) { | |
664 | case 1: | |
665 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0; | |
666 | sa1100_ports[idx].port.mapbase = _Ser1UTCR0; | |
667 | sa1100_ports[idx].port.irq = IRQ_Ser1UART; | |
ce8337cb | 668 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
669 | break; |
670 | ||
671 | case 2: | |
672 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0; | |
673 | sa1100_ports[idx].port.mapbase = _Ser2UTCR0; | |
674 | sa1100_ports[idx].port.irq = IRQ_Ser2ICP; | |
ce8337cb | 675 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
676 | break; |
677 | ||
678 | case 3: | |
679 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0; | |
680 | sa1100_ports[idx].port.mapbase = _Ser3UTCR0; | |
681 | sa1100_ports[idx].port.irq = IRQ_Ser3UART; | |
ce8337cb | 682 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
683 | break; |
684 | ||
685 | default: | |
686 | printk(KERN_ERR "%s: bad port number %d\n", __FUNCTION__, port); | |
687 | } | |
688 | } | |
689 | ||
690 | ||
691 | #ifdef CONFIG_SERIAL_SA1100_CONSOLE | |
692 | ||
693 | /* | |
694 | * Interrupts are disabled on entering | |
695 | */ | |
696 | static void | |
697 | sa1100_console_write(struct console *co, const char *s, unsigned int count) | |
698 | { | |
699 | struct sa1100_port *sport = &sa1100_ports[co->index]; | |
700 | unsigned int old_utcr3, status, i; | |
701 | ||
702 | /* | |
703 | * First, save UTCR3 and then disable interrupts | |
704 | */ | |
705 | old_utcr3 = UART_GET_UTCR3(sport); | |
706 | UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) | | |
707 | UTCR3_TXE); | |
708 | ||
709 | /* | |
710 | * Now, do each character | |
711 | */ | |
712 | for (i = 0; i < count; i++) { | |
713 | do { | |
714 | status = UART_GET_UTSR1(sport); | |
715 | } while (!(status & UTSR1_TNF)); | |
716 | UART_PUT_CHAR(sport, s[i]); | |
717 | if (s[i] == '\n') { | |
718 | do { | |
719 | status = UART_GET_UTSR1(sport); | |
720 | } while (!(status & UTSR1_TNF)); | |
721 | UART_PUT_CHAR(sport, '\r'); | |
722 | } | |
723 | } | |
724 | ||
725 | /* | |
726 | * Finally, wait for transmitter to become empty | |
727 | * and restore UTCR3 | |
728 | */ | |
729 | do { | |
730 | status = UART_GET_UTSR1(sport); | |
731 | } while (status & UTSR1_TBY); | |
732 | UART_PUT_UTCR3(sport, old_utcr3); | |
733 | } | |
734 | ||
735 | /* | |
736 | * If the port was already initialised (eg, by a boot loader), | |
737 | * try to determine the current setup. | |
738 | */ | |
739 | static void __init | |
740 | sa1100_console_get_options(struct sa1100_port *sport, int *baud, | |
741 | int *parity, int *bits) | |
742 | { | |
743 | unsigned int utcr3; | |
744 | ||
745 | utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE); | |
746 | if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) { | |
747 | /* ok, the port was enabled */ | |
748 | unsigned int utcr0, quot; | |
749 | ||
750 | utcr0 = UART_GET_UTCR0(sport); | |
751 | ||
752 | *parity = 'n'; | |
753 | if (utcr0 & UTCR0_PE) { | |
754 | if (utcr0 & UTCR0_OES) | |
755 | *parity = 'e'; | |
756 | else | |
757 | *parity = 'o'; | |
758 | } | |
759 | ||
760 | if (utcr0 & UTCR0_DSS) | |
761 | *bits = 8; | |
762 | else | |
763 | *bits = 7; | |
764 | ||
765 | quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8; | |
766 | quot &= 0xfff; | |
767 | *baud = sport->port.uartclk / (16 * (quot + 1)); | |
768 | } | |
769 | } | |
770 | ||
771 | static int __init | |
772 | sa1100_console_setup(struct console *co, char *options) | |
773 | { | |
774 | struct sa1100_port *sport; | |
775 | int baud = 9600; | |
776 | int bits = 8; | |
777 | int parity = 'n'; | |
778 | int flow = 'n'; | |
779 | ||
780 | /* | |
781 | * Check whether an invalid uart number has been specified, and | |
782 | * if so, search for the first available port that does have | |
783 | * console support. | |
784 | */ | |
785 | if (co->index == -1 || co->index >= NR_PORTS) | |
786 | co->index = 0; | |
787 | sport = &sa1100_ports[co->index]; | |
788 | ||
789 | if (options) | |
790 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
791 | else | |
792 | sa1100_console_get_options(sport, &baud, &parity, &bits); | |
793 | ||
794 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); | |
795 | } | |
796 | ||
2d93486c | 797 | static struct uart_driver sa1100_reg; |
1da177e4 LT |
798 | static struct console sa1100_console = { |
799 | .name = "ttySA", | |
800 | .write = sa1100_console_write, | |
801 | .device = uart_console_device, | |
802 | .setup = sa1100_console_setup, | |
803 | .flags = CON_PRINTBUFFER, | |
804 | .index = -1, | |
805 | .data = &sa1100_reg, | |
806 | }; | |
807 | ||
808 | static int __init sa1100_rs_console_init(void) | |
809 | { | |
810 | sa1100_init_ports(); | |
811 | register_console(&sa1100_console); | |
812 | return 0; | |
813 | } | |
814 | console_initcall(sa1100_rs_console_init); | |
815 | ||
816 | #define SA1100_CONSOLE &sa1100_console | |
817 | #else | |
818 | #define SA1100_CONSOLE NULL | |
819 | #endif | |
820 | ||
821 | static struct uart_driver sa1100_reg = { | |
822 | .owner = THIS_MODULE, | |
823 | .driver_name = "ttySA", | |
824 | .dev_name = "ttySA", | |
825 | .devfs_name = "ttySA", | |
826 | .major = SERIAL_SA1100_MAJOR, | |
827 | .minor = MINOR_START, | |
828 | .nr = NR_PORTS, | |
829 | .cons = SA1100_CONSOLE, | |
830 | }; | |
831 | ||
3ae5eaec | 832 | static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 833 | { |
3ae5eaec | 834 | struct sa1100_port *sport = platform_get_drvdata(dev); |
1da177e4 | 835 | |
9480e307 | 836 | if (sport) |
1da177e4 LT |
837 | uart_suspend_port(&sa1100_reg, &sport->port); |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
3ae5eaec | 842 | static int sa1100_serial_resume(struct platform_device *dev) |
1da177e4 | 843 | { |
3ae5eaec | 844 | struct sa1100_port *sport = platform_get_drvdata(dev); |
1da177e4 | 845 | |
9480e307 | 846 | if (sport) |
1da177e4 LT |
847 | uart_resume_port(&sa1100_reg, &sport->port); |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
3ae5eaec | 852 | static int sa1100_serial_probe(struct platform_device *dev) |
1da177e4 | 853 | { |
1da177e4 LT |
854 | struct resource *res = dev->resource; |
855 | int i; | |
856 | ||
857 | for (i = 0; i < dev->num_resources; i++, res++) | |
858 | if (res->flags & IORESOURCE_MEM) | |
859 | break; | |
860 | ||
861 | if (i < dev->num_resources) { | |
862 | for (i = 0; i < NR_PORTS; i++) { | |
863 | if (sa1100_ports[i].port.mapbase != res->start) | |
864 | continue; | |
865 | ||
3ae5eaec | 866 | sa1100_ports[i].port.dev = &dev->dev; |
1da177e4 | 867 | uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port); |
3ae5eaec | 868 | platform_set_drvdata(dev, &sa1100_ports[i]); |
1da177e4 LT |
869 | break; |
870 | } | |
871 | } | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
3ae5eaec | 876 | static int sa1100_serial_remove(struct platform_device *pdev) |
1da177e4 | 877 | { |
3ae5eaec | 878 | struct sa1100_port *sport = platform_get_drvdata(pdev); |
1da177e4 | 879 | |
3ae5eaec | 880 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
881 | |
882 | if (sport) | |
883 | uart_remove_one_port(&sa1100_reg, &sport->port); | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
3ae5eaec | 888 | static struct platform_driver sa11x0_serial_driver = { |
1da177e4 LT |
889 | .probe = sa1100_serial_probe, |
890 | .remove = sa1100_serial_remove, | |
891 | .suspend = sa1100_serial_suspend, | |
892 | .resume = sa1100_serial_resume, | |
3ae5eaec RK |
893 | .driver = { |
894 | .name = "sa11x0-uart", | |
895 | }, | |
1da177e4 LT |
896 | }; |
897 | ||
898 | static int __init sa1100_serial_init(void) | |
899 | { | |
900 | int ret; | |
901 | ||
902 | printk(KERN_INFO "Serial: SA11x0 driver $Revision: 1.50 $\n"); | |
903 | ||
904 | sa1100_init_ports(); | |
905 | ||
906 | ret = uart_register_driver(&sa1100_reg); | |
907 | if (ret == 0) { | |
3ae5eaec | 908 | ret = platform_driver_register(&sa11x0_serial_driver); |
1da177e4 LT |
909 | if (ret) |
910 | uart_unregister_driver(&sa1100_reg); | |
911 | } | |
912 | return ret; | |
913 | } | |
914 | ||
915 | static void __exit sa1100_serial_exit(void) | |
916 | { | |
3ae5eaec | 917 | platform_driver_unregister(&sa11x0_serial_driver); |
1da177e4 LT |
918 | uart_unregister_driver(&sa1100_reg); |
919 | } | |
920 | ||
921 | module_init(sa1100_serial_init); | |
922 | module_exit(sa1100_serial_exit); | |
923 | ||
924 | MODULE_AUTHOR("Deep Blue Solutions Ltd"); | |
925 | MODULE_DESCRIPTION("SA1100 generic serial port driver $Revision: 1.50 $"); | |
926 | MODULE_LICENSE("GPL"); | |
927 | MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR); |