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b497549a BD |
1 | /* linux/drivers/serial/samsuing.c |
2 | * | |
3 | * Driver core for Samsung SoC onboard UARTs. | |
4 | * | |
5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* Hote on 2410 error handling | |
14 | * | |
15 | * The s3c2410 manual has a love/hate affair with the contents of the | |
16 | * UERSTAT register in the UART blocks, and keeps marking some of the | |
17 | * error bits as reserved. Having checked with the s3c2410x01, | |
18 | * it copes with BREAKs properly, so I am happy to ignore the RESERVED | |
19 | * feature from the latter versions of the manual. | |
20 | * | |
21 | * If it becomes aparrent that latter versions of the 2410 remove these | |
22 | * bits, then action will have to be taken to differentiate the versions | |
23 | * and change the policy on BREAK | |
24 | * | |
25 | * BJD, 04-Nov-2004 | |
26 | */ | |
27 | ||
28 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
29 | #define SUPPORT_SYSRQ | |
30 | #endif | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/io.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/sysrq.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/tty.h> | |
40 | #include <linux/tty_flip.h> | |
41 | #include <linux/serial_core.h> | |
42 | #include <linux/serial.h> | |
43 | #include <linux/delay.h> | |
44 | #include <linux/clk.h> | |
30555476 | 45 | #include <linux/cpufreq.h> |
b497549a BD |
46 | |
47 | #include <asm/irq.h> | |
48 | ||
a09e64fb | 49 | #include <mach/hardware.h> |
b497549a | 50 | |
a2b7ba9c | 51 | #include <plat/regs-serial.h> |
a09e64fb | 52 | #include <mach/regs-gpio.h> |
b497549a BD |
53 | |
54 | #include "samsung.h" | |
55 | ||
56 | /* UART name and device definitions */ | |
57 | ||
58 | #define S3C24XX_SERIAL_NAME "ttySAC" | |
59 | #define S3C24XX_SERIAL_MAJOR 204 | |
60 | #define S3C24XX_SERIAL_MINOR 64 | |
61 | ||
62 | /* we can support 3 uarts, but not always use them */ | |
63 | ||
1d4bab08 | 64 | #if defined(CONFIG_CPU_S3C2400) || defined(CONFIG_CPU_S3C24A0) |
b497549a BD |
65 | #define NR_PORTS (2) |
66 | #else | |
67 | #define NR_PORTS (3) | |
68 | #endif | |
69 | ||
70 | /* port irq numbers */ | |
71 | ||
72 | #define TX_IRQ(port) ((port)->irq + 1) | |
73 | #define RX_IRQ(port) ((port)->irq) | |
74 | ||
75 | /* macros to change one thing to another */ | |
76 | ||
77 | #define tx_enabled(port) ((port)->unused[0]) | |
78 | #define rx_enabled(port) ((port)->unused[1]) | |
79 | ||
80 | /* flag to ignore all characters comming in */ | |
81 | #define RXSTAT_DUMMY_READ (0x10000000) | |
82 | ||
83 | static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) | |
84 | { | |
85 | return container_of(port, struct s3c24xx_uart_port, port); | |
86 | } | |
87 | ||
88 | /* translate a port to the device name */ | |
89 | ||
90 | static inline const char *s3c24xx_serial_portname(struct uart_port *port) | |
91 | { | |
92 | return to_platform_device(port->dev)->name; | |
93 | } | |
94 | ||
95 | static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) | |
96 | { | |
97 | return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE); | |
98 | } | |
99 | ||
100 | static void s3c24xx_serial_rx_enable(struct uart_port *port) | |
101 | { | |
102 | unsigned long flags; | |
103 | unsigned int ucon, ufcon; | |
104 | int count = 10000; | |
105 | ||
106 | spin_lock_irqsave(&port->lock, flags); | |
107 | ||
108 | while (--count && !s3c24xx_serial_txempty_nofifo(port)) | |
109 | udelay(100); | |
110 | ||
111 | ufcon = rd_regl(port, S3C2410_UFCON); | |
112 | ufcon |= S3C2410_UFCON_RESETRX; | |
113 | wr_regl(port, S3C2410_UFCON, ufcon); | |
114 | ||
115 | ucon = rd_regl(port, S3C2410_UCON); | |
116 | ucon |= S3C2410_UCON_RXIRQMODE; | |
117 | wr_regl(port, S3C2410_UCON, ucon); | |
118 | ||
119 | rx_enabled(port) = 1; | |
120 | spin_unlock_irqrestore(&port->lock, flags); | |
121 | } | |
122 | ||
123 | static void s3c24xx_serial_rx_disable(struct uart_port *port) | |
124 | { | |
125 | unsigned long flags; | |
126 | unsigned int ucon; | |
127 | ||
128 | spin_lock_irqsave(&port->lock, flags); | |
129 | ||
130 | ucon = rd_regl(port, S3C2410_UCON); | |
131 | ucon &= ~S3C2410_UCON_RXIRQMODE; | |
132 | wr_regl(port, S3C2410_UCON, ucon); | |
133 | ||
134 | rx_enabled(port) = 0; | |
135 | spin_unlock_irqrestore(&port->lock, flags); | |
136 | } | |
137 | ||
138 | static void s3c24xx_serial_stop_tx(struct uart_port *port) | |
139 | { | |
140 | if (tx_enabled(port)) { | |
141 | disable_irq(TX_IRQ(port)); | |
142 | tx_enabled(port) = 0; | |
143 | if (port->flags & UPF_CONS_FLOW) | |
144 | s3c24xx_serial_rx_enable(port); | |
145 | } | |
146 | } | |
147 | ||
148 | static void s3c24xx_serial_start_tx(struct uart_port *port) | |
149 | { | |
150 | if (!tx_enabled(port)) { | |
151 | if (port->flags & UPF_CONS_FLOW) | |
152 | s3c24xx_serial_rx_disable(port); | |
153 | ||
154 | enable_irq(TX_IRQ(port)); | |
155 | tx_enabled(port) = 1; | |
156 | } | |
157 | } | |
158 | ||
159 | ||
160 | static void s3c24xx_serial_stop_rx(struct uart_port *port) | |
161 | { | |
162 | if (rx_enabled(port)) { | |
163 | dbg("s3c24xx_serial_stop_rx: port=%p\n", port); | |
164 | disable_irq(RX_IRQ(port)); | |
165 | rx_enabled(port) = 0; | |
166 | } | |
167 | } | |
168 | ||
169 | static void s3c24xx_serial_enable_ms(struct uart_port *port) | |
170 | { | |
171 | } | |
172 | ||
173 | static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port) | |
174 | { | |
175 | return to_ourport(port)->info; | |
176 | } | |
177 | ||
178 | static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port) | |
179 | { | |
180 | if (port->dev == NULL) | |
181 | return NULL; | |
182 | ||
183 | return (struct s3c2410_uartcfg *)port->dev->platform_data; | |
184 | } | |
185 | ||
186 | static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, | |
187 | unsigned long ufstat) | |
188 | { | |
189 | struct s3c24xx_uart_info *info = ourport->info; | |
190 | ||
191 | if (ufstat & info->rx_fifofull) | |
192 | return info->fifosize; | |
193 | ||
194 | return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; | |
195 | } | |
196 | ||
197 | ||
198 | /* ? - where has parity gone?? */ | |
199 | #define S3C2410_UERSTAT_PARITY (0x1000) | |
200 | ||
201 | static irqreturn_t | |
202 | s3c24xx_serial_rx_chars(int irq, void *dev_id) | |
203 | { | |
204 | struct s3c24xx_uart_port *ourport = dev_id; | |
205 | struct uart_port *port = &ourport->port; | |
f10140fb | 206 | struct tty_struct *tty = port->info->port.tty; |
b497549a BD |
207 | unsigned int ufcon, ch, flag, ufstat, uerstat; |
208 | int max_count = 64; | |
209 | ||
210 | while (max_count-- > 0) { | |
211 | ufcon = rd_regl(port, S3C2410_UFCON); | |
212 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
213 | ||
214 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) | |
215 | break; | |
216 | ||
217 | uerstat = rd_regl(port, S3C2410_UERSTAT); | |
218 | ch = rd_regb(port, S3C2410_URXH); | |
219 | ||
220 | if (port->flags & UPF_CONS_FLOW) { | |
221 | int txe = s3c24xx_serial_txempty_nofifo(port); | |
222 | ||
223 | if (rx_enabled(port)) { | |
224 | if (!txe) { | |
225 | rx_enabled(port) = 0; | |
226 | continue; | |
227 | } | |
228 | } else { | |
229 | if (txe) { | |
230 | ufcon |= S3C2410_UFCON_RESETRX; | |
231 | wr_regl(port, S3C2410_UFCON, ufcon); | |
232 | rx_enabled(port) = 1; | |
233 | goto out; | |
234 | } | |
235 | continue; | |
236 | } | |
237 | } | |
238 | ||
239 | /* insert the character into the buffer */ | |
240 | ||
241 | flag = TTY_NORMAL; | |
242 | port->icount.rx++; | |
243 | ||
244 | if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { | |
245 | dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", | |
246 | ch, uerstat); | |
247 | ||
248 | /* check for break */ | |
249 | if (uerstat & S3C2410_UERSTAT_BREAK) { | |
250 | dbg("break!\n"); | |
251 | port->icount.brk++; | |
252 | if (uart_handle_break(port)) | |
253 | goto ignore_char; | |
254 | } | |
255 | ||
256 | if (uerstat & S3C2410_UERSTAT_FRAME) | |
257 | port->icount.frame++; | |
258 | if (uerstat & S3C2410_UERSTAT_OVERRUN) | |
259 | port->icount.overrun++; | |
260 | ||
261 | uerstat &= port->read_status_mask; | |
262 | ||
263 | if (uerstat & S3C2410_UERSTAT_BREAK) | |
264 | flag = TTY_BREAK; | |
265 | else if (uerstat & S3C2410_UERSTAT_PARITY) | |
266 | flag = TTY_PARITY; | |
267 | else if (uerstat & (S3C2410_UERSTAT_FRAME | | |
268 | S3C2410_UERSTAT_OVERRUN)) | |
269 | flag = TTY_FRAME; | |
270 | } | |
271 | ||
272 | if (uart_handle_sysrq_char(port, ch)) | |
273 | goto ignore_char; | |
274 | ||
275 | uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, | |
276 | ch, flag); | |
277 | ||
278 | ignore_char: | |
279 | continue; | |
280 | } | |
281 | tty_flip_buffer_push(tty); | |
282 | ||
283 | out: | |
284 | return IRQ_HANDLED; | |
285 | } | |
286 | ||
287 | static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) | |
288 | { | |
289 | struct s3c24xx_uart_port *ourport = id; | |
290 | struct uart_port *port = &ourport->port; | |
291 | struct circ_buf *xmit = &port->info->xmit; | |
292 | int count = 256; | |
293 | ||
294 | if (port->x_char) { | |
295 | wr_regb(port, S3C2410_UTXH, port->x_char); | |
296 | port->icount.tx++; | |
297 | port->x_char = 0; | |
298 | goto out; | |
299 | } | |
300 | ||
301 | /* if there isnt anything more to transmit, or the uart is now | |
302 | * stopped, disable the uart and exit | |
303 | */ | |
304 | ||
305 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
306 | s3c24xx_serial_stop_tx(port); | |
307 | goto out; | |
308 | } | |
309 | ||
310 | /* try and drain the buffer... */ | |
311 | ||
312 | while (!uart_circ_empty(xmit) && count-- > 0) { | |
313 | if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) | |
314 | break; | |
315 | ||
316 | wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); | |
317 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
318 | port->icount.tx++; | |
319 | } | |
320 | ||
321 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
322 | uart_write_wakeup(port); | |
323 | ||
324 | if (uart_circ_empty(xmit)) | |
325 | s3c24xx_serial_stop_tx(port); | |
326 | ||
327 | out: | |
328 | return IRQ_HANDLED; | |
329 | } | |
330 | ||
331 | static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) | |
332 | { | |
333 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
334 | unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); | |
335 | unsigned long ufcon = rd_regl(port, S3C2410_UFCON); | |
336 | ||
337 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | |
338 | if ((ufstat & info->tx_fifomask) != 0 || | |
339 | (ufstat & info->tx_fifofull)) | |
340 | return 0; | |
341 | ||
342 | return 1; | |
343 | } | |
344 | ||
345 | return s3c24xx_serial_txempty_nofifo(port); | |
346 | } | |
347 | ||
348 | /* no modem control lines */ | |
349 | static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) | |
350 | { | |
351 | unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); | |
352 | ||
353 | if (umstat & S3C2410_UMSTAT_CTS) | |
354 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
355 | else | |
356 | return TIOCM_CAR | TIOCM_DSR; | |
357 | } | |
358 | ||
359 | static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
360 | { | |
361 | /* todo - possibly remove AFC and do manual CTS */ | |
362 | } | |
363 | ||
364 | static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) | |
365 | { | |
366 | unsigned long flags; | |
367 | unsigned int ucon; | |
368 | ||
369 | spin_lock_irqsave(&port->lock, flags); | |
370 | ||
371 | ucon = rd_regl(port, S3C2410_UCON); | |
372 | ||
373 | if (break_state) | |
374 | ucon |= S3C2410_UCON_SBREAK; | |
375 | else | |
376 | ucon &= ~S3C2410_UCON_SBREAK; | |
377 | ||
378 | wr_regl(port, S3C2410_UCON, ucon); | |
379 | ||
380 | spin_unlock_irqrestore(&port->lock, flags); | |
381 | } | |
382 | ||
383 | static void s3c24xx_serial_shutdown(struct uart_port *port) | |
384 | { | |
385 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
386 | ||
387 | if (ourport->tx_claimed) { | |
388 | free_irq(TX_IRQ(port), ourport); | |
389 | tx_enabled(port) = 0; | |
390 | ourport->tx_claimed = 0; | |
391 | } | |
392 | ||
393 | if (ourport->rx_claimed) { | |
394 | free_irq(RX_IRQ(port), ourport); | |
395 | ourport->rx_claimed = 0; | |
396 | rx_enabled(port) = 0; | |
397 | } | |
398 | } | |
399 | ||
400 | ||
401 | static int s3c24xx_serial_startup(struct uart_port *port) | |
402 | { | |
403 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
404 | int ret; | |
405 | ||
406 | dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n", | |
407 | port->mapbase, port->membase); | |
408 | ||
409 | rx_enabled(port) = 1; | |
410 | ||
411 | ret = request_irq(RX_IRQ(port), | |
412 | s3c24xx_serial_rx_chars, 0, | |
413 | s3c24xx_serial_portname(port), ourport); | |
414 | ||
415 | if (ret != 0) { | |
416 | printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port)); | |
417 | return ret; | |
418 | } | |
419 | ||
420 | ourport->rx_claimed = 1; | |
421 | ||
422 | dbg("requesting tx irq...\n"); | |
423 | ||
424 | tx_enabled(port) = 1; | |
425 | ||
426 | ret = request_irq(TX_IRQ(port), | |
427 | s3c24xx_serial_tx_chars, 0, | |
428 | s3c24xx_serial_portname(port), ourport); | |
429 | ||
430 | if (ret) { | |
431 | printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port)); | |
432 | goto err; | |
433 | } | |
434 | ||
435 | ourport->tx_claimed = 1; | |
436 | ||
437 | dbg("s3c24xx_serial_startup ok\n"); | |
438 | ||
439 | /* the port reset code should have done the correct | |
440 | * register setup for the port controls */ | |
441 | ||
442 | return ret; | |
443 | ||
444 | err: | |
445 | s3c24xx_serial_shutdown(port); | |
446 | return ret; | |
447 | } | |
448 | ||
449 | /* power power management control */ | |
450 | ||
451 | static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, | |
452 | unsigned int old) | |
453 | { | |
454 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
455 | ||
30555476 BD |
456 | ourport->pm_level = level; |
457 | ||
b497549a BD |
458 | switch (level) { |
459 | case 3: | |
460 | if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) | |
461 | clk_disable(ourport->baudclk); | |
462 | ||
463 | clk_disable(ourport->clk); | |
464 | break; | |
465 | ||
466 | case 0: | |
467 | clk_enable(ourport->clk); | |
468 | ||
469 | if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) | |
470 | clk_enable(ourport->baudclk); | |
471 | ||
472 | break; | |
473 | default: | |
474 | printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level); | |
475 | } | |
476 | } | |
477 | ||
478 | /* baud rate calculation | |
479 | * | |
480 | * The UARTs on the S3C2410/S3C2440 can take their clocks from a number | |
481 | * of different sources, including the peripheral clock ("pclk") and an | |
482 | * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") | |
483 | * with a programmable extra divisor. | |
484 | * | |
485 | * The following code goes through the clock sources, and calculates the | |
486 | * baud clocks (and the resultant actual baud rates) and then tries to | |
487 | * pick the closest one and select that. | |
488 | * | |
489 | */ | |
490 | ||
491 | ||
492 | #define MAX_CLKS (8) | |
493 | ||
494 | static struct s3c24xx_uart_clksrc tmp_clksrc = { | |
495 | .name = "pclk", | |
496 | .min_baud = 0, | |
497 | .max_baud = 0, | |
498 | .divisor = 1, | |
499 | }; | |
500 | ||
501 | static inline int | |
502 | s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) | |
503 | { | |
504 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
505 | ||
506 | return (info->get_clksrc)(port, c); | |
507 | } | |
508 | ||
509 | static inline int | |
510 | s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) | |
511 | { | |
512 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
513 | ||
514 | return (info->set_clksrc)(port, c); | |
515 | } | |
516 | ||
517 | struct baud_calc { | |
518 | struct s3c24xx_uart_clksrc *clksrc; | |
519 | unsigned int calc; | |
520 | unsigned int quot; | |
521 | struct clk *src; | |
522 | }; | |
523 | ||
524 | static int s3c24xx_serial_calcbaud(struct baud_calc *calc, | |
525 | struct uart_port *port, | |
526 | struct s3c24xx_uart_clksrc *clksrc, | |
527 | unsigned int baud) | |
528 | { | |
529 | unsigned long rate; | |
530 | ||
531 | calc->src = clk_get(port->dev, clksrc->name); | |
532 | if (calc->src == NULL || IS_ERR(calc->src)) | |
533 | return 0; | |
534 | ||
535 | rate = clk_get_rate(calc->src); | |
536 | rate /= clksrc->divisor; | |
537 | ||
538 | calc->clksrc = clksrc; | |
539 | calc->quot = (rate + (8 * baud)) / (16 * baud); | |
540 | calc->calc = (rate / (calc->quot * 16)); | |
541 | ||
542 | calc->quot--; | |
543 | return 1; | |
544 | } | |
545 | ||
546 | static unsigned int s3c24xx_serial_getclk(struct uart_port *port, | |
547 | struct s3c24xx_uart_clksrc **clksrc, | |
548 | struct clk **clk, | |
549 | unsigned int baud) | |
550 | { | |
551 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | |
552 | struct s3c24xx_uart_clksrc *clkp; | |
553 | struct baud_calc res[MAX_CLKS]; | |
554 | struct baud_calc *resptr, *best, *sptr; | |
555 | int i; | |
556 | ||
557 | clkp = cfg->clocks; | |
558 | best = NULL; | |
559 | ||
560 | if (cfg->clocks_size < 2) { | |
561 | if (cfg->clocks_size == 0) | |
562 | clkp = &tmp_clksrc; | |
563 | ||
564 | /* check to see if we're sourcing fclk, and if so we're | |
565 | * going to have to update the clock source | |
566 | */ | |
567 | ||
568 | if (strcmp(clkp->name, "fclk") == 0) { | |
569 | struct s3c24xx_uart_clksrc src; | |
570 | ||
571 | s3c24xx_serial_getsource(port, &src); | |
572 | ||
573 | /* check that the port already using fclk, and if | |
574 | * not, then re-select fclk | |
575 | */ | |
576 | ||
577 | if (strcmp(src.name, clkp->name) == 0) { | |
578 | s3c24xx_serial_setsource(port, clkp); | |
579 | s3c24xx_serial_getsource(port, &src); | |
580 | } | |
581 | ||
582 | clkp->divisor = src.divisor; | |
583 | } | |
584 | ||
585 | s3c24xx_serial_calcbaud(res, port, clkp, baud); | |
586 | best = res; | |
587 | resptr = best + 1; | |
588 | } else { | |
589 | resptr = res; | |
590 | ||
591 | for (i = 0; i < cfg->clocks_size; i++, clkp++) { | |
592 | if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud)) | |
593 | resptr++; | |
594 | } | |
595 | } | |
596 | ||
597 | /* ok, we now need to select the best clock we found */ | |
598 | ||
599 | if (!best) { | |
600 | unsigned int deviation = (1<<30)|((1<<30)-1); | |
601 | int calc_deviation; | |
602 | ||
603 | for (sptr = res; sptr < resptr; sptr++) { | |
604 | calc_deviation = baud - sptr->calc; | |
605 | if (calc_deviation < 0) | |
606 | calc_deviation = -calc_deviation; | |
607 | ||
608 | if (calc_deviation < deviation) { | |
609 | best = sptr; | |
610 | deviation = calc_deviation; | |
611 | } | |
612 | } | |
613 | } | |
614 | ||
615 | /* store results to pass back */ | |
616 | ||
617 | *clksrc = best->clksrc; | |
618 | *clk = best->src; | |
619 | ||
620 | return best->quot; | |
621 | } | |
622 | ||
623 | static void s3c24xx_serial_set_termios(struct uart_port *port, | |
624 | struct ktermios *termios, | |
625 | struct ktermios *old) | |
626 | { | |
627 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | |
628 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
629 | struct s3c24xx_uart_clksrc *clksrc = NULL; | |
630 | struct clk *clk = NULL; | |
631 | unsigned long flags; | |
632 | unsigned int baud, quot; | |
633 | unsigned int ulcon; | |
634 | unsigned int umcon; | |
635 | ||
636 | /* | |
637 | * We don't support modem control lines. | |
638 | */ | |
639 | termios->c_cflag &= ~(HUPCL | CMSPAR); | |
640 | termios->c_cflag |= CLOCAL; | |
641 | ||
642 | /* | |
643 | * Ask the core to calculate the divisor for us. | |
644 | */ | |
645 | ||
646 | baud = uart_get_baud_rate(port, termios, old, 0, 115200*8); | |
647 | ||
648 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) | |
649 | quot = port->custom_divisor; | |
650 | else | |
651 | quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud); | |
652 | ||
653 | /* check to see if we need to change clock source */ | |
654 | ||
655 | if (ourport->clksrc != clksrc || ourport->baudclk != clk) { | |
656 | s3c24xx_serial_setsource(port, clksrc); | |
657 | ||
658 | if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) { | |
659 | clk_disable(ourport->baudclk); | |
660 | ourport->baudclk = NULL; | |
661 | } | |
662 | ||
663 | clk_enable(clk); | |
664 | ||
665 | ourport->clksrc = clksrc; | |
666 | ourport->baudclk = clk; | |
30555476 | 667 | ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; |
b497549a BD |
668 | } |
669 | ||
670 | switch (termios->c_cflag & CSIZE) { | |
671 | case CS5: | |
672 | dbg("config: 5bits/char\n"); | |
673 | ulcon = S3C2410_LCON_CS5; | |
674 | break; | |
675 | case CS6: | |
676 | dbg("config: 6bits/char\n"); | |
677 | ulcon = S3C2410_LCON_CS6; | |
678 | break; | |
679 | case CS7: | |
680 | dbg("config: 7bits/char\n"); | |
681 | ulcon = S3C2410_LCON_CS7; | |
682 | break; | |
683 | case CS8: | |
684 | default: | |
685 | dbg("config: 8bits/char\n"); | |
686 | ulcon = S3C2410_LCON_CS8; | |
687 | break; | |
688 | } | |
689 | ||
690 | /* preserve original lcon IR settings */ | |
691 | ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); | |
692 | ||
693 | if (termios->c_cflag & CSTOPB) | |
694 | ulcon |= S3C2410_LCON_STOPB; | |
695 | ||
696 | umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0; | |
697 | ||
698 | if (termios->c_cflag & PARENB) { | |
699 | if (termios->c_cflag & PARODD) | |
700 | ulcon |= S3C2410_LCON_PODD; | |
701 | else | |
702 | ulcon |= S3C2410_LCON_PEVEN; | |
703 | } else { | |
704 | ulcon |= S3C2410_LCON_PNONE; | |
705 | } | |
706 | ||
707 | spin_lock_irqsave(&port->lock, flags); | |
708 | ||
709 | dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot); | |
710 | ||
711 | wr_regl(port, S3C2410_ULCON, ulcon); | |
712 | wr_regl(port, S3C2410_UBRDIV, quot); | |
713 | wr_regl(port, S3C2410_UMCON, umcon); | |
714 | ||
715 | dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", | |
716 | rd_regl(port, S3C2410_ULCON), | |
717 | rd_regl(port, S3C2410_UCON), | |
718 | rd_regl(port, S3C2410_UFCON)); | |
719 | ||
720 | /* | |
721 | * Update the per-port timeout. | |
722 | */ | |
723 | uart_update_timeout(port, termios->c_cflag, baud); | |
724 | ||
725 | /* | |
726 | * Which character status flags are we interested in? | |
727 | */ | |
728 | port->read_status_mask = S3C2410_UERSTAT_OVERRUN; | |
729 | if (termios->c_iflag & INPCK) | |
730 | port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY; | |
731 | ||
732 | /* | |
733 | * Which character status flags should we ignore? | |
734 | */ | |
735 | port->ignore_status_mask = 0; | |
736 | if (termios->c_iflag & IGNPAR) | |
737 | port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; | |
738 | if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) | |
739 | port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; | |
740 | ||
741 | /* | |
742 | * Ignore all characters if CREAD is not set. | |
743 | */ | |
744 | if ((termios->c_cflag & CREAD) == 0) | |
745 | port->ignore_status_mask |= RXSTAT_DUMMY_READ; | |
746 | ||
747 | spin_unlock_irqrestore(&port->lock, flags); | |
748 | } | |
749 | ||
750 | static const char *s3c24xx_serial_type(struct uart_port *port) | |
751 | { | |
752 | switch (port->type) { | |
753 | case PORT_S3C2410: | |
754 | return "S3C2410"; | |
755 | case PORT_S3C2440: | |
756 | return "S3C2440"; | |
757 | case PORT_S3C2412: | |
758 | return "S3C2412"; | |
759 | default: | |
760 | return NULL; | |
761 | } | |
762 | } | |
763 | ||
764 | #define MAP_SIZE (0x100) | |
765 | ||
766 | static void s3c24xx_serial_release_port(struct uart_port *port) | |
767 | { | |
768 | release_mem_region(port->mapbase, MAP_SIZE); | |
769 | } | |
770 | ||
771 | static int s3c24xx_serial_request_port(struct uart_port *port) | |
772 | { | |
773 | const char *name = s3c24xx_serial_portname(port); | |
774 | return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY; | |
775 | } | |
776 | ||
777 | static void s3c24xx_serial_config_port(struct uart_port *port, int flags) | |
778 | { | |
779 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
780 | ||
781 | if (flags & UART_CONFIG_TYPE && | |
782 | s3c24xx_serial_request_port(port) == 0) | |
783 | port->type = info->type; | |
784 | } | |
785 | ||
786 | /* | |
787 | * verify the new serial_struct (for TIOCSSERIAL). | |
788 | */ | |
789 | static int | |
790 | s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
791 | { | |
792 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
793 | ||
794 | if (ser->type != PORT_UNKNOWN && ser->type != info->type) | |
795 | return -EINVAL; | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | ||
801 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | |
802 | ||
803 | static struct console s3c24xx_serial_console; | |
804 | ||
805 | #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console | |
806 | #else | |
807 | #define S3C24XX_SERIAL_CONSOLE NULL | |
808 | #endif | |
809 | ||
810 | static struct uart_ops s3c24xx_serial_ops = { | |
811 | .pm = s3c24xx_serial_pm, | |
812 | .tx_empty = s3c24xx_serial_tx_empty, | |
813 | .get_mctrl = s3c24xx_serial_get_mctrl, | |
814 | .set_mctrl = s3c24xx_serial_set_mctrl, | |
815 | .stop_tx = s3c24xx_serial_stop_tx, | |
816 | .start_tx = s3c24xx_serial_start_tx, | |
817 | .stop_rx = s3c24xx_serial_stop_rx, | |
818 | .enable_ms = s3c24xx_serial_enable_ms, | |
819 | .break_ctl = s3c24xx_serial_break_ctl, | |
820 | .startup = s3c24xx_serial_startup, | |
821 | .shutdown = s3c24xx_serial_shutdown, | |
822 | .set_termios = s3c24xx_serial_set_termios, | |
823 | .type = s3c24xx_serial_type, | |
824 | .release_port = s3c24xx_serial_release_port, | |
825 | .request_port = s3c24xx_serial_request_port, | |
826 | .config_port = s3c24xx_serial_config_port, | |
827 | .verify_port = s3c24xx_serial_verify_port, | |
828 | }; | |
829 | ||
830 | ||
831 | static struct uart_driver s3c24xx_uart_drv = { | |
832 | .owner = THIS_MODULE, | |
833 | .dev_name = "s3c2410_serial", | |
834 | .nr = 3, | |
835 | .cons = S3C24XX_SERIAL_CONSOLE, | |
836 | .driver_name = S3C24XX_SERIAL_NAME, | |
837 | .major = S3C24XX_SERIAL_MAJOR, | |
838 | .minor = S3C24XX_SERIAL_MINOR, | |
839 | }; | |
840 | ||
841 | static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = { | |
842 | [0] = { | |
843 | .port = { | |
844 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock), | |
845 | .iotype = UPIO_MEM, | |
846 | .irq = IRQ_S3CUART_RX0, | |
847 | .uartclk = 0, | |
848 | .fifosize = 16, | |
849 | .ops = &s3c24xx_serial_ops, | |
850 | .flags = UPF_BOOT_AUTOCONF, | |
851 | .line = 0, | |
852 | } | |
853 | }, | |
854 | [1] = { | |
855 | .port = { | |
856 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock), | |
857 | .iotype = UPIO_MEM, | |
858 | .irq = IRQ_S3CUART_RX1, | |
859 | .uartclk = 0, | |
860 | .fifosize = 16, | |
861 | .ops = &s3c24xx_serial_ops, | |
862 | .flags = UPF_BOOT_AUTOCONF, | |
863 | .line = 1, | |
864 | } | |
865 | }, | |
866 | #if NR_PORTS > 2 | |
867 | ||
868 | [2] = { | |
869 | .port = { | |
870 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock), | |
871 | .iotype = UPIO_MEM, | |
872 | .irq = IRQ_S3CUART_RX2, | |
873 | .uartclk = 0, | |
874 | .fifosize = 16, | |
875 | .ops = &s3c24xx_serial_ops, | |
876 | .flags = UPF_BOOT_AUTOCONF, | |
877 | .line = 2, | |
878 | } | |
879 | } | |
880 | #endif | |
881 | }; | |
882 | ||
883 | /* s3c24xx_serial_resetport | |
884 | * | |
885 | * wrapper to call the specific reset for this port (reset the fifos | |
886 | * and the settings) | |
887 | */ | |
888 | ||
889 | static inline int s3c24xx_serial_resetport(struct uart_port *port, | |
890 | struct s3c2410_uartcfg *cfg) | |
891 | { | |
892 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
893 | ||
894 | return (info->reset_port)(port, cfg); | |
895 | } | |
896 | ||
30555476 BD |
897 | |
898 | #ifdef CONFIG_CPU_FREQ | |
899 | ||
900 | static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, | |
901 | unsigned long val, void *data) | |
902 | { | |
903 | struct s3c24xx_uart_port *port; | |
904 | struct uart_port *uport; | |
905 | ||
906 | port = container_of(nb, struct s3c24xx_uart_port, freq_transition); | |
907 | uport = &port->port; | |
908 | ||
909 | /* check to see if port is enabled */ | |
910 | ||
911 | if (port->pm_level != 0) | |
912 | return 0; | |
913 | ||
914 | /* try and work out if the baudrate is changing, we can detect | |
915 | * a change in rate, but we do not have support for detecting | |
916 | * a disturbance in the clock-rate over the change. | |
917 | */ | |
918 | ||
919 | if (IS_ERR(port->clk)) | |
920 | goto exit; | |
921 | ||
922 | if (port->baudclk_rate == clk_get_rate(port->clk)) | |
923 | goto exit; | |
924 | ||
925 | if (val == CPUFREQ_PRECHANGE) { | |
926 | /* we should really shut the port down whilst the | |
927 | * frequency change is in progress. */ | |
928 | ||
929 | } else if (val == CPUFREQ_POSTCHANGE) { | |
930 | struct ktermios *termios; | |
931 | struct tty_struct *tty; | |
932 | ||
933 | if (uport->info == NULL) { | |
934 | printk(KERN_WARNING "%s: info NULL\n", __func__); | |
935 | goto exit; | |
936 | } | |
937 | ||
938 | tty = uport->info->port.tty; | |
939 | ||
940 | if (tty == NULL) { | |
941 | printk(KERN_WARNING "%s: tty is NULL\n", __func__); | |
942 | goto exit; | |
943 | } | |
944 | ||
945 | termios = tty->termios; | |
946 | ||
947 | if (termios == NULL) { | |
948 | printk(KERN_WARNING "%s: no termios?\n", __func__); | |
949 | goto exit; | |
950 | } | |
951 | ||
952 | s3c24xx_serial_set_termios(uport, termios, NULL); | |
953 | } | |
954 | ||
955 | exit: | |
956 | return 0; | |
957 | } | |
958 | ||
959 | static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) | |
960 | { | |
961 | port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; | |
962 | ||
963 | return cpufreq_register_notifier(&port->freq_transition, | |
964 | CPUFREQ_TRANSITION_NOTIFIER); | |
965 | } | |
966 | ||
967 | static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) | |
968 | { | |
969 | cpufreq_unregister_notifier(&port->freq_transition, | |
970 | CPUFREQ_TRANSITION_NOTIFIER); | |
971 | } | |
972 | ||
973 | #else | |
974 | static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) | |
975 | { | |
976 | return 0; | |
977 | } | |
978 | ||
979 | static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) | |
980 | { | |
981 | } | |
982 | #endif | |
983 | ||
b497549a BD |
984 | /* s3c24xx_serial_init_port |
985 | * | |
986 | * initialise a single serial port from the platform device given | |
987 | */ | |
988 | ||
989 | static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, | |
990 | struct s3c24xx_uart_info *info, | |
991 | struct platform_device *platdev) | |
992 | { | |
993 | struct uart_port *port = &ourport->port; | |
994 | struct s3c2410_uartcfg *cfg; | |
995 | struct resource *res; | |
996 | int ret; | |
997 | ||
998 | dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev); | |
999 | ||
1000 | if (platdev == NULL) | |
1001 | return -ENODEV; | |
1002 | ||
1003 | cfg = s3c24xx_dev_to_cfg(&platdev->dev); | |
1004 | ||
1005 | if (port->mapbase != 0) | |
1006 | return 0; | |
1007 | ||
1008 | if (cfg->hwport > 3) | |
1009 | return -EINVAL; | |
1010 | ||
1011 | /* setup info for port */ | |
1012 | port->dev = &platdev->dev; | |
1013 | ourport->info = info; | |
1014 | ||
1015 | /* copy the info in from provided structure */ | |
1016 | ourport->port.fifosize = info->fifosize; | |
1017 | ||
1018 | dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport); | |
1019 | ||
1020 | port->uartclk = 1; | |
1021 | ||
1022 | if (cfg->uart_flags & UPF_CONS_FLOW) { | |
1023 | dbg("s3c24xx_serial_init_port: enabling flow control\n"); | |
1024 | port->flags |= UPF_CONS_FLOW; | |
1025 | } | |
1026 | ||
1027 | /* sort our the physical and virtual addresses for each UART */ | |
1028 | ||
1029 | res = platform_get_resource(platdev, IORESOURCE_MEM, 0); | |
1030 | if (res == NULL) { | |
1031 | printk(KERN_ERR "failed to find memory resource for uart\n"); | |
1032 | return -EINVAL; | |
1033 | } | |
1034 | ||
1035 | dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); | |
1036 | ||
1037 | port->mapbase = res->start; | |
1038 | port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART); | |
1039 | ret = platform_get_irq(platdev, 0); | |
1040 | if (ret < 0) | |
1041 | port->irq = 0; | |
1042 | else | |
1043 | port->irq = ret; | |
1044 | ||
1045 | ourport->clk = clk_get(&platdev->dev, "uart"); | |
1046 | ||
1047 | dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n", | |
1048 | port->mapbase, port->membase, port->irq, port->uartclk); | |
1049 | ||
1050 | /* reset the fifos (and setup the uart) */ | |
1051 | s3c24xx_serial_resetport(port, cfg); | |
1052 | return 0; | |
1053 | } | |
1054 | ||
1055 | static ssize_t s3c24xx_serial_show_clksrc(struct device *dev, | |
1056 | struct device_attribute *attr, | |
1057 | char *buf) | |
1058 | { | |
1059 | struct uart_port *port = s3c24xx_dev_to_port(dev); | |
1060 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
1061 | ||
1062 | return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name); | |
1063 | } | |
1064 | ||
1065 | static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL); | |
1066 | ||
1067 | /* Device driver serial port probe */ | |
1068 | ||
1069 | static int probe_index; | |
1070 | ||
1071 | int s3c24xx_serial_probe(struct platform_device *dev, | |
1072 | struct s3c24xx_uart_info *info) | |
1073 | { | |
1074 | struct s3c24xx_uart_port *ourport; | |
1075 | int ret; | |
1076 | ||
1077 | dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index); | |
1078 | ||
1079 | ourport = &s3c24xx_serial_ports[probe_index]; | |
1080 | probe_index++; | |
1081 | ||
1082 | dbg("%s: initialising port %p...\n", __func__, ourport); | |
1083 | ||
1084 | ret = s3c24xx_serial_init_port(ourport, info, dev); | |
1085 | if (ret < 0) | |
1086 | goto probe_err; | |
1087 | ||
1088 | dbg("%s: adding port\n", __func__); | |
1089 | uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); | |
1090 | platform_set_drvdata(dev, &ourport->port); | |
1091 | ||
1092 | ret = device_create_file(&dev->dev, &dev_attr_clock_source); | |
1093 | if (ret < 0) | |
1094 | printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__); | |
1095 | ||
30555476 BD |
1096 | ret = s3c24xx_serial_cpufreq_register(ourport); |
1097 | if (ret < 0) | |
1098 | dev_err(&dev->dev, "failed to add cpufreq notifier\n"); | |
1099 | ||
b497549a BD |
1100 | return 0; |
1101 | ||
1102 | probe_err: | |
1103 | return ret; | |
1104 | } | |
1105 | ||
1106 | EXPORT_SYMBOL_GPL(s3c24xx_serial_probe); | |
1107 | ||
1108 | int s3c24xx_serial_remove(struct platform_device *dev) | |
1109 | { | |
1110 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | |
1111 | ||
1112 | if (port) { | |
30555476 | 1113 | s3c24xx_serial_cpufreq_deregister(to_ourport(port)); |
b497549a BD |
1114 | device_remove_file(&dev->dev, &dev_attr_clock_source); |
1115 | uart_remove_one_port(&s3c24xx_uart_drv, port); | |
1116 | } | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | EXPORT_SYMBOL_GPL(s3c24xx_serial_remove); | |
1122 | ||
1123 | /* UART power management code */ | |
1124 | ||
1125 | #ifdef CONFIG_PM | |
1126 | ||
1127 | static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1128 | { | |
1129 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | |
1130 | ||
1131 | if (port) | |
1132 | uart_suspend_port(&s3c24xx_uart_drv, port); | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | static int s3c24xx_serial_resume(struct platform_device *dev) | |
1138 | { | |
1139 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | |
1140 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
1141 | ||
1142 | if (port) { | |
1143 | clk_enable(ourport->clk); | |
1144 | s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); | |
1145 | clk_disable(ourport->clk); | |
1146 | ||
1147 | uart_resume_port(&s3c24xx_uart_drv, port); | |
1148 | } | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | #endif | |
1153 | ||
1154 | int s3c24xx_serial_init(struct platform_driver *drv, | |
1155 | struct s3c24xx_uart_info *info) | |
1156 | { | |
1157 | dbg("s3c24xx_serial_init(%p,%p)\n", drv, info); | |
1158 | ||
1159 | #ifdef CONFIG_PM | |
1160 | drv->suspend = s3c24xx_serial_suspend; | |
1161 | drv->resume = s3c24xx_serial_resume; | |
1162 | #endif | |
1163 | ||
1164 | return platform_driver_register(drv); | |
1165 | } | |
1166 | ||
1167 | EXPORT_SYMBOL_GPL(s3c24xx_serial_init); | |
1168 | ||
1169 | /* module initialisation code */ | |
1170 | ||
1171 | static int __init s3c24xx_serial_modinit(void) | |
1172 | { | |
1173 | int ret; | |
1174 | ||
1175 | ret = uart_register_driver(&s3c24xx_uart_drv); | |
1176 | if (ret < 0) { | |
1177 | printk(KERN_ERR "failed to register UART driver\n"); | |
1178 | return -1; | |
1179 | } | |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | static void __exit s3c24xx_serial_modexit(void) | |
1185 | { | |
1186 | uart_unregister_driver(&s3c24xx_uart_drv); | |
1187 | } | |
1188 | ||
1189 | module_init(s3c24xx_serial_modinit); | |
1190 | module_exit(s3c24xx_serial_modexit); | |
1191 | ||
1192 | /* Console code */ | |
1193 | ||
1194 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | |
1195 | ||
1196 | static struct uart_port *cons_uart; | |
1197 | ||
1198 | static int | |
1199 | s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) | |
1200 | { | |
1201 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
1202 | unsigned long ufstat, utrstat; | |
1203 | ||
1204 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | |
1205 | /* fifo mode - check ammount of data in fifo registers... */ | |
1206 | ||
1207 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
1208 | return (ufstat & info->tx_fifofull) ? 0 : 1; | |
1209 | } | |
1210 | ||
1211 | /* in non-fifo mode, we go and use the tx buffer empty */ | |
1212 | ||
1213 | utrstat = rd_regl(port, S3C2410_UTRSTAT); | |
1214 | return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; | |
1215 | } | |
1216 | ||
1217 | static void | |
1218 | s3c24xx_serial_console_putchar(struct uart_port *port, int ch) | |
1219 | { | |
1220 | unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON); | |
1221 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) | |
1222 | barrier(); | |
1223 | wr_regb(cons_uart, S3C2410_UTXH, ch); | |
1224 | } | |
1225 | ||
1226 | static void | |
1227 | s3c24xx_serial_console_write(struct console *co, const char *s, | |
1228 | unsigned int count) | |
1229 | { | |
1230 | uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); | |
1231 | } | |
1232 | ||
1233 | static void __init | |
1234 | s3c24xx_serial_get_options(struct uart_port *port, int *baud, | |
1235 | int *parity, int *bits) | |
1236 | { | |
1237 | struct s3c24xx_uart_clksrc clksrc; | |
1238 | struct clk *clk; | |
1239 | unsigned int ulcon; | |
1240 | unsigned int ucon; | |
1241 | unsigned int ubrdiv; | |
1242 | unsigned long rate; | |
1243 | ||
1244 | ulcon = rd_regl(port, S3C2410_ULCON); | |
1245 | ucon = rd_regl(port, S3C2410_UCON); | |
1246 | ubrdiv = rd_regl(port, S3C2410_UBRDIV); | |
1247 | ||
1248 | dbg("s3c24xx_serial_get_options: port=%p\n" | |
1249 | "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n", | |
1250 | port, ulcon, ucon, ubrdiv); | |
1251 | ||
1252 | if ((ucon & 0xf) != 0) { | |
1253 | /* consider the serial port configured if the tx/rx mode set */ | |
1254 | ||
1255 | switch (ulcon & S3C2410_LCON_CSMASK) { | |
1256 | case S3C2410_LCON_CS5: | |
1257 | *bits = 5; | |
1258 | break; | |
1259 | case S3C2410_LCON_CS6: | |
1260 | *bits = 6; | |
1261 | break; | |
1262 | case S3C2410_LCON_CS7: | |
1263 | *bits = 7; | |
1264 | break; | |
1265 | default: | |
1266 | case S3C2410_LCON_CS8: | |
1267 | *bits = 8; | |
1268 | break; | |
1269 | } | |
1270 | ||
1271 | switch (ulcon & S3C2410_LCON_PMASK) { | |
1272 | case S3C2410_LCON_PEVEN: | |
1273 | *parity = 'e'; | |
1274 | break; | |
1275 | ||
1276 | case S3C2410_LCON_PODD: | |
1277 | *parity = 'o'; | |
1278 | break; | |
1279 | ||
1280 | case S3C2410_LCON_PNONE: | |
1281 | default: | |
1282 | *parity = 'n'; | |
1283 | } | |
1284 | ||
1285 | /* now calculate the baud rate */ | |
1286 | ||
1287 | s3c24xx_serial_getsource(port, &clksrc); | |
1288 | ||
1289 | clk = clk_get(port->dev, clksrc.name); | |
1290 | if (!IS_ERR(clk) && clk != NULL) | |
1291 | rate = clk_get_rate(clk) / clksrc.divisor; | |
1292 | else | |
1293 | rate = 1; | |
1294 | ||
1295 | ||
1296 | *baud = rate / (16 * (ubrdiv + 1)); | |
1297 | dbg("calculated baud %d\n", *baud); | |
1298 | } | |
1299 | ||
1300 | } | |
1301 | ||
1302 | /* s3c24xx_serial_init_ports | |
1303 | * | |
1304 | * initialise the serial ports from the machine provided initialisation | |
1305 | * data. | |
1306 | */ | |
1307 | ||
1308 | static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) | |
1309 | { | |
1310 | struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports; | |
1311 | struct platform_device **platdev_ptr; | |
1312 | int i; | |
1313 | ||
1314 | dbg("s3c24xx_serial_init_ports: initialising ports...\n"); | |
1315 | ||
1316 | platdev_ptr = s3c24xx_uart_devs; | |
1317 | ||
1318 | for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) { | |
1319 | s3c24xx_serial_init_port(ptr, info, *platdev_ptr); | |
1320 | } | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | static int __init | |
1326 | s3c24xx_serial_console_setup(struct console *co, char *options) | |
1327 | { | |
1328 | struct uart_port *port; | |
1329 | int baud = 9600; | |
1330 | int bits = 8; | |
1331 | int parity = 'n'; | |
1332 | int flow = 'n'; | |
1333 | ||
1334 | dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n", | |
1335 | co, co->index, options); | |
1336 | ||
1337 | /* is this a valid port */ | |
1338 | ||
1339 | if (co->index == -1 || co->index >= NR_PORTS) | |
1340 | co->index = 0; | |
1341 | ||
1342 | port = &s3c24xx_serial_ports[co->index].port; | |
1343 | ||
1344 | /* is the port configured? */ | |
1345 | ||
1346 | if (port->mapbase == 0x0) { | |
1347 | co->index = 0; | |
1348 | port = &s3c24xx_serial_ports[co->index].port; | |
1349 | } | |
1350 | ||
1351 | cons_uart = port; | |
1352 | ||
1353 | dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index); | |
1354 | ||
1355 | /* | |
1356 | * Check whether an invalid uart number has been specified, and | |
1357 | * if so, search for the first available port that does have | |
1358 | * console support. | |
1359 | */ | |
1360 | if (options) | |
1361 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1362 | else | |
1363 | s3c24xx_serial_get_options(port, &baud, &parity, &bits); | |
1364 | ||
1365 | dbg("s3c24xx_serial_console_setup: baud %d\n", baud); | |
1366 | ||
1367 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1368 | } | |
1369 | ||
1370 | /* s3c24xx_serial_initconsole | |
1371 | * | |
1372 | * initialise the console from one of the uart drivers | |
1373 | */ | |
1374 | ||
1375 | static struct console s3c24xx_serial_console = { | |
1376 | .name = S3C24XX_SERIAL_NAME, | |
1377 | .device = uart_console_device, | |
1378 | .flags = CON_PRINTBUFFER, | |
1379 | .index = -1, | |
1380 | .write = s3c24xx_serial_console_write, | |
1381 | .setup = s3c24xx_serial_console_setup | |
1382 | }; | |
1383 | ||
1384 | int s3c24xx_serial_initconsole(struct platform_driver *drv, | |
1385 | struct s3c24xx_uart_info *info) | |
1386 | ||
1387 | { | |
1388 | struct platform_device *dev = s3c24xx_uart_devs[0]; | |
1389 | ||
1390 | dbg("s3c24xx_serial_initconsole\n"); | |
1391 | ||
1392 | /* select driver based on the cpu */ | |
1393 | ||
1394 | if (dev == NULL) { | |
1395 | printk(KERN_ERR "s3c24xx: no devices for console init\n"); | |
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | if (strcmp(dev->name, drv->driver.name) != 0) | |
1400 | return 0; | |
1401 | ||
1402 | s3c24xx_serial_console.data = &s3c24xx_uart_drv; | |
1403 | s3c24xx_serial_init_ports(info); | |
1404 | ||
1405 | register_console(&s3c24xx_serial_console); | |
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ | |
1410 | ||
1411 | MODULE_DESCRIPTION("Samsung SoC Serial port driver"); | |
1412 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
1413 | MODULE_LICENSE("GPL v2"); |