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[PATCH] power/video.txt: update documentation with more systems
[deliverable/linux.git] / drivers / serial / serial_txx9.c
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1da177e4
LT		 1/*
2 * drivers/serial/serial_txx9.c
3 *
4 * Derived from many drivers using generic_serial interface,
5 * especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c
6 * (was in Linux/VR tree) by Jim Pick.
7 *
8 * Copyright (C) 1999 Harald Koerfgen
9 * Copyright (C) 2000 Jim Pick <jim@jimpick.com>
10 * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
11 * Copyright (C) 2000-2002 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller
18 *
19 * Revision History:
20 * 0.30 Initial revision. (Renamed from serial_txx927.c)
21 * 0.31 Use save_flags instead of local_irq_save.
22 * 0.32 Support SCLK.
23 * 0.33 Switch TXX9_TTY_NAME by CONFIG_SERIAL_TXX9_STDSERIAL.
24 * Support TIOCSERGETLSR.
25 * 0.34 Support slow baudrate.
26 * 0.40 Merge codes from mainstream kernel (2.4.22).
27 * 0.41 Fix console checking in rs_shutdown_port().
28 * Disable flow-control in serial_console_write().
29 * 0.42 Fix minor compiler warning.
30 * 1.00 Kernel 2.6. Converted to new serial core (based on 8250.c).
31 * 1.01 Set fifosize to make tx_empry called properly.
32 * Use standard uart_get_divisor.
33 * 1.02 Cleanup. (import 8250.c changes)
34 */
35#include <linux/config.h>
36
37#if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
38#define SUPPORT_SYSRQ
39#endif
40
41#include <linux/module.h>
42#include <linux/ioport.h>
43#include <linux/init.h>
44#include <linux/console.h>
45#include <linux/sysrq.h>
46#include <linux/delay.h>
47#include <linux/device.h>
48#include <linux/pci.h>
49#include <linux/tty.h>
50#include <linux/tty_flip.h>
51#include <linux/serial_core.h>
52#include <linux/serial.h>
53
54#include <asm/io.h>
55#include <asm/irq.h>
56
57static char *serial_version = "1.02";
58static char *serial_name = "TX39/49 Serial driver";
59
60#define PASS_LIMIT 256
61
62#if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
63/* "ttyS" is used for standard serial driver */
64#define TXX9_TTY_NAME "ttyTX"
65#define TXX9_TTY_DEVFS_NAME "tttx/"
66#define TXX9_TTY_MINOR_START (64 + 64) /* ttyTX0(128), ttyTX1(129) */
67#else
68/* acts like standard serial driver */
69#define TXX9_TTY_NAME "ttyS"
70#define TXX9_TTY_DEVFS_NAME "tts/"
71#define TXX9_TTY_MINOR_START 64
72#endif
73#define TXX9_TTY_MAJOR TTY_MAJOR
74
75/* flag aliases */
76#define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
77#define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
78
79#ifdef CONFIG_PCI
80/* support for Toshiba TC86C001 SIO */
81#define ENABLE_SERIAL_TXX9_PCI
82#endif
83
84/*
85 * Number of serial ports
86 */
87#ifdef ENABLE_SERIAL_TXX9_PCI
88#define NR_PCI_BOARDS 4
89#define UART_NR (2 + NR_PCI_BOARDS)
90#else
91#define UART_NR 2
92#endif
93
94struct uart_txx9_port {
95 struct uart_port port;
96
97 /*
98 * We provide a per-port pm hook.
99 */
100 void (*pm)(struct uart_port *port,
101 unsigned int state, unsigned int old);
102};
103
104#define TXX9_REGION_SIZE 0x24
105
106/* TXX9 Serial Registers */
107#define TXX9_SILCR 0x00
108#define TXX9_SIDICR 0x04
109#define TXX9_SIDISR 0x08
110#define TXX9_SICISR 0x0c
111#define TXX9_SIFCR 0x10
112#define TXX9_SIFLCR 0x14
113#define TXX9_SIBGR 0x18
114#define TXX9_SITFIFO 0x1c
115#define TXX9_SIRFIFO 0x20
116
117/* SILCR : Line Control */
118#define TXX9_SILCR_SCS_MASK 0x00000060
119#define TXX9_SILCR_SCS_IMCLK 0x00000000
120#define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
121#define TXX9_SILCR_SCS_SCLK 0x00000040
122#define TXX9_SILCR_SCS_SCLK_BG 0x00000060
123#define TXX9_SILCR_UEPS 0x00000010
124#define TXX9_SILCR_UPEN 0x00000008
125#define TXX9_SILCR_USBL_MASK 0x00000004
126#define TXX9_SILCR_USBL_1BIT 0x00000000
127#define TXX9_SILCR_USBL_2BIT 0x00000004
128#define TXX9_SILCR_UMODE_MASK 0x00000003
129#define TXX9_SILCR_UMODE_8BIT 0x00000000
130#define TXX9_SILCR_UMODE_7BIT 0x00000001
131
132/* SIDICR : DMA/Int. Control */
133#define TXX9_SIDICR_TDE 0x00008000
134#define TXX9_SIDICR_RDE 0x00004000
135#define TXX9_SIDICR_TIE 0x00002000
136#define TXX9_SIDICR_RIE 0x00001000
137#define TXX9_SIDICR_SPIE 0x00000800
138#define TXX9_SIDICR_CTSAC 0x00000600
139#define TXX9_SIDICR_STIE_MASK 0x0000003f
140#define TXX9_SIDICR_STIE_OERS 0x00000020
141#define TXX9_SIDICR_STIE_CTSS 0x00000010
142#define TXX9_SIDICR_STIE_RBRKD 0x00000008
143#define TXX9_SIDICR_STIE_TRDY 0x00000004
144#define TXX9_SIDICR_STIE_TXALS 0x00000002
145#define TXX9_SIDICR_STIE_UBRKD 0x00000001
146
147/* SIDISR : DMA/Int. Status */
148#define TXX9_SIDISR_UBRK 0x00008000
149#define TXX9_SIDISR_UVALID 0x00004000
150#define TXX9_SIDISR_UFER 0x00002000
151#define TXX9_SIDISR_UPER 0x00001000
152#define TXX9_SIDISR_UOER 0x00000800
153#define TXX9_SIDISR_ERI 0x00000400
154#define TXX9_SIDISR_TOUT 0x00000200
155#define TXX9_SIDISR_TDIS 0x00000100
156#define TXX9_SIDISR_RDIS 0x00000080
157#define TXX9_SIDISR_STIS 0x00000040
158#define TXX9_SIDISR_RFDN_MASK 0x0000001f
159
160/* SICISR : Change Int. Status */
161#define TXX9_SICISR_OERS 0x00000020
162#define TXX9_SICISR_CTSS 0x00000010
163#define TXX9_SICISR_RBRKD 0x00000008
164#define TXX9_SICISR_TRDY 0x00000004
165#define TXX9_SICISR_TXALS 0x00000002
166#define TXX9_SICISR_UBRKD 0x00000001
167
168/* SIFCR : FIFO Control */
169#define TXX9_SIFCR_SWRST 0x00008000
170#define TXX9_SIFCR_RDIL_MASK 0x00000180
171#define TXX9_SIFCR_RDIL_1 0x00000000
172#define TXX9_SIFCR_RDIL_4 0x00000080
173#define TXX9_SIFCR_RDIL_8 0x00000100
174#define TXX9_SIFCR_RDIL_12 0x00000180
175#define TXX9_SIFCR_RDIL_MAX 0x00000180
176#define TXX9_SIFCR_TDIL_MASK 0x00000018
177#define TXX9_SIFCR_TDIL_MASK 0x00000018
178#define TXX9_SIFCR_TDIL_1 0x00000000
179#define TXX9_SIFCR_TDIL_4 0x00000001
180#define TXX9_SIFCR_TDIL_8 0x00000010
181#define TXX9_SIFCR_TDIL_MAX 0x00000010
182#define TXX9_SIFCR_TFRST 0x00000004
183#define TXX9_SIFCR_RFRST 0x00000002
184#define TXX9_SIFCR_FRSTE 0x00000001
185#define TXX9_SIO_TX_FIFO 8
186#define TXX9_SIO_RX_FIFO 16
187
188/* SIFLCR : Flow Control */
189#define TXX9_SIFLCR_RCS 0x00001000
190#define TXX9_SIFLCR_TES 0x00000800
191#define TXX9_SIFLCR_RTSSC 0x00000200
192#define TXX9_SIFLCR_RSDE 0x00000100
193#define TXX9_SIFLCR_TSDE 0x00000080
194#define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
195#define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
196#define TXX9_SIFLCR_TBRK 0x00000001
197
198/* SIBGR : Baudrate Control */
199#define TXX9_SIBGR_BCLK_MASK 0x00000300
200#define TXX9_SIBGR_BCLK_T0 0x00000000
201#define TXX9_SIBGR_BCLK_T2 0x00000100
202#define TXX9_SIBGR_BCLK_T4 0x00000200
203#define TXX9_SIBGR_BCLK_T6 0x00000300
204#define TXX9_SIBGR_BRD_MASK 0x000000ff
205
206static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
207{
208 switch (up->port.iotype) {
209 default:
210 return *(volatile u32 *)(up->port.membase + offset);
211 case UPIO_PORT:
212 return inl(up->port.iobase + offset);
213 }
214}
215
216static inline void
217sio_out(struct uart_txx9_port *up, int offset, int value)
218{
219 switch (up->port.iotype) {
220 default:
221 *(volatile u32 *)(up->port.membase + offset) = value;
222 break;
223 case UPIO_PORT:
224 outl(value, up->port.iobase + offset);
225 break;
226 }
227}
228
229static inline void
230sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
231{
232 sio_out(up, offset, sio_in(up, offset) & ~value);
233}
234static inline void
235sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
236{
237 sio_out(up, offset, sio_in(up, offset) | value);
238}
239
240static inline void
241sio_quot_set(struct uart_txx9_port *up, int quot)
242{
243 quot >>= 1;
244 if (quot < 256)
245 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
246 else if (quot < (256 << 2))
247 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
248 else if (quot < (256 << 4))
249 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
250 else if (quot < (256 << 6))
251 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
252 else
253 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
254}
255
256static void serial_txx9_stop_tx(struct uart_port *port, unsigned int tty_stop)
257{
258 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
259 unsigned long flags;
260
261 spin_lock_irqsave(&up->port.lock, flags);
262 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
263 spin_unlock_irqrestore(&up->port.lock, flags);
264}
265
266static void serial_txx9_start_tx(struct uart_port *port, unsigned int tty_start)
267{
268 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
269 unsigned long flags;
270
271 spin_lock_irqsave(&up->port.lock, flags);
272 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
273 spin_unlock_irqrestore(&up->port.lock, flags);
274}
275
276static void serial_txx9_stop_rx(struct uart_port *port)
277{
278 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
279 unsigned long flags;
280
281 spin_lock_irqsave(&up->port.lock, flags);
282 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
283#if 0
284 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
285#endif
286 spin_unlock_irqrestore(&up->port.lock, flags);
287}
288
289static void serial_txx9_enable_ms(struct uart_port *port)
290{
291 /* TXX9-SIO can not control DTR... */
292}
293
294static inline void
295receive_chars(struct uart_txx9_port *up, unsigned int *status, struct pt_regs *regs)
296{
297 struct tty_struct *tty = up->port.info->tty;
298 unsigned char ch;
299 unsigned int disr = *status;
300 int max_count = 256;
301 char flag;
302
303 do {
304 /* The following is not allowed by the tty layer and
305 unsafe. It should be fixed ASAP */
306 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
307 if(tty->low_latency)
308 tty_flip_buffer_push(tty);
309 /* If this failed then we will throw away the
310 bytes but must do so to clear interrupts */
311 }
312 ch = sio_in(up, TXX9_SIRFIFO);
313 flag = TTY_NORMAL;
314 up->port.icount.rx++;
315
316 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
317 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
318 /*
319 * For statistics only
320 */
321 if (disr & TXX9_SIDISR_UBRK) {
322 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
323 up->port.icount.brk++;
324 /*
325 * We do the SysRQ and SAK checking
326 * here because otherwise the break
327 * may get masked by ignore_status_mask
328 * or read_status_mask.
329 */
330 if (uart_handle_break(&up->port))
331 goto ignore_char;
332 } else if (disr & TXX9_SIDISR_UPER)
333 up->port.icount.parity++;
334 else if (disr & TXX9_SIDISR_UFER)
335 up->port.icount.frame++;
336 if (disr & TXX9_SIDISR_UOER)
337 up->port.icount.overrun++;
338
339 /*
340 * Mask off conditions which should be ingored.
341 */
342 disr &= up->port.read_status_mask;
343
344 if (disr & TXX9_SIDISR_UBRK) {
345 flag = TTY_BREAK;
346 } else if (disr & TXX9_SIDISR_UPER)
347 flag = TTY_PARITY;
348 else if (disr & TXX9_SIDISR_UFER)
349 flag = TTY_FRAME;
350 }
351 if (uart_handle_sysrq_char(&up->port, ch, regs))
352 goto ignore_char;
353 if ((disr & up->port.ignore_status_mask) == 0) {
354 tty_insert_flip_char(tty, ch, flag);
355 }
356 if ((disr & TXX9_SIDISR_UOER) &&
357 tty->flip.count < TTY_FLIPBUF_SIZE) {
358 /*
359 * Overrun is special, since it's reported
360 * immediately, and doesn't affect the current
361 * character.
362 */
363 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
364 }
365 ignore_char:
366 disr = sio_in(up, TXX9_SIDISR);
367 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
368 tty_flip_buffer_push(tty);
369 *status = disr;
370}
371
372static inline void transmit_chars(struct uart_txx9_port *up)
373{
374 struct circ_buf *xmit = &up->port.info->xmit;
375 int count;
376
377 if (up->port.x_char) {
378 sio_out(up, TXX9_SITFIFO, up->port.x_char);
379 up->port.icount.tx++;
380 up->port.x_char = 0;
381 return;
382 }
383 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
384 serial_txx9_stop_tx(&up->port, 0);
385 return;
386 }
387
388 count = TXX9_SIO_TX_FIFO;
389 do {
390 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
391 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
392 up->port.icount.tx++;
393 if (uart_circ_empty(xmit))
394 break;
395 } while (--count > 0);
396
397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
398 uart_write_wakeup(&up->port);
399
400 if (uart_circ_empty(xmit))
401 serial_txx9_stop_tx(&up->port, 0);
402}
403
404static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id, struct pt_regs *regs)
405{
406 int pass_counter = 0;
407 struct uart_txx9_port *up = dev_id;
408 unsigned int status;
409
410 while (1) {
411 spin_lock(&up->port.lock);
412 status = sio_in(up, TXX9_SIDISR);
413 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
414 status &= ~TXX9_SIDISR_TDIS;
415 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
416 TXX9_SIDISR_TOUT))) {
417 spin_unlock(&up->port.lock);
418 break;
419 }
420
421 if (status & TXX9_SIDISR_RDIS)
422 receive_chars(up, &status, regs);
423 if (status & TXX9_SIDISR_TDIS)
424 transmit_chars(up);
425 /* Clear TX/RX Int. Status */
426 sio_mask(up, TXX9_SIDISR,
427 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
428 TXX9_SIDISR_TOUT);
429 spin_unlock(&up->port.lock);
430
431 if (pass_counter++ > PASS_LIMIT)
432 break;
433 }
434
435 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
436}
437
438static unsigned int serial_txx9_tx_empty(struct uart_port *port)
439{
440 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
441 unsigned long flags;
442 unsigned int ret;
443
444 spin_lock_irqsave(&up->port.lock, flags);
445 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
446 spin_unlock_irqrestore(&up->port.lock, flags);
447
448 return ret;
449}
450
451static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
452{
453 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
454 unsigned long flags;
455 unsigned int ret;
456
457 spin_lock_irqsave(&up->port.lock, flags);
458 ret = ((sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS)
459 | ((sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS);
460 spin_unlock_irqrestore(&up->port.lock, flags);
461
462 return ret;
463}
464
465static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
466{
467 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
468 unsigned long flags;
469
470 spin_lock_irqsave(&up->port.lock, flags);
471 if (mctrl & TIOCM_RTS)
472 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
473 else
474 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
475 spin_unlock_irqrestore(&up->port.lock, flags);
476}
477
478static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
479{
480 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
481 unsigned long flags;
482
483 spin_lock_irqsave(&up->port.lock, flags);
484 if (break_state == -1)
485 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
486 else
487 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
488 spin_unlock_irqrestore(&up->port.lock, flags);
489}
490
491static int serial_txx9_startup(struct uart_port *port)
492{
493 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
494 unsigned long flags;
495 int retval;
496
497 /*
498 * Clear the FIFO buffers and disable them.
499 * (they will be reeanbled in set_termios())
500 */
501 sio_set(up, TXX9_SIFCR,
502 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
503 /* clear reset */
504 sio_mask(up, TXX9_SIFCR,
505 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
506 sio_out(up, TXX9_SIDICR, 0);
507
508 /*
509 * Clear the interrupt registers.
510 */
511 sio_out(up, TXX9_SIDISR, 0);
512
513 retval = request_irq(up->port.irq, serial_txx9_interrupt,
514 SA_SHIRQ, "serial_txx9", up);
515 if (retval)
516 return retval;
517
518 /*
519 * Now, initialize the UART
520 */
521 spin_lock_irqsave(&up->port.lock, flags);
522 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
523 spin_unlock_irqrestore(&up->port.lock, flags);
524
525 /* Enable RX/TX */
526 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
527
528 /*
529 * Finally, enable interrupts.
530 */
531 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
532
533 return 0;
534}
535
536static void serial_txx9_shutdown(struct uart_port *port)
537{
538 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
539 unsigned long flags;
540
541 /*
542 * Disable interrupts from this port
543 */
544 sio_out(up, TXX9_SIDICR, 0); /* disable all intrs */
545
546 spin_lock_irqsave(&up->port.lock, flags);
547 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
548 spin_unlock_irqrestore(&up->port.lock, flags);
549
550 /*
551 * Disable break condition
552 */
553 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
554
555#ifdef CONFIG_SERIAL_TXX9_CONSOLE
556 if (up->port.cons && up->port.line == up->port.cons->index) {
557 free_irq(up->port.irq, up);
558 return;
559 }
560#endif
561 /* reset FIFOs */
562 sio_set(up, TXX9_SIFCR,
563 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
564 /* clear reset */
565 sio_mask(up, TXX9_SIFCR,
566 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
567
568 /* Disable RX/TX */
569 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
570
571 free_irq(up->port.irq, up);
572}
573
574static void
575serial_txx9_set_termios(struct uart_port *port, struct termios *termios,
576 struct termios *old)
577{
578 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
579 unsigned int cval, fcr = 0;
580 unsigned long flags;
581 unsigned int baud, quot;
582
583 cval = sio_in(up, TXX9_SILCR);
584 /* byte size and parity */
585 cval &= ~TXX9_SILCR_UMODE_MASK;
586 switch (termios->c_cflag & CSIZE) {
587 case CS7:
588 cval |= TXX9_SILCR_UMODE_7BIT;
589 break;
590 default:
591 case CS5: /* not supported */
592 case CS6: /* not supported */
593 case CS8:
594 cval |= TXX9_SILCR_UMODE_8BIT;
595 break;
596 }
597
598 cval &= ~TXX9_SILCR_USBL_MASK;
599 if (termios->c_cflag & CSTOPB)
600 cval |= TXX9_SILCR_USBL_2BIT;
601 else
602 cval |= TXX9_SILCR_USBL_1BIT;
603 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
604 if (termios->c_cflag & PARENB)
605 cval |= TXX9_SILCR_UPEN;
606 if (!(termios->c_cflag & PARODD))
607 cval |= TXX9_SILCR_UEPS;
608
609 /*
610 * Ask the core to calculate the divisor for us.
611 */
612 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
613 quot = uart_get_divisor(port, baud);
614
615 /* Set up FIFOs */
616 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
617 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
618
619 /*
620 * Ok, we're now changing the port state. Do it with
621 * interrupts disabled.
622 */
623 spin_lock_irqsave(&up->port.lock, flags);
624
625 /*
626 * Update the per-port timeout.
627 */
628 uart_update_timeout(port, termios->c_cflag, baud);
629
630 up->port.read_status_mask = TXX9_SIDISR_UOER |
631 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
632 if (termios->c_iflag & INPCK)
633 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
634 if (termios->c_iflag & (BRKINT | PARMRK))
635 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
636
637 /*
638 * Characteres to ignore
639 */
640 up->port.ignore_status_mask = 0;
641 if (termios->c_iflag & IGNPAR)
642 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
643 if (termios->c_iflag & IGNBRK) {
644 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
645 /*
646 * If we're ignoring parity and break indicators,
647 * ignore overruns too (for real raw support).
648 */
649 if (termios->c_iflag & IGNPAR)
650 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
651 }
652
653 /*
654 * ignore all characters if CREAD is not set
655 */
656 if ((termios->c_cflag & CREAD) == 0)
657 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
658
659 /* CTS flow control flag */
660 if ((termios->c_cflag & CRTSCTS) &&
661 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
662 sio_set(up, TXX9_SIFLCR,
663 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
664 } else {
665 sio_mask(up, TXX9_SIFLCR,
666 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
667 }
668
669 sio_out(up, TXX9_SILCR, cval);
670 sio_quot_set(up, quot);
671 sio_out(up, TXX9_SIFCR, fcr);
672
673 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
674 spin_unlock_irqrestore(&up->port.lock, flags);
675}
676
677static void
678serial_txx9_pm(struct uart_port *port, unsigned int state,
679 unsigned int oldstate)
680{
681 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
682 if (state) {
683 /* sleep */
684
685 if (up->pm)
686 up->pm(port, state, oldstate);
687 } else {
688 /* wake */
689
690 if (up->pm)
691 up->pm(port, state, oldstate);
692 }
693}
694
695static int serial_txx9_request_resource(struct uart_txx9_port *up)
696{
697 unsigned int size = TXX9_REGION_SIZE;
698 int ret = 0;
699
700 switch (up->port.iotype) {
701 default:
702 if (!up->port.mapbase)
703 break;
704
705 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
706 ret = -EBUSY;
707 break;
708 }
709
710 if (up->port.flags & UPF_IOREMAP) {
711 up->port.membase = ioremap(up->port.mapbase, size);
712 if (!up->port.membase) {
713 release_mem_region(up->port.mapbase, size);
714 ret = -ENOMEM;
715 }
716 }
717 break;
718
719 case UPIO_PORT:
720 if (!request_region(up->port.iobase, size, "serial_txx9"))
721 ret = -EBUSY;
722 break;
723 }
724 return ret;
725}
726
727static void serial_txx9_release_resource(struct uart_txx9_port *up)
728{
729 unsigned int size = TXX9_REGION_SIZE;
730
731 switch (up->port.iotype) {
732 default:
733 if (!up->port.mapbase)
734 break;
735
736 if (up->port.flags & UPF_IOREMAP) {
737 iounmap(up->port.membase);
738 up->port.membase = NULL;
739 }
740
741 release_mem_region(up->port.mapbase, size);
742 break;
743
744 case UPIO_PORT:
745 release_region(up->port.iobase, size);
746 break;
747 }
748}
749
750static void serial_txx9_release_port(struct uart_port *port)
751{
752 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
753 serial_txx9_release_resource(up);
754}
755
756static int serial_txx9_request_port(struct uart_port *port)
757{
758 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
759 return serial_txx9_request_resource(up);
760}
761
762static void serial_txx9_config_port(struct uart_port *port, int uflags)
763{
764 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
765 unsigned long flags;
766 int ret;
767
768 /*
769 * Find the region that we can probe for. This in turn
770 * tells us whether we can probe for the type of port.
771 */
772 ret = serial_txx9_request_resource(up);
773 if (ret < 0)
774 return;
775 port->type = PORT_TXX9;
776 up->port.fifosize = TXX9_SIO_TX_FIFO;
777
778#ifdef CONFIG_SERIAL_TXX9_CONSOLE
779 if (up->port.line == up->port.cons->index)
780 return;
781#endif
782 spin_lock_irqsave(&up->port.lock, flags);
783 /*
784 * Reset the UART.
785 */
786 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
787#ifdef CONFIG_CPU_TX49XX
788 /* TX4925 BUG WORKAROUND. Accessing SIOC register
789 * immediately after soft reset causes bus error. */
790 iob();
791 udelay(1);
792#endif
793 while (sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST)
794 ;
795 /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
796 sio_set(up, TXX9_SIFCR,
797 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
798 /* initial settings */
799 sio_out(up, TXX9_SILCR,
800 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
801 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
802 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
803 sio_quot_set(up, uart_get_divisor(port, 9600));
804 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
805 spin_unlock_irqrestore(&up->port.lock, flags);
806}
807
808static int
809serial_txx9_verify_port(struct uart_port *port, struct serial_struct *ser)
810{
811 if (ser->irq < 0 ||
812 ser->baud_base < 9600 || ser->type != PORT_TXX9)
813 return -EINVAL;
814 return 0;
815}
816
817static const char *
818serial_txx9_type(struct uart_port *port)
819{
820 return "txx9";
821}
822
823static struct uart_ops serial_txx9_pops = {
824 .tx_empty = serial_txx9_tx_empty,
825 .set_mctrl = serial_txx9_set_mctrl,
826 .get_mctrl = serial_txx9_get_mctrl,
827 .stop_tx = serial_txx9_stop_tx,
828 .start_tx = serial_txx9_start_tx,
829 .stop_rx = serial_txx9_stop_rx,
830 .enable_ms = serial_txx9_enable_ms,
831 .break_ctl = serial_txx9_break_ctl,
832 .startup = serial_txx9_startup,
833 .shutdown = serial_txx9_shutdown,
834 .set_termios = serial_txx9_set_termios,
835 .pm = serial_txx9_pm,
836 .type = serial_txx9_type,
837 .release_port = serial_txx9_release_port,
838 .request_port = serial_txx9_request_port,
839 .config_port = serial_txx9_config_port,
840 .verify_port = serial_txx9_verify_port,
841};
842
843static struct uart_txx9_port serial_txx9_ports[UART_NR];
844
845static void __init serial_txx9_register_ports(struct uart_driver *drv)
846{
847 int i;
848
849 for (i = 0; i < UART_NR; i++) {
850 struct uart_txx9_port *up = &serial_txx9_ports[i];
851
852 up->port.line = i;
853 up->port.ops = &serial_txx9_pops;
854 uart_add_one_port(drv, &up->port);
855 }
856}
857
858#ifdef CONFIG_SERIAL_TXX9_CONSOLE
859
860/*
861 * Wait for transmitter & holding register to empty
862 */
863static inline void wait_for_xmitr(struct uart_txx9_port *up)
864{
865 unsigned int tmout = 10000;
866
867 /* Wait up to 10ms for the character(s) to be sent. */
868 while (--tmout &&
869 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
870 udelay(1);
871
872 /* Wait up to 1s for flow control if necessary */
873 if (up->port.flags & UPF_CONS_FLOW) {
874 tmout = 1000000;
875 while (--tmout &&
876 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
877 udelay(1);
878 }
879}
880
881/*
882 * Print a string to the serial port trying not to disturb
883 * any possible real use of the port...
884 *
885 * The console_lock must be held when we get here.
886 */
887static void
888serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
889{
890 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
891 unsigned int ier, flcr;
892 int i;
893
894 /*
895 * First save the UER then disable the interrupts
896 */
897 ier = sio_in(up, TXX9_SIDICR);
898 sio_out(up, TXX9_SIDICR, 0);
899 /*
900 * Disable flow-control if enabled (and unnecessary)
901 */
902 flcr = sio_in(up, TXX9_SIFLCR);
903 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
904 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
905
906 /*
907 * Now, do each character
908 */
909 for (i = 0; i < count; i++, s++) {
910 wait_for_xmitr(up);
911
912 /*
913 * Send the character out.
914 * If a LF, also do CR...
915 */
916 sio_out(up, TXX9_SITFIFO, *s);
917 if (*s == 10) {
918 wait_for_xmitr(up);
919 sio_out(up, TXX9_SITFIFO, 13);
920 }
921 }
922
923 /*
924 * Finally, wait for transmitter to become empty
925 * and restore the IER
926 */
927 wait_for_xmitr(up);
928 sio_out(up, TXX9_SIFLCR, flcr);
929 sio_out(up, TXX9_SIDICR, ier);
930}
931
932static int serial_txx9_console_setup(struct console *co, char *options)
933{
934 struct uart_port *port;
935 struct uart_txx9_port *up;
936 int baud = 9600;
937 int bits = 8;
938 int parity = 'n';
939 int flow = 'n';
940
941 /*
942 * Check whether an invalid uart number has been specified, and
943 * if so, search for the first available port that does have
944 * console support.
945 */
946 if (co->index >= UART_NR)
947 co->index = 0;
948 up = &serial_txx9_ports[co->index];
949 port = &up->port;
950 if (!port->ops)
951 return -ENODEV;
952
953 /*
954 * Temporary fix.
955 */
956 spin_lock_init(&port->lock);
957
958 /*
959 * Disable UART interrupts, set DTR and RTS high
960 * and set speed.
961 */
962 sio_out(up, TXX9_SIDICR, 0);
963 /* initial settings */
964 sio_out(up, TXX9_SILCR,
965 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
966 ((port->flags & UPF_TXX9_USE_SCLK) ?
967 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
968 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
969
970 if (options)
971 uart_parse_options(options, &baud, &parity, &bits, &flow);
972
973 return uart_set_options(port, co, baud, parity, bits, flow);
974}
975
976static struct uart_driver serial_txx9_reg;
977static struct console serial_txx9_console = {
978 .name = TXX9_TTY_NAME,
979 .write = serial_txx9_console_write,
980 .device = uart_console_device,
981 .setup = serial_txx9_console_setup,
982 .flags = CON_PRINTBUFFER,
983 .index = -1,
984 .data = &serial_txx9_reg,
985};
986
987static int __init serial_txx9_console_init(void)
988{
989 register_console(&serial_txx9_console);
990 return 0;
991}
992console_initcall(serial_txx9_console_init);
993
994static int __init serial_txx9_late_console_init(void)
995{
996 if (!(serial_txx9_console.flags & CON_ENABLED))
997 register_console(&serial_txx9_console);
998 return 0;
999}
1000late_initcall(serial_txx9_late_console_init);
1001
1002#define SERIAL_TXX9_CONSOLE &serial_txx9_console
1003#else
1004#define SERIAL_TXX9_CONSOLE NULL
1005#endif
1006
1007static struct uart_driver serial_txx9_reg = {
1008 .owner = THIS_MODULE,
1009 .driver_name = "serial_txx9",
1010 .devfs_name = TXX9_TTY_DEVFS_NAME,
1011 .dev_name = TXX9_TTY_NAME,
1012 .major = TXX9_TTY_MAJOR,
1013 .minor = TXX9_TTY_MINOR_START,
1014 .nr = UART_NR,
1015 .cons = SERIAL_TXX9_CONSOLE,
1016};
1017
1018int __init early_serial_txx9_setup(struct uart_port *port)
1019{
1020 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
1021 return -ENODEV;
1022
1023 serial_txx9_ports[port->line].port = *port;
1024 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
1025 serial_txx9_ports[port->line].port.flags |= UPF_BOOT_AUTOCONF;
1026 return 0;
1027}
1028
1029#ifdef ENABLE_SERIAL_TXX9_PCI
1030/**
1031 * serial_txx9_suspend_port - suspend one serial port
1032 * @line: serial line number
1033 * @level: the level of port suspension, as per uart_suspend_port
1034 *
1035 * Suspend one serial port.
1036 */
1037static void serial_txx9_suspend_port(int line)
1038{
1039 uart_suspend_port(&serial_txx9_reg, &serial_txx9_ports[line].port);
1040}
1041
1042/**
1043 * serial_txx9_resume_port - resume one serial port
1044 * @line: serial line number
1045 * @level: the level of port resumption, as per uart_resume_port
1046 *
1047 * Resume one serial port.
1048 */
1049static void serial_txx9_resume_port(int line)
1050{
1051 uart_resume_port(&serial_txx9_reg, &serial_txx9_ports[line].port);
1052}
1053
1054/*
1055 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1056 * to the arrangement of serial ports on a PCI card.
1057 */
1058static int __devinit
1059pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1060{
1061 struct uart_port port;
1062 int line;
1063 int rc;
1064
1065 rc = pci_enable_device(dev);
1066 if (rc)
1067 return rc;
1068
1069 memset(&port, 0, sizeof(port));
1070 port.ops = &serial_txx9_pops;
1071 port.flags |= UPF_BOOT_AUTOCONF; /* uart_ops.config_port will be called */
1072 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1073 port.uartclk = 66670000;
1074 port.irq = dev->irq;
1075 port.iotype = UPIO_PORT;
1076 port.iobase = pci_resource_start(dev, 1);
1077 line = uart_register_port(&serial_txx9_reg, &port);
1078 if (line < 0) {
1079 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1080 }
1081 pci_set_drvdata(dev, (void *)(long)line);
1082
1083 return 0;
1084}
1085
1086static void __devexit pciserial_txx9_remove_one(struct pci_dev *dev)
1087{
1088 int line = (int)(long)pci_get_drvdata(dev);
1089
1090 pci_set_drvdata(dev, NULL);
1091
1092 if (line) {
1093 uart_unregister_port(&serial_txx9_reg, line);
1094 pci_disable_device(dev);
1095 }
1096}
1097
1098static int pciserial_txx9_suspend_one(struct pci_dev *dev, u32 state)
1099{
1100 int line = (int)(long)pci_get_drvdata(dev);
1101
1102 if (line)
1103 serial_txx9_suspend_port(line);
1104 return 0;
1105}
1106
1107static int pciserial_txx9_resume_one(struct pci_dev *dev)
1108{
1109 int line = (int)(long)pci_get_drvdata(dev);
1110
1111 if (line)
1112 serial_txx9_resume_port(line);
1113 return 0;
1114}
1115
1116static struct pci_device_id serial_txx9_pci_tbl[] = {
1117 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC,
1118 PCI_ANY_ID, PCI_ANY_ID,
1119 0, 0, 0 },
1120 { 0, }
1121};
1122
1123static struct pci_driver serial_txx9_pci_driver = {
1124 .name = "serial_txx9",
1125 .probe = pciserial_txx9_init_one,
1126 .remove = __devexit_p(pciserial_txx9_remove_one),
1127 .suspend = pciserial_txx9_suspend_one,
1128 .resume = pciserial_txx9_resume_one,
1129 .id_table = serial_txx9_pci_tbl,
1130};
1131
1132MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1133#endif /* ENABLE_SERIAL_TXX9_PCI */
1134
1135static int __init serial_txx9_init(void)
1136{
1137 int ret;
1138
1139 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1140
1141 ret = uart_register_driver(&serial_txx9_reg);
1142 if (ret >= 0) {
1143 serial_txx9_register_ports(&serial_txx9_reg);
1144
1145#ifdef ENABLE_SERIAL_TXX9_PCI
1146 ret = pci_module_init(&serial_txx9_pci_driver);
1147#endif
1148 }
1149 return ret;
1150}
1151
1152static void __exit serial_txx9_exit(void)
1153{
1154 int i;
1155
1156#ifdef ENABLE_SERIAL_TXX9_PCI
1157 pci_unregister_driver(&serial_txx9_pci_driver);
1158#endif
1159 for (i = 0; i < UART_NR; i++)
1160 uart_remove_one_port(&serial_txx9_reg, &serial_txx9_ports[i].port);
1161
1162 uart_unregister_driver(&serial_txx9_reg);
1163}
1164
1165module_init(serial_txx9_init);
1166module_exit(serial_txx9_exit);
1167
1168MODULE_LICENSE("GPL");
1169MODULE_DESCRIPTION("TX39/49 serial driver");
1170
1171MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
Linux kernel - Deliverables
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