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1da177e4 LT |
1 | /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $ |
2 | * | |
3 | * linux/drivers/serial/sh-sci.h | |
4 | * | |
5 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
6 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
7 | * Copyright (C) 2000 Greg Banks | |
8 | * Copyright (C) 2002, 2003 Paul Mundt | |
9 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
10 | * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). | |
11 | * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). | |
12 | */ | |
1da177e4 | 13 | #include <linux/serial_core.h> |
e108b2ca | 14 | #include <asm/io.h> |
1da177e4 LT |
15 | |
16 | #if defined(__H8300H__) || defined(__H8300S__) | |
17 | #include <asm/gpio.h> | |
18 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
19 | #include <asm/regs306x.h> | |
20 | #endif | |
21 | #if defined(CONFIG_H8S2678) | |
22 | #include <asm/regs267x.h> | |
23 | #endif | |
24 | #endif | |
25 | ||
1da177e4 | 26 | #if defined(CONFIG_CPU_SUBTYPE_SH7708) |
1da177e4 LT |
27 | # define SCSPTR 0xffffff7c /* 8 bit */ |
28 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
29 | # define SCI_ONLY | |
e108b2ca PM |
30 | #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
31 | defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | |
32 | defined(CONFIG_CPU_SUBTYPE_SH7706) | |
1da177e4 LT |
33 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
34 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | |
35 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
36 | # define SCI_AND_SCIF | |
37 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
38 | # define SCIF0 0xA4400000 | |
39 | # define SCIF2 0xA4410000 | |
b7a76e4b PM |
40 | # define SCSMR_Ir 0xA44A0000 |
41 | # define IRDA_SCIF SCIF0 | |
1da177e4 LT |
42 | # define SCPCR 0xA4000116 |
43 | # define SCPDR 0xA4000136 | |
44 | ||
45 | /* Set the clock source, | |
46 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | |
47 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | |
48 | */ | |
49 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | |
50 | # define SCIF_ONLY | |
51 | #elif defined(CONFIG_SH_RTS7751R2D) | |
1da177e4 LT |
52 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
53 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
54 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
55 | # define SCIF_ONLY | |
56 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) | |
1da177e4 LT |
57 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
58 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
59 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
60 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | |
61 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
62 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | |
63 | # define SCI_AND_SCIF | |
64 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | |
b7a76e4b PM |
65 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
66 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | |
67 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | |
1da177e4 LT |
68 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
69 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
70 | # define SCIF_ONLY | |
71 | #elif defined(CONFIG_CPU_SUBTYPE_SH7300) | |
1da177e4 LT |
72 | # define SCPCR 0xA4050116 /* 16 bit SCIF */ |
73 | # define SCPDR 0xA4050136 /* 16 bit SCIF */ | |
74 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
75 | # define SCIF_ONLY | |
e108b2ca PM |
76 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) |
77 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ | |
78 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
79 | # define SCIF_ONLY | |
1da177e4 | 80 | #elif defined(CONFIG_CPU_SUBTYPE_SH73180) |
1da177e4 LT |
81 | # define SCPDR 0xA4050138 /* 16 bit SCIF */ |
82 | # define SCSPTR2 SCPDR | |
83 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
84 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
85 | # define SCIF_ONLY | |
e108b2ca PM |
86 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
87 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | |
88 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | |
89 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | |
90 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | |
91 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | |
92 | # define SCIF_ONLY | |
41504c39 PM |
93 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
94 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
95 | # define SCSPTR0 SCPDR0 | |
96 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
97 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
98 | # define SCIF_ONLY | |
99 | # define PORT_PSCR 0xA405011E | |
1da177e4 | 100 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
1da177e4 LT |
101 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
102 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
103 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
104 | # define SCIF_ONLY | |
105 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) | |
1da177e4 LT |
106 | # define SCSPTR1 0xffe00020 /* 16 bit SCIF */ |
107 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | |
108 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
109 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
110 | # define SCIF_ONLY | |
111 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | |
112 | # include <asm/hardware.h> | |
113 | # define SCIF_BASE_ADDR 0x01030000 | |
114 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | |
115 | # define SCIF_PTR2_OFFS 0x0000020 | |
116 | # define SCIF_LSR2_OFFS 0x0000024 | |
1da177e4 LT |
117 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
118 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | |
119 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, | |
120 | TE=1,RE=1,REIE=1 */ | |
121 | # define SCIF_ONLY | |
122 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
1da177e4 LT |
123 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
124 | # define SCI_ONLY | |
125 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | |
126 | #elif defined(CONFIG_H8S2678) | |
1da177e4 LT |
127 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
128 | # define SCI_ONLY | |
129 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | |
b7a76e4b PM |
130 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
131 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | |
132 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | |
133 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | |
134 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
135 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | |
136 | # define SCIF_ONLY | |
137 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
138 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
139 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | |
e108b2ca | 140 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
b7a76e4b PM |
141 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
142 | # define SCIF_ONLY | |
9d4436a6 YS |
143 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
144 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ | |
145 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | |
146 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | |
147 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | |
148 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
149 | # define SCIF_ONLY | |
150 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
151 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | |
152 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | |
153 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | |
154 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
155 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
156 | # define SCIF_ONLY | |
1da177e4 LT |
157 | #else |
158 | # error CPU subtype not defined | |
159 | #endif | |
160 | ||
161 | /* SCSCR */ | |
162 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ | |
163 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | |
164 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | |
165 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | |
b7a76e4b | 166 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780) |
1da177e4 LT |
167 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
168 | #else | |
169 | #define SCI_CTRL_FLAGS_REIE 0 | |
170 | #endif | |
171 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
172 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
173 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ | |
174 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ | |
175 | ||
176 | /* SCxSR SCI */ | |
177 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
178 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
179 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
180 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
181 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
182 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
183 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
184 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
185 | ||
186 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | |
187 | ||
188 | /* SCxSR SCIF */ | |
189 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
190 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
191 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
192 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
193 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
194 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
195 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
196 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
197 | ||
198 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | |
199 | #define SCIF_ORER 0x0200 | |
200 | #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | |
201 | #define SCIF_RFDC_MASK 0x007f | |
202 | #define SCIF_TXROOM_MAX 64 | |
203 | #else | |
204 | #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) | |
205 | #define SCIF_RFDC_MASK 0x001f | |
206 | #define SCIF_TXROOM_MAX 16 | |
207 | #endif | |
208 | ||
209 | #if defined(SCI_ONLY) | |
210 | # define SCxSR_TEND(port) SCI_TEND | |
211 | # define SCxSR_ERRORS(port) SCI_ERRORS | |
212 | # define SCxSR_RDxF(port) SCI_RDRF | |
213 | # define SCxSR_TDxE(port) SCI_TDRE | |
214 | # define SCxSR_ORER(port) SCI_ORER | |
215 | # define SCxSR_FER(port) SCI_FER | |
216 | # define SCxSR_PER(port) SCI_PER | |
217 | # define SCxSR_BRK(port) 0x00 | |
218 | # define SCxSR_RDxF_CLEAR(port) 0xbc | |
219 | # define SCxSR_ERROR_CLEAR(port) 0xc4 | |
220 | # define SCxSR_TDxE_CLEAR(port) 0x78 | |
b7a76e4b | 221 | # define SCxSR_BREAK_CLEAR(port) 0xc4 |
1da177e4 LT |
222 | #elif defined(SCIF_ONLY) |
223 | # define SCxSR_TEND(port) SCIF_TEND | |
224 | # define SCxSR_ERRORS(port) SCIF_ERRORS | |
225 | # define SCxSR_RDxF(port) SCIF_RDF | |
226 | # define SCxSR_TDxE(port) SCIF_TDFE | |
227 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | |
228 | # define SCxSR_ORER(port) SCIF_ORER | |
229 | #else | |
230 | # define SCxSR_ORER(port) 0x0000 | |
231 | #endif | |
232 | # define SCxSR_FER(port) SCIF_FER | |
233 | # define SCxSR_PER(port) SCIF_PER | |
234 | # define SCxSR_BRK(port) SCIF_BRK | |
235 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | |
236 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) | |
237 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) | |
238 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) | |
239 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) | |
240 | #else | |
241 | /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */ | |
242 | # define SCxSR_RDxF_CLEAR(port) 0x00fc | |
243 | # define SCxSR_ERROR_CLEAR(port) 0x0073 | |
244 | # define SCxSR_TDxE_CLEAR(port) 0x00df | |
b7a76e4b | 245 | # define SCxSR_BREAK_CLEAR(port) 0x00e3 |
1da177e4 LT |
246 | #endif |
247 | #else | |
248 | # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) | |
249 | # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | |
250 | # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | |
251 | # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
252 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) | |
253 | # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
254 | # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
255 | # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
256 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) | |
257 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
258 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
259 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
260 | #endif | |
261 | ||
262 | /* SCFCR */ | |
263 | #define SCFCR_RFRST 0x0002 | |
264 | #define SCFCR_TFRST 0x0004 | |
265 | #define SCFCR_TCRST 0x4000 | |
266 | #define SCFCR_MCE 0x0008 | |
267 | ||
268 | #define SCI_MAJOR 204 | |
269 | #define SCI_MINOR_START 8 | |
270 | ||
271 | /* Generic serial flags */ | |
272 | #define SCI_RX_THROTTLE 0x0000001 | |
273 | ||
274 | #define SCI_MAGIC 0xbabeface | |
275 | ||
276 | /* | |
277 | * Events are used to schedule things to happen at timer-interrupt | |
278 | * time, instead of at rs interrupt time. | |
279 | */ | |
280 | #define SCI_EVENT_WRITE_WAKEUP 0 | |
281 | ||
1da177e4 LT |
282 | #define SCI_IN(size, offset) \ |
283 | unsigned int addr = port->mapbase + (offset); \ | |
b7a76e4b | 284 | if ((size) == 8) { \ |
1da177e4 | 285 | return ctrl_inb(addr); \ |
b7a76e4b | 286 | } else { \ |
1da177e4 LT |
287 | return ctrl_inw(addr); \ |
288 | } | |
289 | #define SCI_OUT(size, offset, value) \ | |
290 | unsigned int addr = port->mapbase + (offset); \ | |
b7a76e4b | 291 | if ((size) == 8) { \ |
1da177e4 LT |
292 | ctrl_outb(value, addr); \ |
293 | } else { \ | |
294 | ctrl_outw(value, addr); \ | |
295 | } | |
296 | ||
297 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | |
298 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
299 | { \ | |
b7a76e4b | 300 | if (port->type == PORT_SCI) { \ |
1da177e4 LT |
301 | SCI_IN(sci_size, sci_offset) \ |
302 | } else { \ | |
b7a76e4b | 303 | SCI_IN(scif_size, scif_offset); \ |
1da177e4 LT |
304 | } \ |
305 | } \ | |
306 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
307 | { \ | |
308 | if (port->type == PORT_SCI) { \ | |
309 | SCI_OUT(sci_size, sci_offset, value) \ | |
310 | } else { \ | |
311 | SCI_OUT(scif_size, scif_offset, value); \ | |
312 | } \ | |
313 | } | |
314 | ||
315 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
316 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
317 | { \ | |
b7a76e4b | 318 | SCI_IN(scif_size, scif_offset); \ |
1da177e4 LT |
319 | } \ |
320 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
321 | { \ | |
322 | SCI_OUT(scif_size, scif_offset, value); \ | |
323 | } | |
324 | ||
325 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | |
326 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | |
327 | { \ | |
b7a76e4b | 328 | SCI_IN(sci_size, sci_offset); \ |
1da177e4 LT |
329 | } \ |
330 | static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ | |
331 | { \ | |
332 | SCI_OUT(sci_size, sci_offset, value); \ | |
333 | } | |
334 | ||
335 | #ifdef CONFIG_CPU_SH3 | |
e108b2ca PM |
336 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ |
337 | defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | |
338 | defined(CONFIG_CPU_SUBTYPE_SH7710) | |
1da177e4 LT |
339 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
340 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
341 | #else | |
342 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
343 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
344 | h8_sci_offset, h8_sci_size) \ | |
345 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) | |
346 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
347 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | |
348 | #endif | |
349 | #elif defined(__H8300H__) || defined(__H8300S__) | |
350 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
351 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
352 | h8_sci_offset, h8_sci_size) \ | |
353 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | |
354 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) | |
355 | #else | |
356 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
357 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
358 | h8_sci_offset, h8_sci_size) \ | |
359 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
360 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
361 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
362 | #endif | |
363 | ||
e108b2ca PM |
364 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ |
365 | defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | |
366 | defined(CONFIG_CPU_SUBTYPE_SH7710) | |
1da177e4 LT |
367 | SCIF_FNS(SCSMR, 0x00, 16) |
368 | SCIF_FNS(SCBRR, 0x04, 8) | |
369 | SCIF_FNS(SCSCR, 0x08, 16) | |
370 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
371 | SCIF_FNS(SCFER, 0x10, 16) | |
372 | SCIF_FNS(SCxSR, 0x14, 16) | |
373 | SCIF_FNS(SCFCR, 0x18, 16) | |
374 | SCIF_FNS(SCFDR, 0x1c, 16) | |
375 | SCIF_FNS(SCxTDR, 0x20, 8) | |
376 | SCIF_FNS(SCxRDR, 0x24, 8) | |
377 | SCIF_FNS(SCLSR, 0x24, 16) | |
378 | #else | |
379 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | |
380 | /* name off sz off sz off sz off sz off sz*/ | |
381 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | |
382 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | |
383 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | |
384 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |
385 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | |
386 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | |
387 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | |
b7a76e4b | 388 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) |
6fc21b82 | 389 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
b7a76e4b PM |
390 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
391 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
392 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
393 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
394 | #else | |
1da177e4 LT |
395 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
396 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) | |
397 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) | |
398 | #endif | |
b7a76e4b | 399 | #endif |
1da177e4 LT |
400 | #define sci_in(port, reg) sci_##reg##_in(port) |
401 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | |
402 | ||
403 | /* H8/300 series SCI pins assignment */ | |
404 | #if defined(__H8300H__) || defined(__H8300S__) | |
405 | static const struct __attribute__((packed)) { | |
406 | int port; /* GPIO port no */ | |
407 | unsigned short rx,tx; /* GPIO bit no */ | |
408 | } h8300_sci_pins[] = { | |
409 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
410 | { /* SCI0 */ | |
411 | .port = H8300_GPIO_P9, | |
412 | .rx = H8300_GPIO_B2, | |
413 | .tx = H8300_GPIO_B0, | |
414 | }, | |
415 | { /* SCI1 */ | |
416 | .port = H8300_GPIO_P9, | |
417 | .rx = H8300_GPIO_B3, | |
418 | .tx = H8300_GPIO_B1, | |
419 | }, | |
420 | { /* SCI2 */ | |
421 | .port = H8300_GPIO_PB, | |
422 | .rx = H8300_GPIO_B7, | |
423 | .tx = H8300_GPIO_B6, | |
424 | } | |
425 | #elif defined(CONFIG_H8S2678) | |
426 | { /* SCI0 */ | |
427 | .port = H8300_GPIO_P3, | |
428 | .rx = H8300_GPIO_B2, | |
429 | .tx = H8300_GPIO_B0, | |
430 | }, | |
431 | { /* SCI1 */ | |
432 | .port = H8300_GPIO_P3, | |
433 | .rx = H8300_GPIO_B3, | |
434 | .tx = H8300_GPIO_B1, | |
435 | }, | |
436 | { /* SCI2 */ | |
437 | .port = H8300_GPIO_P5, | |
438 | .rx = H8300_GPIO_B1, | |
439 | .tx = H8300_GPIO_B0, | |
440 | } | |
441 | #endif | |
442 | }; | |
443 | #endif | |
444 | ||
445 | #if defined(CONFIG_CPU_SUBTYPE_SH7708) | |
446 | static inline int sci_rxd_in(struct uart_port *port) | |
447 | { | |
448 | if (port->mapbase == 0xfffffe80) | |
449 | return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */ | |
450 | return 1; | |
451 | } | |
e108b2ca PM |
452 | #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
453 | defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | |
454 | defined(CONFIG_CPU_SUBTYPE_SH7706) | |
1da177e4 LT |
455 | static inline int sci_rxd_in(struct uart_port *port) |
456 | { | |
457 | if (port->mapbase == 0xfffffe80) | |
458 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
459 | if (port->mapbase == 0xa4000150) | |
460 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
461 | if (port->mapbase == 0xa4000140) | |
462 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
463 | return 1; | |
464 | } | |
465 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
466 | static inline int sci_rxd_in(struct uart_port *port) | |
467 | { | |
468 | if (port->mapbase == SCIF0) | |
469 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
470 | if (port->mapbase == SCIF2) | |
471 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
472 | return 1; | |
473 | } | |
e108b2ca PM |
474 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) |
475 | static inline int sci_rxd_in(struct uart_port *port) | |
476 | { | |
477 | if (port->mapbase == SCSPTR0) | |
478 | return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0; | |
479 | return 1; | |
480 | } | |
1da177e4 LT |
481 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
482 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
483 | defined(CONFIG_CPU_SUBTYPE_SH4_202) | |
484 | static inline int sci_rxd_in(struct uart_port *port) | |
485 | { | |
486 | #ifndef SCIF_ONLY | |
487 | if (port->mapbase == 0xffe00000) | |
488 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
489 | #endif | |
490 | #ifndef SCI_ONLY | |
491 | if (port->mapbase == 0xffe80000) | |
492 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
493 | #endif | |
494 | return 1; | |
495 | } | |
496 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | |
497 | static inline int sci_rxd_in(struct uart_port *port) | |
498 | { | |
499 | if (port->mapbase == 0xfe600000) | |
500 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
501 | if (port->mapbase == 0xfe610000) | |
502 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
503 | if (port->mapbase == 0xfe620000) | |
504 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 505 | return 1; |
1da177e4 LT |
506 | } |
507 | #elif defined(CONFIG_CPU_SUBTYPE_SH7300) | |
508 | static inline int sci_rxd_in(struct uart_port *port) | |
509 | { | |
510 | if (port->mapbase == 0xa4430000) | |
511 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ | |
512 | return 1; | |
513 | } | |
514 | #elif defined(CONFIG_CPU_SUBTYPE_SH73180) | |
515 | static inline int sci_rxd_in(struct uart_port *port) | |
516 | { | |
517 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ | |
518 | } | |
e108b2ca PM |
519 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
520 | static inline int sci_rxd_in(struct uart_port *port) | |
521 | { | |
522 | if (port->mapbase == 0xffe00000) | |
523 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
524 | if (port->mapbase == 0xffe10000) | |
525 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
526 | if (port->mapbase == 0xffe20000) | |
527 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
528 | if (port->mapbase == 0xffe30000) | |
529 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
530 | return 1; | |
531 | } | |
41504c39 PM |
532 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
533 | static inline int sci_rxd_in(struct uart_port *port) | |
534 | { | |
535 | if (port->mapbase == 0xffe00000) | |
536 | return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | |
537 | return 1; | |
538 | } | |
1da177e4 LT |
539 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) |
540 | static inline int sci_rxd_in(struct uart_port *port) | |
541 | { | |
542 | if (port->mapbase == 0xffe00000) | |
543 | return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */ | |
544 | else | |
545 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
546 | ||
547 | } | |
548 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | |
549 | static inline int sci_rxd_in(struct uart_port *port) | |
550 | { | |
551 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ | |
552 | } | |
553 | #elif defined(__H8300H__) || defined(__H8300S__) | |
554 | static inline int sci_rxd_in(struct uart_port *port) | |
555 | { | |
556 | int ch = (port->mapbase - SMR0) >> 3; | |
557 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | |
558 | } | |
b7a76e4b PM |
559 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
560 | static inline int sci_rxd_in(struct uart_port *port) | |
561 | { | |
562 | if (port->mapbase == 0xff923000) | |
563 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
564 | if (port->mapbase == 0xff924000) | |
565 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
566 | if (port->mapbase == 0xff925000) | |
567 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 568 | return 1; |
b7a76e4b PM |
569 | } |
570 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
571 | static inline int sci_rxd_in(struct uart_port *port) | |
572 | { | |
573 | if (port->mapbase == 0xffe00000) | |
574 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
575 | if (port->mapbase == 0xffe10000) | |
576 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 577 | return 1; |
b7a76e4b | 578 | } |
9d4436a6 YS |
579 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
580 | static inline int sci_rxd_in(struct uart_port *port) | |
581 | { | |
582 | if (port->mapbase == 0xfffe8000) | |
583 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
584 | if (port->mapbase == 0xfffe8800) | |
585 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
586 | if (port->mapbase == 0xfffe9000) | |
587 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
588 | if (port->mapbase == 0xfffe9800) | |
589 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 590 | return 1; |
9d4436a6 YS |
591 | } |
592 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
593 | static inline int sci_rxd_in(struct uart_port *port) | |
594 | { | |
595 | if (port->mapbase == 0xf8400000) | |
596 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
597 | if (port->mapbase == 0xf8410000) | |
598 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
599 | if (port->mapbase == 0xf8420000) | |
600 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
31388750 | 601 | return 1; |
9d4436a6 | 602 | } |
1da177e4 LT |
603 | #endif |
604 | ||
605 | /* | |
606 | * Values for the BitRate Register (SCBRR) | |
607 | * | |
608 | * The values are actually divisors for a frequency which can | |
609 | * be internal to the SH3 (14.7456MHz) or derived from an external | |
610 | * clock source. This driver assumes the internal clock is used; | |
611 | * to support using an external clock source, config options or | |
612 | * possibly command-line options would need to be added. | |
613 | * | |
614 | * Also, to support speeds below 2400 (why?) the lower 2 bits of | |
615 | * the SCSMR register would also need to be set to non-zero values. | |
616 | * | |
617 | * -- Greg Banks 27Feb2000 | |
618 | * | |
619 | * Answer: The SCBRR register is only eight bits, and the value in | |
620 | * it gets larger with lower baud rates. At around 2400 (depending on | |
621 | * the peripherial module clock) you run out of bits. However the | |
622 | * lower two bits of SCSMR allow the module clock to be divided down, | |
623 | * scaling the value which is needed in SCBRR. | |
624 | * | |
625 | * -- Stuart Menefy - 23 May 2000 | |
626 | * | |
627 | * I meant, why would anyone bother with bitrates below 2400. | |
628 | * | |
629 | * -- Greg Banks - 7Jul2000 | |
630 | * | |
631 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper | |
632 | * tape reader as a console! | |
633 | * | |
634 | * -- Mitch Davis - 15 Jul 2000 | |
635 | */ | |
636 | ||
b7a76e4b PM |
637 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780) |
638 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) | |
1da177e4 | 639 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
b7a76e4b PM |
640 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
641 | #elif defined(__H8300H__) || defined(__H8300S__) | |
1da177e4 | 642 | #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) |
b7a76e4b PM |
643 | #elif defined(CONFIG_SUPERH64) |
644 | #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1) | |
645 | #else /* Generic SH */ | |
646 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | |
1da177e4 | 647 | #endif |