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serial: DZ11: avoid a hang at console switch-over
[deliverable/linux.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4 1#include <linux/serial_core.h>
e108b2ca 2#include <asm/io.h>
1da177e4 3#include <asm/gpio.h>
3ea6bc3d 4
1da177e4
LT		 5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
1da177e4 11
0fbde950
MD		 12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19# define SCI_AND_SCIF
20#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
21# define SCIF0 0xA4400000
22# define SCIF2 0xA4410000
b7a76e4b
PM		 23# define SCSMR_Ir 0xA44A0000
24# define IRDA_SCIF SCIF0
1da177e4
LT		 25# define SCPCR 0xA4000116
26# define SCPDR 0xA4000136
27
28/* Set the clock source,
29 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
30 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
31 */
32# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
33# define SCIF_ONLY
31a49c4b
YS		 34#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7721)
3ea6bc3d
MB		 36# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
37# define SCIF_ONLY
38#define SCIF_ORER 0x0200 /* overrun error bit */
1da177e4 39#elif defined(CONFIG_SH_RTS7751R2D)
1da177e4
LT		 40# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41# define SCIF_ORER 0x0001 /* overrun error bit */
42# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
43# define SCIF_ONLY
05627486
PM		 44#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
49 defined(CONFIG_CPU_SUBTYPE_SH7751R)
1da177e4
LT		 50# define SCSPTR1 0xffe0001c /* 8 bit SCI */
51# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
52# define SCIF_ORER 0x0001 /* overrun error bit */
53# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
54 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
55 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
56# define SCI_AND_SCIF
57#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 58# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
59# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
60# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 61# define SCIF_ORER 0x0001 /* overrun error bit */
62# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
63# define SCIF_ONLY
2b1bd1ac 64#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca 65# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
9465a54f
NI		 66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define PACR 0xa4050100
68# define PBCR 0xa4050102
69# define SCSCR_INIT(port) 0x3B
e108b2ca 70# define SCIF_ONLY
e108b2ca
PM		 71#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
72# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
73# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
74# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
75# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
77# define SCIF_ONLY
41504c39 78#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
346b7463
MD		 79# define PADR 0xA4050120
80# define PSDR 0xA405013e
81# define PWDR 0xA4050166
82# define PSCR 0xA405011E
41504c39
PM		 83# define SCIF_ORER 0x0001 /* overrun error bit */
84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
85# define SCIF_ONLY
9109a30e
MD		 86#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
87# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
88# define SCSPTR0 SCPDR0
89# define SCIF_ORER 0x0001 /* overrun error bit */
90# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
178dd0cd
PM		 91#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
92# define SCSPTR0 0xa4050160
93# define SCSPTR1 0xa405013e
94# define SCSPTR2 0xa4050160
95# define SCSPTR3 0xa405013e
96# define SCSPTR4 0xa4050128
97# define SCSPTR5 0xa4050128
98# define SCIF_ORER 0x0001 /* overrun error bit */
99# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
9109a30e 100# define SCIF_ONLY
1da177e4 101#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 102# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
103# define SCIF_ORER 0x0001 /* overrun error bit */
104# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
105# define SCIF_ONLY
1da177e4 106#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1da177e4
LT		 107# define SCIF_BASE_ADDR 0x01030000
108# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
109# define SCIF_PTR2_OFFS 0x0000020
110# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 111# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
112# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
f9669187 113# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
1da177e4
LT		 114# define SCIF_ONLY
115#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4
LT		 116# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
117# define SCI_ONLY
118# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
119#elif defined(CONFIG_H8S2678)
1da177e4
LT		 120# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
121# define SCI_ONLY
122# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
7d740a06
YS		 123#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
124# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
125# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
126# define SCIF_ORER 0x0001 /* overrun error bit */
127# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
128# define SCIF_ONLY
b7a76e4b
PM		 129#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
130# define SCSPTR0 0xff923020 /* 16 bit SCIF */
131# define SCSPTR1 0xff924020 /* 16 bit SCIF */
132# define SCSPTR2 0xff925020 /* 16 bit SCIF */
133# define SCIF_ORER 0x0001 /* overrun error bit */
134# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
135# define SCIF_ONLY
136#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
137# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
138# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 139# define SCIF_ORER 0x0001 /* Overrun error bit */
b7a76e4b
PM		 140# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
141# define SCIF_ONLY
32351a28
PM		 142#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
143# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
144# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
145# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
146# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
147# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
148# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
149# define SCIF_OPER 0x0001 /* Overrun error bit */
150# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
151# define SCIF_ONLY
6d01f510 152#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 153 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
154 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 155# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
156# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
157# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
158# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
159# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
160# define SCIF_ONLY
161#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
162# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
163# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
164# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
165# define SCIF_ORER 0x0001 /* overrun error bit */
166# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
167# define SCIF_ONLY
2b1bd1ac
PM		 168#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
169# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
170# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
171# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
172# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
173# define SCIF_ORER 0x0001 /* Overrun error bit */
174# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
175# define SCIF_ONLY
1da177e4
LT		 176#else
177# error CPU subtype not defined
178#endif
179
180/* SCSCR */
181#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
182#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
183#define SCI_CTRL_FLAGS_TE 0x20 /* all */
184#define SCI_CTRL_FLAGS_RE 0x10 /* all */
05627486
PM		 185#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
190 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac
PM		 192 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
193 defined(CONFIG_CPU_SUBTYPE_SHX3)
1da177e4
LT		 194#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
195#else
196#define SCI_CTRL_FLAGS_REIE 0
197#endif
198/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
201/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
202
203/* SCxSR SCI */
204#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
208#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
209#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
211/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
212
213#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
214
215/* SCxSR SCIF */
216#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
220#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
221#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
223#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
224
3ea6bc3d 225#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 226 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
227 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 228#define SCIF_ORER 0x0200
229#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
230#define SCIF_RFDC_MASK 0x007f
231#define SCIF_TXROOM_MAX 64
232#else
233#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
234#define SCIF_RFDC_MASK 0x001f
235#define SCIF_TXROOM_MAX 16
236#endif
237
238#if defined(SCI_ONLY)
239# define SCxSR_TEND(port) SCI_TEND
240# define SCxSR_ERRORS(port) SCI_ERRORS
241# define SCxSR_RDxF(port) SCI_RDRF
242# define SCxSR_TDxE(port) SCI_TDRE
243# define SCxSR_ORER(port) SCI_ORER
244# define SCxSR_FER(port) SCI_FER
245# define SCxSR_PER(port) SCI_PER
246# define SCxSR_BRK(port) 0x00
247# define SCxSR_RDxF_CLEAR(port) 0xbc
248# define SCxSR_ERROR_CLEAR(port) 0xc4
249# define SCxSR_TDxE_CLEAR(port) 0x78
b7a76e4b 250# define SCxSR_BREAK_CLEAR(port) 0xc4
1da177e4
LT		 251#elif defined(SCIF_ONLY)
252# define SCxSR_TEND(port) SCIF_TEND
253# define SCxSR_ERRORS(port) SCIF_ERRORS
254# define SCxSR_RDxF(port) SCIF_RDF
255# define SCxSR_TDxE(port) SCIF_TDFE
d89ddd1c 256#if defined(CONFIG_CPU_SUBTYPE_SH7705)
1da177e4
LT		 257# define SCxSR_ORER(port) SCIF_ORER
258#else
259# define SCxSR_ORER(port) 0x0000
260#endif
261# define SCxSR_FER(port) SCIF_FER
262# define SCxSR_PER(port) SCIF_PER
263# define SCxSR_BRK(port) SCIF_BRK
3ea6bc3d 264#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 265 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
266 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 267# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
268# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
269# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
270# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
271#else
d89ddd1c 272/* SH7705 can also use this, clearing is same between 7705 and 7709 */
1da177e4
LT		 273# define SCxSR_RDxF_CLEAR(port) 0x00fc
274# define SCxSR_ERROR_CLEAR(port) 0x0073
275# define SCxSR_TDxE_CLEAR(port) 0x00df
b7a76e4b 276# define SCxSR_BREAK_CLEAR(port) 0x00e3
1da177e4
LT		 277#endif
278#else
279# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
280# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
281# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
282# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
283# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
284# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
285# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
286# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
287# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
288# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
289# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
290# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
291#endif
292
293/* SCFCR */
294#define SCFCR_RFRST 0x0002
295#define SCFCR_TFRST 0x0004
296#define SCFCR_TCRST 0x4000
297#define SCFCR_MCE 0x0008
298
299#define SCI_MAJOR 204
300#define SCI_MINOR_START 8
301
302/* Generic serial flags */
303#define SCI_RX_THROTTLE 0x0000001
304
305#define SCI_MAGIC 0xbabeface
306
307/*
308 * Events are used to schedule things to happen at timer-interrupt
309 * time, instead of at rs interrupt time.
310 */
311#define SCI_EVENT_WRITE_WAKEUP 0
312
1da177e4
LT		 313#define SCI_IN(size, offset) \
314 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 315 if ((size) == 8) { \
1da177e4 316 return ctrl_inb(addr); \
b7a76e4b 317 } else { \
1da177e4
LT		 318 return ctrl_inw(addr); \
319 }
320#define SCI_OUT(size, offset, value) \
321 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 322 if ((size) == 8) { \
1da177e4 323 ctrl_outb(value, addr); \
3d2c2f3e 324 } else if ((size) == 16) { \
1da177e4
LT		 325 ctrl_outw(value, addr); \
326 }
327
328#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
329 static inline unsigned int sci_##name##_in(struct uart_port *port) \
330 { \
b7a76e4b 331 if (port->type == PORT_SCI) { \
1da177e4
LT		 332 SCI_IN(sci_size, sci_offset) \
333 } else { \
b7a76e4b 334 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 335 } \
336 } \
337 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
338 { \
339 if (port->type == PORT_SCI) { \
340 SCI_OUT(sci_size, sci_offset, value) \
341 } else { \
342 SCI_OUT(scif_size, scif_offset, value); \
343 } \
344 }
345
346#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
347 static inline unsigned int sci_##name##_in(struct uart_port *port) \
348 { \
b7a76e4b 349 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 350 } \
351 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
352 { \
353 SCI_OUT(scif_size, scif_offset, value); \
354 }
355
356#define CPU_SCI_FNS(name, sci_offset, sci_size) \
357 static inline unsigned int sci_##name##_in(struct uart_port* port) \
358 { \
b7a76e4b 359 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 360 } \
361 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
362 { \
363 SCI_OUT(sci_size, sci_offset, value); \
364 }
365
366#ifdef CONFIG_CPU_SH3
9465a54f
NI		 367#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
368#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
369 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
370 h8_sci_offset, h8_sci_size) \
371 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
372#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
373 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
3ea6bc3d 374#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 375 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
376 defined(CONFIG_CPU_SUBTYPE_SH7721)
1da177e4
LT		 377#define SCIF_FNS(name, scif_offset, scif_size) \
378 CPU_SCIF_FNS(name, scif_offset, scif_size)
379#else
380#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
381 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
382 h8_sci_offset, h8_sci_size) \
383 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
384#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
385 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
386#endif
387#elif defined(__H8300H__) || defined(__H8300S__)
388#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
389 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
390 h8_sci_offset, h8_sci_size) \
391 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
392#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
178dd0cd
PM		 393#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
394 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
395 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
396 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
397 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
1da177e4
LT		 398#else
399#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
400 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
401 h8_sci_offset, h8_sci_size) \
402 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
403#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
404 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
405#endif
406
3ea6bc3d 407#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 408 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
409 defined(CONFIG_CPU_SUBTYPE_SH7721)
9465a54f 410
1da177e4
LT		 411SCIF_FNS(SCSMR, 0x00, 16)
412SCIF_FNS(SCBRR, 0x04, 8)
413SCIF_FNS(SCSCR, 0x08, 16)
414SCIF_FNS(SCTDSR, 0x0c, 8)
415SCIF_FNS(SCFER, 0x10, 16)
416SCIF_FNS(SCxSR, 0x14, 16)
417SCIF_FNS(SCFCR, 0x18, 16)
418SCIF_FNS(SCFDR, 0x1c, 16)
419SCIF_FNS(SCxTDR, 0x20, 8)
420SCIF_FNS(SCxRDR, 0x24, 8)
421SCIF_FNS(SCLSR, 0x24, 16)
178dd0cd
PM		 422#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
423SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
424SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
425SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
426SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
427SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
428SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
429SCIF_FNS(SCTDSR, 0x0c, 8)
430SCIF_FNS(SCFER, 0x10, 16)
431SCIF_FNS(SCFCR, 0x18, 16)
432SCIF_FNS(SCFDR, 0x1c, 16)
433SCIF_FNS(SCLSR, 0x24, 16)
1da177e4
LT		 434#else
435/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
436/* name off sz off sz off sz off sz off sz*/
437SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
438SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
439SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
440SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
441SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
442SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
443SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
32351a28 444#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
7d740a06 445 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
32351a28
PM		 446 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
447 defined(CONFIG_CPU_SUBTYPE_SH7785)
6fc21b82 448SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 449SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
450SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
451SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
452SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
453#else
1da177e4 454SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
9b4e466f
MD		 455#if defined(CONFIG_CPU_SUBTYPE_SH7722)
456SCIF_FNS(SCSPTR, 0, 0, 0, 0)
457#else
1da177e4 458SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
9b4e466f 459#endif
1da177e4
LT		 460SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
461#endif
b7a76e4b 462#endif
1da177e4
LT		 463#define sci_in(port, reg) sci_##reg##_in(port)
464#define sci_out(port, reg, value) sci_##reg##_out(port, value)
465
466/* H8/300 series SCI pins assignment */
467#if defined(__H8300H__) || defined(__H8300S__)
468static const struct __attribute__((packed)) {
469 int port; /* GPIO port no */
470 unsigned short rx,tx; /* GPIO bit no */
471} h8300_sci_pins[] = {
472#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
473 { /* SCI0 */
474 .port = H8300_GPIO_P9,
475 .rx = H8300_GPIO_B2,
476 .tx = H8300_GPIO_B0,
477 },
478 { /* SCI1 */
479 .port = H8300_GPIO_P9,
480 .rx = H8300_GPIO_B3,
481 .tx = H8300_GPIO_B1,
482 },
483 { /* SCI2 */
484 .port = H8300_GPIO_PB,
485 .rx = H8300_GPIO_B7,
486 .tx = H8300_GPIO_B6,
487 }
488#elif defined(CONFIG_H8S2678)
489 { /* SCI0 */
490 .port = H8300_GPIO_P3,
491 .rx = H8300_GPIO_B2,
492 .tx = H8300_GPIO_B0,
493 },
494 { /* SCI1 */
495 .port = H8300_GPIO_P3,
496 .rx = H8300_GPIO_B3,
497 .tx = H8300_GPIO_B1,
498 },
499 { /* SCI2 */
500 .port = H8300_GPIO_P5,
501 .rx = H8300_GPIO_B1,
502 .tx = H8300_GPIO_B0,
503 }
504#endif
505};
506#endif
507
0fbde950
MD		 508#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
509 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
510 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
511 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 512static inline int sci_rxd_in(struct uart_port *port)
513{
514 if (port->mapbase == 0xfffffe80)
515 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
516 if (port->mapbase == 0xa4000150)
517 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
518 if (port->mapbase == 0xa4000140)
519 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
520 return 1;
521}
522#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
523static inline int sci_rxd_in(struct uart_port *port)
524{
525 if (port->mapbase == SCIF0)
526 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
527 if (port->mapbase == SCIF2)
528 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
529 return 1;
530}
9465a54f 531#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca
PM		 532static inline int sci_rxd_in(struct uart_port *port)
533{
9465a54f
NI		 534 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
535}
536static inline void set_sh771x_scif_pfc(struct uart_port *port)
537{
538 if (port->mapbase == 0xA4400000){
539 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
540 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
541 return;
542 }
543 if (port->mapbase == 0xA4410000){
544 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
545 return;
546 }
e108b2ca 547}
31a49c4b
YS		 548#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
549 defined(CONFIG_CPU_SUBTYPE_SH7721)
3ea6bc3d
MB		 550static inline int sci_rxd_in(struct uart_port *port)
551{
552 if (port->mapbase == 0xa4430000)
553 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
554 else if (port->mapbase == 0xa4438000)
555 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
556 return 1;
557}
05627486
PM		 558#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
559 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
560 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
561 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
562 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
563 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
1da177e4
LT		 564 defined(CONFIG_CPU_SUBTYPE_SH4_202)
565static inline int sci_rxd_in(struct uart_port *port)
566{
567#ifndef SCIF_ONLY
568 if (port->mapbase == 0xffe00000)
569 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
570#endif
571#ifndef SCI_ONLY
572 if (port->mapbase == 0xffe80000)
573 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
574#endif
575 return 1;
576}
577#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
578static inline int sci_rxd_in(struct uart_port *port)
579{
580 if (port->mapbase == 0xfe600000)
581 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
582 if (port->mapbase == 0xfe610000)
583 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
584 if (port->mapbase == 0xfe620000)
585 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 586 return 1;
1da177e4 587}
e108b2ca
PM		 588#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
589static inline int sci_rxd_in(struct uart_port *port)
590{
591 if (port->mapbase == 0xffe00000)
592 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
593 if (port->mapbase == 0xffe10000)
594 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
595 if (port->mapbase == 0xffe20000)
596 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
597 if (port->mapbase == 0xffe30000)
598 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
599 return 1;
600}
346b7463 601#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
41504c39
PM		 602static inline int sci_rxd_in(struct uart_port *port)
603{
604 if (port->mapbase == 0xffe00000)
605 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
606 return 1;
607}
346b7463
MD		 608#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
609static inline int sci_rxd_in(struct uart_port *port)
610{
611 if (port->mapbase == 0xffe00000)
612 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
613 if (port->mapbase == 0xffe10000)
614 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
615 if (port->mapbase == 0xffe20000)
616 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
617
618 return 1;
619}
178dd0cd
PM		 620#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
621static inline int sci_rxd_in(struct uart_port *port)
622{
623 if (port->mapbase == 0xffe00000)
624 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
625 if (port->mapbase == 0xffe10000)
626 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
627 if (port->mapbase == 0xffe20000)
628 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
629 if (port->mapbase == 0xa4e30000)
630 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
631 if (port->mapbase == 0xa4e40000)
632 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
633 if (port->mapbase == 0xa4e50000)
634 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
635 return 1;
636}
1da177e4
LT		 637#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
638static inline int sci_rxd_in(struct uart_port *port)
639{
640 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
641}
642#elif defined(__H8300H__) || defined(__H8300S__)
643static inline int sci_rxd_in(struct uart_port *port)
644{
645 int ch = (port->mapbase - SMR0) >> 3;
646 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
647}
7d740a06
YS		 648#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
649static inline int sci_rxd_in(struct uart_port *port)
650{
651 if (port->mapbase == 0xffe00000)
652 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
653 if (port->mapbase == 0xffe08000)
654 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
655 return 1;
656}
b7a76e4b
PM		 657#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
658static inline int sci_rxd_in(struct uart_port *port)
659{
660 if (port->mapbase == 0xff923000)
661 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
662 if (port->mapbase == 0xff924000)
663 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
664 if (port->mapbase == 0xff925000)
665 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 666 return 1;
b7a76e4b
PM		 667}
668#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
669static inline int sci_rxd_in(struct uart_port *port)
670{
671 if (port->mapbase == 0xffe00000)
672 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
673 if (port->mapbase == 0xffe10000)
674 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
31388750 675 return 1;
b7a76e4b 676}
32351a28
PM		 677#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
678static inline int sci_rxd_in(struct uart_port *port)
679{
680 if (port->mapbase == 0xffea0000)
681 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
682 if (port->mapbase == 0xffeb0000)
683 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
684 if (port->mapbase == 0xffec0000)
685 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
686 if (port->mapbase == 0xffed0000)
687 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
688 if (port->mapbase == 0xffee0000)
689 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
690 if (port->mapbase == 0xffef0000)
691 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
692 return 1;
693}
6d01f510 694#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 695 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
696 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 697static inline int sci_rxd_in(struct uart_port *port)
698{
699 if (port->mapbase == 0xfffe8000)
700 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
701 if (port->mapbase == 0xfffe8800)
702 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
703 if (port->mapbase == 0xfffe9000)
704 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
705 if (port->mapbase == 0xfffe9800)
706 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
31388750 707 return 1;
9d4436a6
YS		 708}
709#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
710static inline int sci_rxd_in(struct uart_port *port)
711{
712 if (port->mapbase == 0xf8400000)
713 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
714 if (port->mapbase == 0xf8410000)
715 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
716 if (port->mapbase == 0xf8420000)
717 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 718 return 1;
9d4436a6 719}
2b1bd1ac
PM		 720#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
721static inline int sci_rxd_in(struct uart_port *port)
722{
723 if (port->mapbase == 0xffc30000)
724 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
725 if (port->mapbase == 0xffc40000)
726 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
727 if (port->mapbase == 0xffc50000)
728 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
729 if (port->mapbase == 0xffc60000)
730 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
1760b7d7 731 return 1;
2b1bd1ac 732}
1da177e4
LT		 733#endif
734
735/*
736 * Values for the BitRate Register (SCBRR)
737 *
738 * The values are actually divisors for a frequency which can
739 * be internal to the SH3 (14.7456MHz) or derived from an external
740 * clock source. This driver assumes the internal clock is used;
741 * to support using an external clock source, config options or
742 * possibly command-line options would need to be added.
743 *
744 * Also, to support speeds below 2400 (why?) the lower 2 bits of
745 * the SCSMR register would also need to be set to non-zero values.
746 *
747 * -- Greg Banks 27Feb2000
748 *
749 * Answer: The SCBRR register is only eight bits, and the value in
750 * it gets larger with lower baud rates. At around 2400 (depending on
751 * the peripherial module clock) you run out of bits. However the
752 * lower two bits of SCSMR allow the module clock to be divided down,
753 * scaling the value which is needed in SCBRR.
754 *
755 * -- Stuart Menefy - 23 May 2000
756 *
757 * I meant, why would anyone bother with bitrates below 2400.
758 *
759 * -- Greg Banks - 7Jul2000
760 *
761 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
762 * tape reader as a console!
763 *
764 * -- Mitch Davis - 15 Jul 2000
765 */
766
7d740a06
YS		 767#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
768 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
32351a28 769 defined(CONFIG_CPU_SUBTYPE_SH7785)
b7a76e4b 770#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
3ea6bc3d 771#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b
YS		 772 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
773 defined(CONFIG_CPU_SUBTYPE_SH7721)
b7a76e4b 774#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
178dd0cd
PM		 775#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
776#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1)
b7a76e4b 777#elif defined(__H8300H__) || defined(__H8300S__)
1da177e4 778#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
b7a76e4b
PM		 779#elif defined(CONFIG_SUPERH64)
780#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
781#else /* Generic SH */
782#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 783#endif
Linux kernel - Deliverables
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