Commit | Line | Data |
---|---|---|
2967dab1 MD |
1 | /* |
2 | * Pinmuxed GPIO support for SuperH. | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
b72421d8 PM |
10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
11 | ||
2967dab1 MD |
12 | #include <linux/errno.h> |
13 | #include <linux/kernel.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/bitops.h> | |
21 | #include <linux/gpio.h> | |
b0e10211 MD |
22 | #include <linux/slab.h> |
23 | #include <linux/ioport.h> | |
24 | ||
25 | static void pfc_iounmap(struct pinmux_info *pip) | |
26 | { | |
27 | int k; | |
28 | ||
29 | for (k = 0; k < pip->num_resources; k++) | |
30 | if (pip->window[k].virt) | |
31 | iounmap(pip->window[k].virt); | |
32 | ||
33 | kfree(pip->window); | |
34 | pip->window = NULL; | |
35 | } | |
36 | ||
37 | static int pfc_ioremap(struct pinmux_info *pip) | |
38 | { | |
39 | struct resource *res; | |
40 | int k; | |
41 | ||
42 | if (!pip->num_resources) | |
43 | return 0; | |
44 | ||
45 | pip->window = kzalloc(pip->num_resources * sizeof(*pip->window), | |
46 | GFP_NOWAIT); | |
47 | if (!pip->window) | |
48 | goto err1; | |
49 | ||
50 | for (k = 0; k < pip->num_resources; k++) { | |
51 | res = pip->resource + k; | |
52 | WARN_ON(resource_type(res) != IORESOURCE_MEM); | |
53 | pip->window[k].phys = res->start; | |
54 | pip->window[k].size = resource_size(res); | |
55 | pip->window[k].virt = ioremap_nocache(res->start, | |
56 | resource_size(res)); | |
57 | if (!pip->window[k].virt) | |
58 | goto err2; | |
59 | } | |
60 | ||
61 | return 0; | |
62 | ||
63 | err2: | |
64 | pfc_iounmap(pip); | |
65 | err1: | |
66 | return -1; | |
67 | } | |
68 | ||
69 | static void __iomem *pfc_phys_to_virt(struct pinmux_info *pip, | |
70 | unsigned long address) | |
71 | { | |
72 | struct pfc_window *window; | |
73 | int k; | |
74 | ||
75 | /* scan through physical windows and convert address */ | |
76 | for (k = 0; k < pip->num_resources; k++) { | |
77 | window = pip->window + k; | |
78 | ||
79 | if (address < window->phys) | |
80 | continue; | |
81 | ||
82 | if (address >= (window->phys + window->size)) | |
83 | continue; | |
84 | ||
85 | return window->virt + (address - window->phys); | |
86 | } | |
87 | ||
88 | /* no windows defined, register must be 1:1 mapped virt:phys */ | |
89 | return (void __iomem *)address; | |
90 | } | |
2967dab1 | 91 | |
2967dab1 MD |
92 | static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) |
93 | { | |
94 | if (enum_id < r->begin) | |
95 | return 0; | |
96 | ||
97 | if (enum_id > r->end) | |
98 | return 0; | |
99 | ||
100 | return 1; | |
101 | } | |
102 | ||
b0e10211 | 103 | static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg, |
3292094e MD |
104 | unsigned long reg_width) |
105 | { | |
106 | switch (reg_width) { | |
107 | case 8: | |
b0e10211 | 108 | return ioread8(mapped_reg); |
3292094e | 109 | case 16: |
b0e10211 | 110 | return ioread16(mapped_reg); |
3292094e | 111 | case 32: |
b0e10211 | 112 | return ioread32(mapped_reg); |
3292094e MD |
113 | } |
114 | ||
115 | BUG(); | |
116 | return 0; | |
117 | } | |
118 | ||
b0e10211 | 119 | static void gpio_write_raw_reg(void __iomem *mapped_reg, |
3292094e MD |
120 | unsigned long reg_width, |
121 | unsigned long data) | |
122 | { | |
123 | switch (reg_width) { | |
124 | case 8: | |
b0e10211 | 125 | iowrite8(data, mapped_reg); |
3292094e MD |
126 | return; |
127 | case 16: | |
b0e10211 | 128 | iowrite16(data, mapped_reg); |
3292094e MD |
129 | return; |
130 | case 32: | |
b0e10211 | 131 | iowrite32(data, mapped_reg); |
3292094e MD |
132 | return; |
133 | } | |
134 | ||
135 | BUG(); | |
136 | } | |
137 | ||
92554d97 MD |
138 | static int gpio_read_bit(struct pinmux_data_reg *dr, |
139 | unsigned long in_pos) | |
140 | { | |
141 | unsigned long pos; | |
142 | ||
143 | pos = dr->reg_width - (in_pos + 1); | |
144 | ||
145 | pr_debug("read_bit: addr = %lx, pos = %ld, " | |
146 | "r_width = %ld\n", dr->reg, pos, dr->reg_width); | |
147 | ||
148 | return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; | |
149 | } | |
150 | ||
3292094e MD |
151 | static void gpio_write_bit(struct pinmux_data_reg *dr, |
152 | unsigned long in_pos, unsigned long value) | |
153 | { | |
154 | unsigned long pos; | |
155 | ||
156 | pos = dr->reg_width - (in_pos + 1); | |
157 | ||
ca6f2d7f | 158 | pr_debug("write_bit addr = %lx, value = %d, pos = %ld, " |
fd2cb0ce PM |
159 | "r_width = %ld\n", |
160 | dr->reg, !!value, pos, dr->reg_width); | |
3292094e MD |
161 | |
162 | if (value) | |
163 | set_bit(pos, &dr->reg_shadow); | |
164 | else | |
165 | clear_bit(pos, &dr->reg_shadow); | |
166 | ||
b0e10211 | 167 | gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); |
3292094e MD |
168 | } |
169 | ||
18925e11 MD |
170 | static void config_reg_helper(struct pinmux_info *gpioc, |
171 | struct pinmux_cfg_reg *crp, | |
172 | unsigned long in_pos, | |
173 | void __iomem **mapped_regp, | |
174 | unsigned long *maskp, | |
175 | unsigned long *posp) | |
2967dab1 | 176 | { |
f78a26f5 MD |
177 | int k; |
178 | ||
18925e11 | 179 | *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg); |
2967dab1 | 180 | |
f78a26f5 MD |
181 | if (crp->field_width) { |
182 | *maskp = (1 << crp->field_width) - 1; | |
183 | *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); | |
184 | } else { | |
185 | *maskp = (1 << crp->var_field_width[in_pos]) - 1; | |
186 | *posp = crp->reg_width; | |
187 | for (k = 0; k <= in_pos; k++) | |
188 | *posp -= crp->var_field_width[k]; | |
189 | } | |
18925e11 MD |
190 | } |
191 | ||
192 | static int read_config_reg(struct pinmux_info *gpioc, | |
193 | struct pinmux_cfg_reg *crp, | |
194 | unsigned long field) | |
195 | { | |
196 | void __iomem *mapped_reg; | |
197 | unsigned long mask, pos; | |
198 | ||
199 | config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos); | |
2967dab1 | 200 | |
18925e11 | 201 | pr_debug("read_reg: addr = %lx, field = %ld, " |
fd2cb0ce | 202 | "r_width = %ld, f_width = %ld\n", |
18925e11 | 203 | crp->reg, field, crp->reg_width, crp->field_width); |
2967dab1 | 204 | |
18925e11 | 205 | return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask; |
0fc64cc0 MD |
206 | } |
207 | ||
18925e11 MD |
208 | static void write_config_reg(struct pinmux_info *gpioc, |
209 | struct pinmux_cfg_reg *crp, | |
210 | unsigned long field, unsigned long value) | |
0fc64cc0 | 211 | { |
18925e11 | 212 | void __iomem *mapped_reg; |
e499ada8 | 213 | unsigned long mask, pos, data; |
0fc64cc0 | 214 | |
18925e11 | 215 | config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 216 | |
18925e11 | 217 | pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " |
fd2cb0ce | 218 | "r_width = %ld, f_width = %ld\n", |
18925e11 | 219 | crp->reg, value, field, crp->reg_width, crp->field_width); |
0fc64cc0 MD |
220 | |
221 | mask = ~(mask << pos); | |
222 | value = value << pos; | |
2967dab1 | 223 | |
e499ada8 MD |
224 | data = gpio_read_raw_reg(mapped_reg, crp->reg_width); |
225 | data &= mask; | |
226 | data |= value; | |
227 | ||
228 | if (gpioc->unlock_reg) | |
229 | gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg), | |
230 | 32, ~data); | |
231 | ||
232 | gpio_write_raw_reg(mapped_reg, crp->reg_width, data); | |
2967dab1 MD |
233 | } |
234 | ||
18801be7 | 235 | static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio) |
2967dab1 | 236 | { |
18801be7 | 237 | struct pinmux_gpio *gpiop = &gpioc->gpios[gpio]; |
2967dab1 MD |
238 | struct pinmux_data_reg *data_reg; |
239 | int k, n; | |
240 | ||
18801be7 | 241 | if (!enum_in_range(gpiop->enum_id, &gpioc->data)) |
2967dab1 MD |
242 | return -1; |
243 | ||
244 | k = 0; | |
245 | while (1) { | |
246 | data_reg = gpioc->data_regs + k; | |
247 | ||
248 | if (!data_reg->reg_width) | |
249 | break; | |
250 | ||
b0e10211 MD |
251 | data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg); |
252 | ||
2967dab1 | 253 | for (n = 0; n < data_reg->reg_width; n++) { |
18801be7 MD |
254 | if (data_reg->enum_ids[n] == gpiop->enum_id) { |
255 | gpiop->flags &= ~PINMUX_FLAG_DREG; | |
256 | gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); | |
257 | gpiop->flags &= ~PINMUX_FLAG_DBIT; | |
258 | gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); | |
2967dab1 | 259 | return 0; |
2967dab1 MD |
260 | } |
261 | } | |
262 | k++; | |
263 | } | |
264 | ||
18801be7 MD |
265 | BUG(); |
266 | ||
2967dab1 MD |
267 | return -1; |
268 | } | |
269 | ||
3292094e MD |
270 | static void setup_data_regs(struct pinmux_info *gpioc) |
271 | { | |
272 | struct pinmux_data_reg *drp; | |
273 | int k; | |
274 | ||
275 | for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++) | |
276 | setup_data_reg(gpioc, k); | |
277 | ||
278 | k = 0; | |
279 | while (1) { | |
280 | drp = gpioc->data_regs + k; | |
281 | ||
282 | if (!drp->reg_width) | |
283 | break; | |
284 | ||
b0e10211 MD |
285 | drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg, |
286 | drp->reg_width); | |
3292094e MD |
287 | k++; |
288 | } | |
289 | } | |
290 | ||
18801be7 MD |
291 | static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio, |
292 | struct pinmux_data_reg **drp, int *bitp) | |
293 | { | |
294 | struct pinmux_gpio *gpiop = &gpioc->gpios[gpio]; | |
295 | int k, n; | |
296 | ||
297 | if (!enum_in_range(gpiop->enum_id, &gpioc->data)) | |
298 | return -1; | |
299 | ||
300 | k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; | |
301 | n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; | |
302 | *drp = gpioc->data_regs + k; | |
303 | *bitp = n; | |
304 | return 0; | |
305 | } | |
306 | ||
2967dab1 | 307 | static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, |
ad4a07ff MD |
308 | struct pinmux_cfg_reg **crp, |
309 | int *fieldp, int *valuep, | |
2967dab1 MD |
310 | unsigned long **cntp) |
311 | { | |
312 | struct pinmux_cfg_reg *config_reg; | |
f78a26f5 MD |
313 | unsigned long r_width, f_width, curr_width, ncomb; |
314 | int k, m, n, pos, bit_pos; | |
2967dab1 MD |
315 | |
316 | k = 0; | |
317 | while (1) { | |
318 | config_reg = gpioc->cfg_regs + k; | |
319 | ||
320 | r_width = config_reg->reg_width; | |
321 | f_width = config_reg->field_width; | |
322 | ||
323 | if (!r_width) | |
324 | break; | |
f78a26f5 MD |
325 | |
326 | pos = 0; | |
327 | m = 0; | |
328 | for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { | |
329 | if (f_width) | |
330 | curr_width = f_width; | |
331 | else | |
332 | curr_width = config_reg->var_field_width[m]; | |
333 | ||
334 | ncomb = 1 << curr_width; | |
335 | for (n = 0; n < ncomb; n++) { | |
336 | if (config_reg->enum_ids[pos + n] == enum_id) { | |
337 | *crp = config_reg; | |
338 | *fieldp = m; | |
339 | *valuep = n; | |
340 | *cntp = &config_reg->cnt[m]; | |
341 | return 0; | |
342 | } | |
2967dab1 | 343 | } |
f78a26f5 MD |
344 | pos += ncomb; |
345 | m++; | |
2967dab1 MD |
346 | } |
347 | k++; | |
348 | } | |
349 | ||
350 | return -1; | |
351 | } | |
352 | ||
353 | static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio, | |
354 | int pos, pinmux_enum_t *enum_idp) | |
355 | { | |
356 | pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id; | |
357 | pinmux_enum_t *data = gpioc->gpio_data; | |
358 | int k; | |
359 | ||
360 | if (!enum_in_range(enum_id, &gpioc->data)) { | |
361 | if (!enum_in_range(enum_id, &gpioc->mark)) { | |
362 | pr_err("non data/mark enum_id for gpio %d\n", gpio); | |
363 | return -1; | |
364 | } | |
365 | } | |
366 | ||
367 | if (pos) { | |
368 | *enum_idp = data[pos + 1]; | |
369 | return pos + 1; | |
370 | } | |
371 | ||
372 | for (k = 0; k < gpioc->gpio_data_size; k++) { | |
373 | if (data[k] == enum_id) { | |
374 | *enum_idp = data[k + 1]; | |
375 | return k + 1; | |
376 | } | |
377 | } | |
378 | ||
379 | pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); | |
380 | return -1; | |
381 | } | |
382 | ||
2967dab1 MD |
383 | enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; |
384 | ||
0fc64cc0 MD |
385 | static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, |
386 | int pinmux_type, int cfg_mode) | |
2967dab1 MD |
387 | { |
388 | struct pinmux_cfg_reg *cr = NULL; | |
389 | pinmux_enum_t enum_id; | |
390 | struct pinmux_range *range; | |
ad4a07ff | 391 | int in_range, pos, field, value; |
2967dab1 MD |
392 | unsigned long *cntp; |
393 | ||
394 | switch (pinmux_type) { | |
395 | ||
396 | case PINMUX_TYPE_FUNCTION: | |
397 | range = NULL; | |
398 | break; | |
399 | ||
400 | case PINMUX_TYPE_OUTPUT: | |
401 | range = &gpioc->output; | |
402 | break; | |
403 | ||
404 | case PINMUX_TYPE_INPUT: | |
405 | range = &gpioc->input; | |
406 | break; | |
407 | ||
408 | case PINMUX_TYPE_INPUT_PULLUP: | |
409 | range = &gpioc->input_pu; | |
410 | break; | |
411 | ||
412 | case PINMUX_TYPE_INPUT_PULLDOWN: | |
413 | range = &gpioc->input_pd; | |
414 | break; | |
415 | ||
416 | default: | |
417 | goto out_err; | |
418 | } | |
419 | ||
420 | pos = 0; | |
421 | enum_id = 0; | |
ad4a07ff MD |
422 | field = 0; |
423 | value = 0; | |
2967dab1 MD |
424 | while (1) { |
425 | pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id); | |
426 | if (pos <= 0) | |
427 | goto out_err; | |
428 | ||
429 | if (!enum_id) | |
430 | break; | |
431 | ||
50dd3145 | 432 | /* first check if this is a function enum */ |
2967dab1 | 433 | in_range = enum_in_range(enum_id, &gpioc->function); |
50dd3145 MD |
434 | if (!in_range) { |
435 | /* not a function enum */ | |
436 | if (range) { | |
437 | /* | |
438 | * other range exists, so this pin is | |
439 | * a regular GPIO pin that now is being | |
440 | * bound to a specific direction. | |
441 | * | |
442 | * for this case we only allow function enums | |
443 | * and the enums that match the other range. | |
444 | */ | |
445 | in_range = enum_in_range(enum_id, range); | |
446 | ||
447 | /* | |
448 | * special case pass through for fixed | |
449 | * input-only or output-only pins without | |
450 | * function enum register association. | |
451 | */ | |
452 | if (in_range && enum_id == range->force) | |
453 | continue; | |
454 | } else { | |
455 | /* | |
456 | * no other range exists, so this pin | |
457 | * must then be of the function type. | |
458 | * | |
459 | * allow function type pins to select | |
460 | * any combination of function/in/out | |
461 | * in their MARK lists. | |
462 | */ | |
463 | in_range = 1; | |
464 | } | |
42eed42b MD |
465 | } |
466 | ||
2967dab1 MD |
467 | if (!in_range) |
468 | continue; | |
469 | ||
ad4a07ff MD |
470 | if (get_config_reg(gpioc, enum_id, &cr, |
471 | &field, &value, &cntp) != 0) | |
2967dab1 MD |
472 | goto out_err; |
473 | ||
474 | switch (cfg_mode) { | |
475 | case GPIO_CFG_DRYRUN: | |
18925e11 MD |
476 | if (!*cntp || |
477 | (read_config_reg(gpioc, cr, field) != value)) | |
2967dab1 MD |
478 | continue; |
479 | break; | |
480 | ||
481 | case GPIO_CFG_REQ: | |
ad4a07ff | 482 | write_config_reg(gpioc, cr, field, value); |
2967dab1 MD |
483 | *cntp = *cntp + 1; |
484 | break; | |
485 | ||
486 | case GPIO_CFG_FREE: | |
487 | *cntp = *cntp - 1; | |
488 | break; | |
489 | } | |
490 | } | |
491 | ||
492 | return 0; | |
493 | out_err: | |
494 | return -1; | |
495 | } | |
496 | ||
497 | static DEFINE_SPINLOCK(gpio_lock); | |
498 | ||
69edbba0 | 499 | static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip) |
2967dab1 | 500 | { |
69edbba0 MD |
501 | return container_of(chip, struct pinmux_info, chip); |
502 | } | |
503 | ||
504 | static int sh_gpio_request(struct gpio_chip *chip, unsigned offset) | |
505 | { | |
506 | struct pinmux_info *gpioc = chip_to_pinmux(chip); | |
2967dab1 MD |
507 | struct pinmux_data_reg *dummy; |
508 | unsigned long flags; | |
509 | int i, ret, pinmux_type; | |
510 | ||
511 | ret = -EINVAL; | |
512 | ||
513 | if (!gpioc) | |
514 | goto err_out; | |
515 | ||
516 | spin_lock_irqsave(&gpio_lock, flags); | |
517 | ||
69edbba0 | 518 | if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE) |
2967dab1 MD |
519 | goto err_unlock; |
520 | ||
521 | /* setup pin function here if no data is associated with pin */ | |
522 | ||
69edbba0 | 523 | if (get_data_reg(gpioc, offset, &dummy, &i) != 0) |
2967dab1 MD |
524 | pinmux_type = PINMUX_TYPE_FUNCTION; |
525 | else | |
526 | pinmux_type = PINMUX_TYPE_GPIO; | |
527 | ||
528 | if (pinmux_type == PINMUX_TYPE_FUNCTION) { | |
69edbba0 | 529 | if (pinmux_config_gpio(gpioc, offset, |
2967dab1 MD |
530 | pinmux_type, |
531 | GPIO_CFG_DRYRUN) != 0) | |
532 | goto err_unlock; | |
533 | ||
69edbba0 | 534 | if (pinmux_config_gpio(gpioc, offset, |
2967dab1 MD |
535 | pinmux_type, |
536 | GPIO_CFG_REQ) != 0) | |
537 | BUG(); | |
538 | } | |
539 | ||
69edbba0 MD |
540 | gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE; |
541 | gpioc->gpios[offset].flags |= pinmux_type; | |
2967dab1 MD |
542 | |
543 | ret = 0; | |
544 | err_unlock: | |
545 | spin_unlock_irqrestore(&gpio_lock, flags); | |
546 | err_out: | |
547 | return ret; | |
548 | } | |
2967dab1 | 549 | |
69edbba0 | 550 | static void sh_gpio_free(struct gpio_chip *chip, unsigned offset) |
2967dab1 | 551 | { |
69edbba0 | 552 | struct pinmux_info *gpioc = chip_to_pinmux(chip); |
2967dab1 MD |
553 | unsigned long flags; |
554 | int pinmux_type; | |
555 | ||
556 | if (!gpioc) | |
557 | return; | |
558 | ||
559 | spin_lock_irqsave(&gpio_lock, flags); | |
560 | ||
69edbba0 MD |
561 | pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE; |
562 | pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE); | |
563 | gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE; | |
564 | gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE; | |
2967dab1 MD |
565 | |
566 | spin_unlock_irqrestore(&gpio_lock, flags); | |
567 | } | |
2967dab1 MD |
568 | |
569 | static int pinmux_direction(struct pinmux_info *gpioc, | |
570 | unsigned gpio, int new_pinmux_type) | |
571 | { | |
0fc64cc0 MD |
572 | int pinmux_type; |
573 | int ret = -EINVAL; | |
574 | ||
575 | if (!gpioc) | |
576 | goto err_out; | |
2967dab1 | 577 | |
2967dab1 MD |
578 | pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE; |
579 | ||
580 | switch (pinmux_type) { | |
581 | case PINMUX_TYPE_GPIO: | |
582 | break; | |
583 | case PINMUX_TYPE_OUTPUT: | |
584 | case PINMUX_TYPE_INPUT: | |
585 | case PINMUX_TYPE_INPUT_PULLUP: | |
586 | case PINMUX_TYPE_INPUT_PULLDOWN: | |
587 | pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE); | |
588 | break; | |
589 | default: | |
590 | goto err_out; | |
591 | } | |
592 | ||
593 | if (pinmux_config_gpio(gpioc, gpio, | |
594 | new_pinmux_type, | |
595 | GPIO_CFG_DRYRUN) != 0) | |
596 | goto err_out; | |
597 | ||
598 | if (pinmux_config_gpio(gpioc, gpio, | |
599 | new_pinmux_type, | |
600 | GPIO_CFG_REQ) != 0) | |
601 | BUG(); | |
602 | ||
18801be7 MD |
603 | gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE; |
604 | gpioc->gpios[gpio].flags |= new_pinmux_type; | |
2967dab1 MD |
605 | |
606 | ret = 0; | |
607 | err_out: | |
608 | return ret; | |
609 | } | |
610 | ||
69edbba0 | 611 | static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
2967dab1 | 612 | { |
69edbba0 | 613 | struct pinmux_info *gpioc = chip_to_pinmux(chip); |
2967dab1 | 614 | unsigned long flags; |
0fc64cc0 | 615 | int ret; |
2967dab1 MD |
616 | |
617 | spin_lock_irqsave(&gpio_lock, flags); | |
69edbba0 | 618 | ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT); |
2967dab1 | 619 | spin_unlock_irqrestore(&gpio_lock, flags); |
0fc64cc0 | 620 | |
2967dab1 MD |
621 | return ret; |
622 | } | |
2967dab1 | 623 | |
69edbba0 | 624 | static void sh_gpio_set_value(struct pinmux_info *gpioc, |
0fc64cc0 | 625 | unsigned gpio, int value) |
2967dab1 MD |
626 | { |
627 | struct pinmux_data_reg *dr = NULL; | |
628 | int bit = 0; | |
629 | ||
0fc64cc0 | 630 | if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) |
2967dab1 MD |
631 | BUG(); |
632 | else | |
3292094e | 633 | gpio_write_bit(dr, bit, value); |
2967dab1 MD |
634 | } |
635 | ||
69edbba0 MD |
636 | static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
637 | int value) | |
2967dab1 | 638 | { |
69edbba0 | 639 | struct pinmux_info *gpioc = chip_to_pinmux(chip); |
2967dab1 | 640 | unsigned long flags; |
0fc64cc0 | 641 | int ret; |
2967dab1 | 642 | |
69edbba0 | 643 | sh_gpio_set_value(gpioc, offset, value); |
3292094e | 644 | spin_lock_irqsave(&gpio_lock, flags); |
69edbba0 | 645 | ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT); |
2967dab1 | 646 | spin_unlock_irqrestore(&gpio_lock, flags); |
0fc64cc0 | 647 | |
2967dab1 MD |
648 | return ret; |
649 | } | |
2967dab1 | 650 | |
69edbba0 | 651 | static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio) |
2967dab1 | 652 | { |
0fc64cc0 MD |
653 | struct pinmux_data_reg *dr = NULL; |
654 | int bit = 0; | |
2967dab1 | 655 | |
e8184a47 PM |
656 | if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) |
657 | return -EINVAL; | |
2967dab1 | 658 | |
92554d97 | 659 | return gpio_read_bit(dr, bit); |
0fc64cc0 MD |
660 | } |
661 | ||
69edbba0 | 662 | static int sh_gpio_get(struct gpio_chip *chip, unsigned offset) |
0fc64cc0 | 663 | { |
69edbba0 | 664 | return sh_gpio_get_value(chip_to_pinmux(chip), offset); |
2967dab1 | 665 | } |
2967dab1 | 666 | |
69edbba0 | 667 | static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
2967dab1 | 668 | { |
69edbba0 | 669 | sh_gpio_set_value(chip_to_pinmux(chip), offset, value); |
2967dab1 | 670 | } |
2967dab1 | 671 | |
ad2a8e7e MD |
672 | static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
673 | { | |
674 | struct pinmux_info *gpioc = chip_to_pinmux(chip); | |
675 | pinmux_enum_t enum_id; | |
676 | pinmux_enum_t *enum_ids; | |
677 | int i, k, pos; | |
678 | ||
679 | pos = 0; | |
680 | enum_id = 0; | |
681 | while (1) { | |
682 | pos = get_gpio_enum_id(gpioc, offset, pos, &enum_id); | |
683 | if (pos <= 0 || !enum_id) | |
684 | break; | |
685 | ||
686 | for (i = 0; i < gpioc->gpio_irq_size; i++) { | |
687 | enum_ids = gpioc->gpio_irq[i].enum_ids; | |
688 | for (k = 0; enum_ids[k]; k++) { | |
689 | if (enum_ids[k] == enum_id) | |
690 | return gpioc->gpio_irq[i].irq; | |
691 | } | |
692 | } | |
693 | } | |
694 | ||
695 | return -ENOSYS; | |
696 | } | |
697 | ||
2967dab1 MD |
698 | int register_pinmux(struct pinmux_info *pip) |
699 | { | |
69edbba0 | 700 | struct gpio_chip *chip = &pip->chip; |
b0e10211 | 701 | int ret; |
69edbba0 | 702 | |
b72421d8 | 703 | pr_info("%s handling gpio %d -> %d\n", |
2967dab1 MD |
704 | pip->name, pip->first_gpio, pip->last_gpio); |
705 | ||
b0e10211 MD |
706 | ret = pfc_ioremap(pip); |
707 | if (ret < 0) | |
708 | return ret; | |
709 | ||
69edbba0 MD |
710 | setup_data_regs(pip); |
711 | ||
712 | chip->request = sh_gpio_request; | |
713 | chip->free = sh_gpio_free; | |
714 | chip->direction_input = sh_gpio_direction_input; | |
715 | chip->get = sh_gpio_get; | |
716 | chip->direction_output = sh_gpio_direction_output; | |
717 | chip->set = sh_gpio_set; | |
ad2a8e7e | 718 | chip->to_irq = sh_gpio_to_irq; |
69edbba0 MD |
719 | |
720 | WARN_ON(pip->first_gpio != 0); /* needs testing */ | |
721 | ||
722 | chip->label = pip->name; | |
723 | chip->owner = THIS_MODULE; | |
724 | chip->base = pip->first_gpio; | |
725 | chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1; | |
726 | ||
b0e10211 MD |
727 | ret = gpiochip_add(chip); |
728 | if (ret < 0) | |
729 | pfc_iounmap(pip); | |
730 | ||
731 | return ret; | |
2967dab1 | 732 | } |
b72421d8 PM |
733 | |
734 | int unregister_pinmux(struct pinmux_info *pip) | |
735 | { | |
736 | pr_info("%s deregistering\n", pip->name); | |
b0e10211 | 737 | pfc_iounmap(pip); |
b72421d8 PM |
738 | return gpiochip_remove(&pip->chip); |
739 | } |