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7c696693 CW |
1 | /* |
2 | * Rockchip Generic power domain support. | |
3 | * | |
4 | * Copyright (c) 2015 ROCKCHIP, Co. Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/io.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/pm_clock.h> | |
14 | #include <linux/pm_domain.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_platform.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/regmap.h> | |
19 | #include <linux/mfd/syscon.h> | |
20 | #include <dt-bindings/power/rk3288-power.h> | |
8c20b67f | 21 | #include <dt-bindings/power/rk3368-power.h> |
7c696693 CW |
22 | |
23 | struct rockchip_domain_info { | |
24 | int pwr_mask; | |
25 | int status_mask; | |
26 | int req_mask; | |
27 | int idle_mask; | |
28 | int ack_mask; | |
29 | }; | |
30 | ||
31 | struct rockchip_pmu_info { | |
32 | u32 pwr_offset; | |
33 | u32 status_offset; | |
34 | u32 req_offset; | |
35 | u32 idle_offset; | |
36 | u32 ack_offset; | |
37 | ||
38 | u32 core_pwrcnt_offset; | |
39 | u32 gpu_pwrcnt_offset; | |
40 | ||
41 | unsigned int core_power_transition_time; | |
42 | unsigned int gpu_power_transition_time; | |
43 | ||
44 | int num_domains; | |
45 | const struct rockchip_domain_info *domain_info; | |
46 | }; | |
47 | ||
48 | struct rockchip_pm_domain { | |
49 | struct generic_pm_domain genpd; | |
50 | const struct rockchip_domain_info *info; | |
51 | struct rockchip_pmu *pmu; | |
52 | int num_clks; | |
53 | struct clk *clks[]; | |
54 | }; | |
55 | ||
56 | struct rockchip_pmu { | |
57 | struct device *dev; | |
58 | struct regmap *regmap; | |
59 | const struct rockchip_pmu_info *info; | |
60 | struct mutex mutex; /* mutex lock for pmu */ | |
61 | struct genpd_onecell_data genpd_data; | |
62 | struct generic_pm_domain *domains[]; | |
63 | }; | |
64 | ||
65 | #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) | |
66 | ||
67 | #define DOMAIN(pwr, status, req, idle, ack) \ | |
68 | { \ | |
69 | .pwr_mask = BIT(pwr), \ | |
70 | .status_mask = BIT(status), \ | |
71 | .req_mask = BIT(req), \ | |
72 | .idle_mask = BIT(idle), \ | |
73 | .ack_mask = BIT(ack), \ | |
74 | } | |
75 | ||
76 | #define DOMAIN_RK3288(pwr, status, req) \ | |
77 | DOMAIN(pwr, status, req, req, (req) + 16) | |
78 | ||
8c20b67f | 79 | #define DOMAIN_RK3368(pwr, status, req) \ |
80 | DOMAIN(pwr, status, req, (req) + 16, req) | |
81 | ||
7c696693 CW |
82 | static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) |
83 | { | |
84 | struct rockchip_pmu *pmu = pd->pmu; | |
85 | const struct rockchip_domain_info *pd_info = pd->info; | |
86 | unsigned int val; | |
87 | ||
88 | regmap_read(pmu->regmap, pmu->info->idle_offset, &val); | |
89 | return (val & pd_info->idle_mask) == pd_info->idle_mask; | |
90 | } | |
91 | ||
92 | static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, | |
93 | bool idle) | |
94 | { | |
95 | const struct rockchip_domain_info *pd_info = pd->info; | |
96 | struct rockchip_pmu *pmu = pd->pmu; | |
97 | unsigned int val; | |
98 | ||
99 | regmap_update_bits(pmu->regmap, pmu->info->req_offset, | |
100 | pd_info->req_mask, idle ? -1U : 0); | |
101 | ||
102 | dsb(sy); | |
103 | ||
104 | do { | |
105 | regmap_read(pmu->regmap, pmu->info->ack_offset, &val); | |
106 | } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0)); | |
107 | ||
108 | while (rockchip_pmu_domain_is_idle(pd) != idle) | |
109 | cpu_relax(); | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
114 | static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) | |
115 | { | |
116 | struct rockchip_pmu *pmu = pd->pmu; | |
117 | unsigned int val; | |
118 | ||
119 | regmap_read(pmu->regmap, pmu->info->status_offset, &val); | |
120 | ||
121 | /* 1'b0: power on, 1'b1: power off */ | |
122 | return !(val & pd->info->status_mask); | |
123 | } | |
124 | ||
125 | static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, | |
126 | bool on) | |
127 | { | |
128 | struct rockchip_pmu *pmu = pd->pmu; | |
129 | ||
130 | regmap_update_bits(pmu->regmap, pmu->info->pwr_offset, | |
131 | pd->info->pwr_mask, on ? 0 : -1U); | |
132 | ||
133 | dsb(sy); | |
134 | ||
135 | while (rockchip_pmu_domain_is_on(pd) != on) | |
136 | cpu_relax(); | |
137 | } | |
138 | ||
139 | static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) | |
140 | { | |
141 | int i; | |
142 | ||
143 | mutex_lock(&pd->pmu->mutex); | |
144 | ||
145 | if (rockchip_pmu_domain_is_on(pd) != power_on) { | |
146 | for (i = 0; i < pd->num_clks; i++) | |
147 | clk_enable(pd->clks[i]); | |
148 | ||
149 | if (!power_on) { | |
150 | /* FIXME: add code to save AXI_QOS */ | |
151 | ||
152 | /* if powering down, idle request to NIU first */ | |
153 | rockchip_pmu_set_idle_request(pd, true); | |
154 | } | |
155 | ||
156 | rockchip_do_pmu_set_power_domain(pd, power_on); | |
157 | ||
158 | if (power_on) { | |
159 | /* if powering up, leave idle mode */ | |
160 | rockchip_pmu_set_idle_request(pd, false); | |
161 | ||
162 | /* FIXME: add code to restore AXI_QOS */ | |
163 | } | |
164 | ||
165 | for (i = pd->num_clks - 1; i >= 0; i--) | |
166 | clk_disable(pd->clks[i]); | |
167 | } | |
168 | ||
169 | mutex_unlock(&pd->pmu->mutex); | |
170 | return 0; | |
171 | } | |
172 | ||
173 | static int rockchip_pd_power_on(struct generic_pm_domain *domain) | |
174 | { | |
175 | struct rockchip_pm_domain *pd = to_rockchip_pd(domain); | |
176 | ||
177 | return rockchip_pd_power(pd, true); | |
178 | } | |
179 | ||
180 | static int rockchip_pd_power_off(struct generic_pm_domain *domain) | |
181 | { | |
182 | struct rockchip_pm_domain *pd = to_rockchip_pd(domain); | |
183 | ||
184 | return rockchip_pd_power(pd, false); | |
185 | } | |
186 | ||
187 | static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd, | |
188 | struct device *dev) | |
189 | { | |
190 | struct clk *clk; | |
191 | int i; | |
192 | int error; | |
193 | ||
194 | dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); | |
195 | ||
196 | error = pm_clk_create(dev); | |
197 | if (error) { | |
198 | dev_err(dev, "pm_clk_create failed %d\n", error); | |
199 | return error; | |
200 | } | |
201 | ||
202 | i = 0; | |
203 | while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { | |
204 | dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk); | |
205 | error = pm_clk_add_clk(dev, clk); | |
206 | if (error) { | |
207 | dev_err(dev, "pm_clk_add_clk failed %d\n", error); | |
208 | clk_put(clk); | |
209 | pm_clk_destroy(dev); | |
210 | return error; | |
211 | } | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd, | |
218 | struct device *dev) | |
219 | { | |
220 | dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); | |
221 | ||
222 | pm_clk_destroy(dev); | |
223 | } | |
224 | ||
225 | static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, | |
226 | struct device_node *node) | |
227 | { | |
228 | const struct rockchip_domain_info *pd_info; | |
229 | struct rockchip_pm_domain *pd; | |
230 | struct clk *clk; | |
231 | int clk_cnt; | |
232 | int i; | |
233 | u32 id; | |
234 | int error; | |
235 | ||
236 | error = of_property_read_u32(node, "reg", &id); | |
237 | if (error) { | |
238 | dev_err(pmu->dev, | |
239 | "%s: failed to retrieve domain id (reg): %d\n", | |
240 | node->name, error); | |
241 | return -EINVAL; | |
242 | } | |
243 | ||
244 | if (id >= pmu->info->num_domains) { | |
245 | dev_err(pmu->dev, "%s: invalid domain id %d\n", | |
246 | node->name, id); | |
247 | return -EINVAL; | |
248 | } | |
249 | ||
250 | pd_info = &pmu->info->domain_info[id]; | |
251 | if (!pd_info) { | |
252 | dev_err(pmu->dev, "%s: undefined domain id %d\n", | |
253 | node->name, id); | |
254 | return -EINVAL; | |
255 | } | |
256 | ||
257 | clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells"); | |
258 | pd = devm_kzalloc(pmu->dev, | |
259 | sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]), | |
260 | GFP_KERNEL); | |
261 | if (!pd) | |
262 | return -ENOMEM; | |
263 | ||
264 | pd->info = pd_info; | |
265 | pd->pmu = pmu; | |
266 | ||
267 | for (i = 0; i < clk_cnt; i++) { | |
268 | clk = of_clk_get(node, i); | |
269 | if (IS_ERR(clk)) { | |
270 | error = PTR_ERR(clk); | |
271 | dev_err(pmu->dev, | |
c3ce5b37 HS |
272 | "%s: failed to get clk at index %d: %d\n", |
273 | node->name, i, error); | |
7c696693 CW |
274 | goto err_out; |
275 | } | |
276 | ||
277 | error = clk_prepare(clk); | |
278 | if (error) { | |
279 | dev_err(pmu->dev, | |
280 | "%s: failed to prepare clk %pC (index %d): %d\n", | |
281 | node->name, clk, i, error); | |
282 | clk_put(clk); | |
283 | goto err_out; | |
284 | } | |
285 | ||
286 | pd->clks[pd->num_clks++] = clk; | |
287 | ||
288 | dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n", | |
289 | clk, node->name); | |
290 | } | |
291 | ||
292 | error = rockchip_pd_power(pd, true); | |
293 | if (error) { | |
294 | dev_err(pmu->dev, | |
295 | "failed to power on domain '%s': %d\n", | |
296 | node->name, error); | |
297 | goto err_out; | |
298 | } | |
299 | ||
300 | pd->genpd.name = node->name; | |
301 | pd->genpd.power_off = rockchip_pd_power_off; | |
302 | pd->genpd.power_on = rockchip_pd_power_on; | |
303 | pd->genpd.attach_dev = rockchip_pd_attach_dev; | |
304 | pd->genpd.detach_dev = rockchip_pd_detach_dev; | |
305 | pd->genpd.flags = GENPD_FLAG_PM_CLK; | |
306 | pm_genpd_init(&pd->genpd, NULL, false); | |
307 | ||
308 | pmu->genpd_data.domains[id] = &pd->genpd; | |
309 | return 0; | |
310 | ||
311 | err_out: | |
312 | while (--i >= 0) { | |
313 | clk_unprepare(pd->clks[i]); | |
314 | clk_put(pd->clks[i]); | |
315 | } | |
316 | return error; | |
317 | } | |
318 | ||
319 | static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd) | |
320 | { | |
321 | int i; | |
322 | ||
323 | for (i = 0; i < pd->num_clks; i++) { | |
324 | clk_unprepare(pd->clks[i]); | |
325 | clk_put(pd->clks[i]); | |
326 | } | |
327 | ||
328 | /* protect the zeroing of pm->num_clks */ | |
329 | mutex_lock(&pd->pmu->mutex); | |
330 | pd->num_clks = 0; | |
331 | mutex_unlock(&pd->pmu->mutex); | |
332 | ||
333 | /* devm will free our memory */ | |
334 | } | |
335 | ||
336 | static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu) | |
337 | { | |
338 | struct generic_pm_domain *genpd; | |
339 | struct rockchip_pm_domain *pd; | |
340 | int i; | |
341 | ||
342 | for (i = 0; i < pmu->genpd_data.num_domains; i++) { | |
343 | genpd = pmu->genpd_data.domains[i]; | |
344 | if (genpd) { | |
345 | pd = to_rockchip_pd(genpd); | |
346 | rockchip_pm_remove_one_domain(pd); | |
347 | } | |
348 | } | |
349 | ||
350 | /* devm will free our memory */ | |
351 | } | |
352 | ||
353 | static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu, | |
354 | u32 domain_reg_offset, | |
355 | unsigned int count) | |
356 | { | |
357 | /* First configure domain power down transition count ... */ | |
358 | regmap_write(pmu->regmap, domain_reg_offset, count); | |
359 | /* ... and then power up count. */ | |
360 | regmap_write(pmu->regmap, domain_reg_offset + 4, count); | |
361 | } | |
362 | ||
363 | static int rockchip_pm_domain_probe(struct platform_device *pdev) | |
364 | { | |
365 | struct device *dev = &pdev->dev; | |
366 | struct device_node *np = dev->of_node; | |
367 | struct device_node *node; | |
368 | struct device *parent; | |
369 | struct rockchip_pmu *pmu; | |
370 | const struct of_device_id *match; | |
371 | const struct rockchip_pmu_info *pmu_info; | |
372 | int error; | |
373 | ||
374 | if (!np) { | |
375 | dev_err(dev, "device tree node not found\n"); | |
376 | return -ENODEV; | |
377 | } | |
378 | ||
379 | match = of_match_device(dev->driver->of_match_table, dev); | |
380 | if (!match || !match->data) { | |
381 | dev_err(dev, "missing pmu data\n"); | |
382 | return -EINVAL; | |
383 | } | |
384 | ||
385 | pmu_info = match->data; | |
386 | ||
387 | pmu = devm_kzalloc(dev, | |
388 | sizeof(*pmu) + | |
389 | pmu_info->num_domains * sizeof(pmu->domains[0]), | |
390 | GFP_KERNEL); | |
391 | if (!pmu) | |
392 | return -ENOMEM; | |
393 | ||
394 | pmu->dev = &pdev->dev; | |
395 | mutex_init(&pmu->mutex); | |
396 | ||
397 | pmu->info = pmu_info; | |
398 | ||
399 | pmu->genpd_data.domains = pmu->domains; | |
400 | pmu->genpd_data.num_domains = pmu_info->num_domains; | |
401 | ||
402 | parent = dev->parent; | |
403 | if (!parent) { | |
404 | dev_err(dev, "no parent for syscon devices\n"); | |
405 | return -ENODEV; | |
406 | } | |
407 | ||
408 | pmu->regmap = syscon_node_to_regmap(parent->of_node); | |
409 | ||
410 | /* | |
411 | * Configure power up and down transition delays for CORE | |
412 | * and GPU domains. | |
413 | */ | |
414 | rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, | |
415 | pmu_info->core_power_transition_time); | |
416 | rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, | |
417 | pmu_info->gpu_power_transition_time); | |
418 | ||
419 | error = -ENODEV; | |
420 | ||
421 | for_each_available_child_of_node(np, node) { | |
422 | error = rockchip_pm_add_one_domain(pmu, node); | |
423 | if (error) { | |
424 | dev_err(dev, "failed to handle node %s: %d\n", | |
425 | node->name, error); | |
1d961f11 | 426 | of_node_put(node); |
7c696693 CW |
427 | goto err_out; |
428 | } | |
429 | } | |
430 | ||
431 | if (error) { | |
432 | dev_dbg(dev, "no power domains defined\n"); | |
433 | goto err_out; | |
434 | } | |
435 | ||
436 | of_genpd_add_provider_onecell(np, &pmu->genpd_data); | |
437 | ||
438 | return 0; | |
439 | ||
440 | err_out: | |
441 | rockchip_pm_domain_cleanup(pmu); | |
442 | return error; | |
443 | } | |
444 | ||
445 | static const struct rockchip_domain_info rk3288_pm_domains[] = { | |
446 | [RK3288_PD_VIO] = DOMAIN_RK3288(7, 7, 4), | |
447 | [RK3288_PD_HEVC] = DOMAIN_RK3288(14, 10, 9), | |
448 | [RK3288_PD_VIDEO] = DOMAIN_RK3288(8, 8, 3), | |
449 | [RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2), | |
450 | }; | |
451 | ||
8c20b67f | 452 | static const struct rockchip_domain_info rk3368_pm_domains[] = { |
453 | [RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6), | |
454 | [RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8), | |
455 | [RK3368_PD_VIDEO] = DOMAIN_RK3368(14, 13, 7), | |
456 | [RK3368_PD_GPU_0] = DOMAIN_RK3368(16, 15, 2), | |
457 | [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2), | |
458 | }; | |
459 | ||
7c696693 CW |
460 | static const struct rockchip_pmu_info rk3288_pmu = { |
461 | .pwr_offset = 0x08, | |
462 | .status_offset = 0x0c, | |
463 | .req_offset = 0x10, | |
464 | .idle_offset = 0x14, | |
465 | .ack_offset = 0x14, | |
466 | ||
467 | .core_pwrcnt_offset = 0x34, | |
468 | .gpu_pwrcnt_offset = 0x3c, | |
469 | ||
470 | .core_power_transition_time = 24, /* 1us */ | |
471 | .gpu_power_transition_time = 24, /* 1us */ | |
472 | ||
473 | .num_domains = ARRAY_SIZE(rk3288_pm_domains), | |
474 | .domain_info = rk3288_pm_domains, | |
475 | }; | |
476 | ||
8c20b67f | 477 | static const struct rockchip_pmu_info rk3368_pmu = { |
478 | .pwr_offset = 0x0c, | |
479 | .status_offset = 0x10, | |
480 | .req_offset = 0x3c, | |
481 | .idle_offset = 0x40, | |
482 | .ack_offset = 0x40, | |
483 | ||
484 | .core_pwrcnt_offset = 0x48, | |
485 | .gpu_pwrcnt_offset = 0x50, | |
486 | ||
487 | .core_power_transition_time = 24, | |
488 | .gpu_power_transition_time = 24, | |
489 | ||
490 | .num_domains = ARRAY_SIZE(rk3368_pm_domains), | |
491 | .domain_info = rk3368_pm_domains, | |
492 | }; | |
493 | ||
7c696693 CW |
494 | static const struct of_device_id rockchip_pm_domain_dt_match[] = { |
495 | { | |
496 | .compatible = "rockchip,rk3288-power-controller", | |
497 | .data = (void *)&rk3288_pmu, | |
498 | }, | |
8c20b67f | 499 | { |
500 | .compatible = "rockchip,rk3368-power-controller", | |
501 | .data = (void *)&rk3368_pmu, | |
502 | }, | |
7c696693 CW |
503 | { /* sentinel */ }, |
504 | }; | |
505 | ||
506 | static struct platform_driver rockchip_pm_domain_driver = { | |
507 | .probe = rockchip_pm_domain_probe, | |
508 | .driver = { | |
509 | .name = "rockchip-pm-domain", | |
510 | .of_match_table = rockchip_pm_domain_dt_match, | |
511 | /* | |
512 | * We can't forcibly eject devices form power domain, | |
513 | * so we can't really remove power domains once they | |
514 | * were added. | |
515 | */ | |
516 | .suppress_bind_attrs = true, | |
517 | }, | |
518 | }; | |
519 | ||
520 | static int __init rockchip_pm_domain_drv_register(void) | |
521 | { | |
522 | return platform_driver_register(&rockchip_pm_domain_driver); | |
523 | } | |
524 | postcore_initcall(rockchip_pm_domain_drv_register); |