Commit | Line | Data |
---|---|---|
7232398a TR |
1 | /* |
2 | * drivers/soc/tegra/pmc.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
7d71e903 TR |
20 | #define pr_fmt(fmt) "tegra-pmc: " fmt |
21 | ||
7232398a TR |
22 | #include <linux/kernel.h> |
23 | #include <linux/clk.h> | |
24 | #include <linux/clk/tegra.h> | |
25 | #include <linux/debugfs.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/export.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/io.h> | |
0a2d87e0 | 31 | #include <linux/iopoll.h> |
7232398a TR |
32 | #include <linux/of.h> |
33 | #include <linux/of_address.h> | |
a3804512 | 34 | #include <linux/of_platform.h> |
7232398a | 35 | #include <linux/platform_device.h> |
a3804512 | 36 | #include <linux/pm_domain.h> |
7232398a TR |
37 | #include <linux/reboot.h> |
38 | #include <linux/reset.h> | |
39 | #include <linux/seq_file.h> | |
a3804512 | 40 | #include <linux/slab.h> |
7232398a TR |
41 | #include <linux/spinlock.h> |
42 | ||
43 | #include <soc/tegra/common.h> | |
44 | #include <soc/tegra/fuse.h> | |
45 | #include <soc/tegra/pmc.h> | |
46 | ||
47 | #define PMC_CNTRL 0x0 | |
48 | #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ | |
49 | #define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */ | |
50 | #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ | |
51 | #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ | |
52 | #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ | |
53 | #define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */ | |
f5353c60 | 54 | #define PMC_CNTRL_MAIN_RST (1 << 4) |
7232398a TR |
55 | |
56 | #define DPD_SAMPLE 0x020 | |
57 | #define DPD_SAMPLE_ENABLE (1 << 0) | |
58 | #define DPD_SAMPLE_DISABLE (0 << 0) | |
59 | ||
60 | #define PWRGATE_TOGGLE 0x30 | |
61 | #define PWRGATE_TOGGLE_START (1 << 8) | |
62 | ||
63 | #define REMOVE_CLAMPING 0x34 | |
64 | ||
65 | #define PWRGATE_STATUS 0x38 | |
66 | ||
67 | #define PMC_SCRATCH0 0x50 | |
68 | #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) | |
69 | #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) | |
70 | #define PMC_SCRATCH0_MODE_RCM (1 << 1) | |
71 | #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ | |
72 | PMC_SCRATCH0_MODE_BOOTLOADER | \ | |
73 | PMC_SCRATCH0_MODE_RCM) | |
74 | ||
75 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | |
76 | #define PMC_CPUPWROFF_TIMER 0xcc | |
77 | ||
78 | #define PMC_SCRATCH41 0x140 | |
79 | ||
3568df3d MP |
80 | #define PMC_SENSOR_CTRL 0x1b0 |
81 | #define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2) | |
82 | #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1) | |
83 | ||
f5353c60 TR |
84 | #define PMC_RST_STATUS 0x1b4 |
85 | #define PMC_RST_STATUS_POR 0 | |
86 | #define PMC_RST_STATUS_WATCHDOG 1 | |
87 | #define PMC_RST_STATUS_SENSOR 2 | |
88 | #define PMC_RST_STATUS_SW_MAIN 3 | |
89 | #define PMC_RST_STATUS_LP0 4 | |
90 | #define PMC_RST_STATUS_AOTAG 5 | |
91 | ||
7232398a TR |
92 | #define IO_DPD_REQ 0x1b8 |
93 | #define IO_DPD_REQ_CODE_IDLE (0 << 30) | |
94 | #define IO_DPD_REQ_CODE_OFF (1 << 30) | |
95 | #define IO_DPD_REQ_CODE_ON (2 << 30) | |
96 | #define IO_DPD_REQ_CODE_MASK (3 << 30) | |
97 | ||
98 | #define IO_DPD_STATUS 0x1bc | |
99 | #define IO_DPD2_REQ 0x1c0 | |
100 | #define IO_DPD2_STATUS 0x1c4 | |
101 | #define SEL_DPD_TIM 0x1c8 | |
102 | ||
3568df3d MP |
103 | #define PMC_SCRATCH54 0x258 |
104 | #define PMC_SCRATCH54_DATA_SHIFT 8 | |
105 | #define PMC_SCRATCH54_ADDR_SHIFT 0 | |
106 | ||
107 | #define PMC_SCRATCH55 0x25c | |
108 | #define PMC_SCRATCH55_RESET_TEGRA (1 << 31) | |
109 | #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 | |
110 | #define PMC_SCRATCH55_PINMUX_SHIFT 24 | |
111 | #define PMC_SCRATCH55_16BITOP (1 << 15) | |
112 | #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 | |
113 | #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 | |
114 | ||
7232398a TR |
115 | #define GPU_RG_CNTRL 0x2d4 |
116 | ||
a3804512 JH |
117 | struct tegra_powergate { |
118 | struct generic_pm_domain genpd; | |
119 | struct tegra_pmc *pmc; | |
120 | unsigned int id; | |
121 | struct clk **clks; | |
122 | unsigned int num_clks; | |
123 | struct reset_control **resets; | |
124 | unsigned int num_resets; | |
125 | }; | |
126 | ||
7232398a TR |
127 | struct tegra_pmc_soc { |
128 | unsigned int num_powergates; | |
129 | const char *const *powergates; | |
130 | unsigned int num_cpu_powergates; | |
131 | const u8 *cpu_powergates; | |
a9a40a4a | 132 | |
3568df3d | 133 | bool has_tsense_reset; |
a9a40a4a | 134 | bool has_gpu_clamps; |
7232398a TR |
135 | }; |
136 | ||
137 | /** | |
138 | * struct tegra_pmc - NVIDIA Tegra PMC | |
35b67291 | 139 | * @dev: pointer to PMC device structure |
7232398a TR |
140 | * @base: pointer to I/O remapped register region |
141 | * @clk: pointer to pclk clock | |
35b67291 | 142 | * @soc: pointer to SoC data structure |
3195ac6d | 143 | * @debugfs: pointer to debugfs entry |
7232398a TR |
144 | * @rate: currently configured rate of pclk |
145 | * @suspend_mode: lowest suspend mode available | |
146 | * @cpu_good_time: CPU power good time (in microseconds) | |
147 | * @cpu_off_time: CPU power off time (in microsecends) | |
148 | * @core_osc_time: core power good OSC time (in microseconds) | |
149 | * @core_pmu_time: core power good PMU time (in microseconds) | |
150 | * @core_off_time: core power off time (in microseconds) | |
151 | * @corereq_high: core power request is active-high | |
152 | * @sysclkreq_high: system clock request is active-high | |
153 | * @combined_req: combined power request for CPU & core | |
154 | * @cpu_pwr_good_en: CPU power good signal is enabled | |
155 | * @lp0_vec_phys: physical base address of the LP0 warm boot code | |
156 | * @lp0_vec_size: size of the LP0 warm boot code | |
a3804512 | 157 | * @powergates_available: Bitmap of available power gates |
7232398a TR |
158 | * @powergates_lock: mutex for power gate register access |
159 | */ | |
160 | struct tegra_pmc { | |
3568df3d | 161 | struct device *dev; |
7232398a TR |
162 | void __iomem *base; |
163 | struct clk *clk; | |
3195ac6d | 164 | struct dentry *debugfs; |
7232398a TR |
165 | |
166 | const struct tegra_pmc_soc *soc; | |
167 | ||
168 | unsigned long rate; | |
169 | ||
170 | enum tegra_suspend_mode suspend_mode; | |
171 | u32 cpu_good_time; | |
172 | u32 cpu_off_time; | |
173 | u32 core_osc_time; | |
174 | u32 core_pmu_time; | |
175 | u32 core_off_time; | |
176 | bool corereq_high; | |
177 | bool sysclkreq_high; | |
178 | bool combined_req; | |
179 | bool cpu_pwr_good_en; | |
180 | u32 lp0_vec_phys; | |
181 | u32 lp0_vec_size; | |
a3804512 | 182 | DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); |
7232398a TR |
183 | |
184 | struct mutex powergates_lock; | |
185 | }; | |
186 | ||
187 | static struct tegra_pmc *pmc = &(struct tegra_pmc) { | |
188 | .base = NULL, | |
189 | .suspend_mode = TEGRA_SUSPEND_NONE, | |
190 | }; | |
191 | ||
a3804512 JH |
192 | static inline struct tegra_powergate * |
193 | to_powergate(struct generic_pm_domain *domain) | |
194 | { | |
195 | return container_of(domain, struct tegra_powergate, genpd); | |
196 | } | |
197 | ||
7232398a TR |
198 | static u32 tegra_pmc_readl(unsigned long offset) |
199 | { | |
200 | return readl(pmc->base + offset); | |
201 | } | |
202 | ||
203 | static void tegra_pmc_writel(u32 value, unsigned long offset) | |
204 | { | |
205 | writel(value, pmc->base + offset); | |
206 | } | |
207 | ||
0ecf2d33 JH |
208 | static inline bool tegra_powergate_state(int id) |
209 | { | |
bc9af23d JH |
210 | if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) |
211 | return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; | |
212 | else | |
213 | return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; | |
0ecf2d33 JH |
214 | } |
215 | ||
0a243bd4 JH |
216 | static inline bool tegra_powergate_is_valid(int id) |
217 | { | |
218 | return (pmc->soc && pmc->soc->powergates[id]); | |
219 | } | |
220 | ||
a3804512 JH |
221 | static inline bool tegra_powergate_is_available(int id) |
222 | { | |
223 | return test_bit(id, pmc->powergates_available); | |
224 | } | |
225 | ||
226 | static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) | |
227 | { | |
228 | unsigned int i; | |
229 | ||
230 | if (!pmc || !pmc->soc || !name) | |
231 | return -EINVAL; | |
232 | ||
233 | for (i = 0; i < pmc->soc->num_powergates; i++) { | |
234 | if (!tegra_powergate_is_valid(i)) | |
235 | continue; | |
236 | ||
237 | if (!strcmp(name, pmc->soc->powergates[i])) | |
238 | return i; | |
239 | } | |
240 | ||
241 | dev_err(pmc->dev, "powergate %s not found\n", name); | |
242 | ||
243 | return -ENODEV; | |
244 | } | |
245 | ||
7232398a TR |
246 | /** |
247 | * tegra_powergate_set() - set the state of a partition | |
248 | * @id: partition ID | |
249 | * @new_state: new state of the partition | |
250 | */ | |
70293ed0 | 251 | static int tegra_powergate_set(unsigned int id, bool new_state) |
7232398a | 252 | { |
0a2d87e0 JH |
253 | bool status; |
254 | int err; | |
255 | ||
bc9af23d JH |
256 | if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) |
257 | return -EINVAL; | |
258 | ||
7232398a TR |
259 | mutex_lock(&pmc->powergates_lock); |
260 | ||
0ecf2d33 | 261 | if (tegra_powergate_state(id) == new_state) { |
7232398a TR |
262 | mutex_unlock(&pmc->powergates_lock); |
263 | return 0; | |
264 | } | |
265 | ||
266 | tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); | |
267 | ||
0a2d87e0 JH |
268 | err = readx_poll_timeout(tegra_powergate_state, id, status, |
269 | status == new_state, 10, 100000); | |
270 | ||
7232398a TR |
271 | mutex_unlock(&pmc->powergates_lock); |
272 | ||
0a2d87e0 | 273 | return err; |
7232398a TR |
274 | } |
275 | ||
a3804512 JH |
276 | static int __tegra_powergate_remove_clamping(unsigned int id) |
277 | { | |
278 | u32 mask; | |
279 | ||
280 | mutex_lock(&pmc->powergates_lock); | |
281 | ||
282 | /* | |
283 | * On Tegra124 and later, the clamps for the GPU are controlled by a | |
284 | * separate register (with different semantics). | |
285 | */ | |
286 | if (id == TEGRA_POWERGATE_3D) { | |
287 | if (pmc->soc->has_gpu_clamps) { | |
288 | tegra_pmc_writel(0, GPU_RG_CNTRL); | |
289 | goto out; | |
290 | } | |
291 | } | |
292 | ||
293 | /* | |
294 | * Tegra 2 has a bug where PCIE and VDE clamping masks are | |
295 | * swapped relatively to the partition ids | |
296 | */ | |
297 | if (id == TEGRA_POWERGATE_VDEC) | |
298 | mask = (1 << TEGRA_POWERGATE_PCIE); | |
299 | else if (id == TEGRA_POWERGATE_PCIE) | |
300 | mask = (1 << TEGRA_POWERGATE_VDEC); | |
301 | else | |
302 | mask = (1 << id); | |
303 | ||
304 | tegra_pmc_writel(mask, REMOVE_CLAMPING); | |
305 | ||
306 | out: | |
307 | mutex_unlock(&pmc->powergates_lock); | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) | |
313 | { | |
314 | unsigned int i; | |
315 | ||
316 | for (i = 0; i < pg->num_clks; i++) | |
317 | clk_disable_unprepare(pg->clks[i]); | |
318 | } | |
319 | ||
320 | static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) | |
321 | { | |
322 | unsigned int i; | |
323 | int err; | |
324 | ||
325 | for (i = 0; i < pg->num_clks; i++) { | |
326 | err = clk_prepare_enable(pg->clks[i]); | |
327 | if (err) | |
328 | goto out; | |
329 | } | |
330 | ||
331 | return 0; | |
332 | ||
333 | out: | |
334 | while (i--) | |
335 | clk_disable_unprepare(pg->clks[i]); | |
336 | ||
337 | return err; | |
338 | } | |
339 | ||
340 | static int tegra_powergate_reset_assert(struct tegra_powergate *pg) | |
341 | { | |
342 | unsigned int i; | |
343 | int err; | |
344 | ||
345 | for (i = 0; i < pg->num_resets; i++) { | |
346 | err = reset_control_assert(pg->resets[i]); | |
347 | if (err) | |
348 | return err; | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | static int tegra_powergate_reset_deassert(struct tegra_powergate *pg) | |
355 | { | |
356 | unsigned int i; | |
357 | int err; | |
358 | ||
359 | for (i = 0; i < pg->num_resets; i++) { | |
360 | err = reset_control_deassert(pg->resets[i]); | |
361 | if (err) | |
362 | return err; | |
363 | } | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static int tegra_powergate_power_up(struct tegra_powergate *pg, | |
369 | bool disable_clocks) | |
370 | { | |
371 | int err; | |
372 | ||
373 | err = tegra_powergate_reset_assert(pg); | |
374 | if (err) | |
375 | return err; | |
376 | ||
377 | usleep_range(10, 20); | |
378 | ||
379 | err = tegra_powergate_set(pg->id, true); | |
380 | if (err < 0) | |
381 | return err; | |
382 | ||
383 | usleep_range(10, 20); | |
384 | ||
385 | err = tegra_powergate_enable_clocks(pg); | |
386 | if (err) | |
387 | goto disable_clks; | |
388 | ||
389 | usleep_range(10, 20); | |
390 | ||
391 | err = __tegra_powergate_remove_clamping(pg->id); | |
392 | if (err) | |
393 | goto disable_clks; | |
394 | ||
395 | usleep_range(10, 20); | |
396 | ||
397 | err = tegra_powergate_reset_deassert(pg); | |
398 | if (err) | |
399 | goto powergate_off; | |
400 | ||
401 | usleep_range(10, 20); | |
402 | ||
403 | if (disable_clocks) | |
404 | tegra_powergate_disable_clocks(pg); | |
405 | ||
406 | return 0; | |
407 | ||
408 | disable_clks: | |
409 | tegra_powergate_disable_clocks(pg); | |
410 | usleep_range(10, 20); | |
411 | powergate_off: | |
412 | tegra_powergate_set(pg->id, false); | |
413 | ||
414 | return err; | |
415 | } | |
416 | ||
417 | static int tegra_powergate_power_down(struct tegra_powergate *pg) | |
418 | { | |
419 | int err; | |
420 | ||
421 | err = tegra_powergate_enable_clocks(pg); | |
422 | if (err) | |
423 | return err; | |
424 | ||
425 | usleep_range(10, 20); | |
426 | ||
427 | err = tegra_powergate_reset_assert(pg); | |
428 | if (err) | |
429 | goto disable_clks; | |
430 | ||
431 | usleep_range(10, 20); | |
432 | ||
433 | tegra_powergate_disable_clocks(pg); | |
434 | ||
435 | usleep_range(10, 20); | |
436 | ||
437 | err = tegra_powergate_set(pg->id, false); | |
438 | if (err) | |
439 | goto assert_resets; | |
440 | ||
441 | return 0; | |
442 | ||
443 | assert_resets: | |
444 | tegra_powergate_enable_clocks(pg); | |
445 | usleep_range(10, 20); | |
446 | tegra_powergate_reset_deassert(pg); | |
447 | usleep_range(10, 20); | |
448 | disable_clks: | |
449 | tegra_powergate_disable_clocks(pg); | |
450 | ||
451 | return err; | |
452 | } | |
453 | ||
454 | static int tegra_genpd_power_on(struct generic_pm_domain *domain) | |
455 | { | |
456 | struct tegra_powergate *pg = to_powergate(domain); | |
457 | struct tegra_pmc *pmc = pg->pmc; | |
458 | int err; | |
459 | ||
460 | err = tegra_powergate_power_up(pg, true); | |
461 | if (err) | |
462 | dev_err(pmc->dev, "failed to turn on PM domain %s: %d\n", | |
463 | pg->genpd.name, err); | |
464 | ||
465 | return err; | |
466 | } | |
467 | ||
468 | static int tegra_genpd_power_off(struct generic_pm_domain *domain) | |
469 | { | |
470 | struct tegra_powergate *pg = to_powergate(domain); | |
471 | struct tegra_pmc *pmc = pg->pmc; | |
472 | int err; | |
473 | ||
474 | err = tegra_powergate_power_down(pg); | |
475 | if (err) | |
476 | dev_err(pmc->dev, "failed to turn off PM domain %s: %d\n", | |
477 | pg->genpd.name, err); | |
478 | ||
479 | return err; | |
480 | } | |
481 | ||
7232398a TR |
482 | /** |
483 | * tegra_powergate_power_on() - power on partition | |
484 | * @id: partition ID | |
485 | */ | |
70293ed0 | 486 | int tegra_powergate_power_on(unsigned int id) |
7232398a | 487 | { |
a3804512 | 488 | if (!tegra_powergate_is_available(id)) |
7232398a TR |
489 | return -EINVAL; |
490 | ||
491 | return tegra_powergate_set(id, true); | |
492 | } | |
493 | ||
494 | /** | |
495 | * tegra_powergate_power_off() - power off partition | |
496 | * @id: partition ID | |
497 | */ | |
70293ed0 | 498 | int tegra_powergate_power_off(unsigned int id) |
7232398a | 499 | { |
a3804512 | 500 | if (!tegra_powergate_is_available(id)) |
7232398a TR |
501 | return -EINVAL; |
502 | ||
503 | return tegra_powergate_set(id, false); | |
504 | } | |
505 | EXPORT_SYMBOL(tegra_powergate_power_off); | |
506 | ||
507 | /** | |
508 | * tegra_powergate_is_powered() - check if partition is powered | |
509 | * @id: partition ID | |
510 | */ | |
70293ed0 | 511 | int tegra_powergate_is_powered(unsigned int id) |
7232398a | 512 | { |
0ecf2d33 | 513 | int status; |
7232398a | 514 | |
0a243bd4 | 515 | if (!tegra_powergate_is_valid(id)) |
7232398a TR |
516 | return -EINVAL; |
517 | ||
e8cf6616 | 518 | mutex_lock(&pmc->powergates_lock); |
0ecf2d33 | 519 | status = tegra_powergate_state(id); |
e8cf6616 JH |
520 | mutex_unlock(&pmc->powergates_lock); |
521 | ||
0ecf2d33 | 522 | return status; |
7232398a TR |
523 | } |
524 | ||
525 | /** | |
526 | * tegra_powergate_remove_clamping() - remove power clamps for partition | |
527 | * @id: partition ID | |
528 | */ | |
70293ed0 | 529 | int tegra_powergate_remove_clamping(unsigned int id) |
7232398a | 530 | { |
a3804512 | 531 | if (!tegra_powergate_is_available(id)) |
7232398a TR |
532 | return -EINVAL; |
533 | ||
a3804512 | 534 | return __tegra_powergate_remove_clamping(id); |
7232398a TR |
535 | } |
536 | EXPORT_SYMBOL(tegra_powergate_remove_clamping); | |
537 | ||
538 | /** | |
539 | * tegra_powergate_sequence_power_up() - power up partition | |
540 | * @id: partition ID | |
541 | * @clk: clock for partition | |
542 | * @rst: reset for partition | |
543 | * | |
544 | * Must be called with clk disabled, and returns with clk enabled. | |
545 | */ | |
70293ed0 | 546 | int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, |
7232398a TR |
547 | struct reset_control *rst) |
548 | { | |
a3804512 JH |
549 | struct tegra_powergate pg; |
550 | int err; | |
7232398a | 551 | |
403db2d2 JH |
552 | if (!tegra_powergate_is_available(id)) |
553 | return -EINVAL; | |
554 | ||
a3804512 JH |
555 | pg.id = id; |
556 | pg.clks = &clk; | |
557 | pg.num_clks = 1; | |
558 | pg.resets = &rst; | |
559 | pg.num_resets = 1; | |
7232398a | 560 | |
a3804512 JH |
561 | err = tegra_powergate_power_up(&pg, false); |
562 | if (err) | |
563 | pr_err("failed to turn on partition %d: %d\n", id, err); | |
7232398a | 564 | |
a3804512 | 565 | return err; |
7232398a TR |
566 | } |
567 | EXPORT_SYMBOL(tegra_powergate_sequence_power_up); | |
568 | ||
569 | #ifdef CONFIG_SMP | |
570 | /** | |
571 | * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID | |
572 | * @cpuid: CPU partition ID | |
573 | * | |
574 | * Returns the partition ID corresponding to the CPU partition ID or a | |
575 | * negative error code on failure. | |
576 | */ | |
70293ed0 | 577 | static int tegra_get_cpu_powergate_id(unsigned int cpuid) |
7232398a | 578 | { |
70293ed0 | 579 | if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) |
7232398a TR |
580 | return pmc->soc->cpu_powergates[cpuid]; |
581 | ||
582 | return -EINVAL; | |
583 | } | |
584 | ||
585 | /** | |
586 | * tegra_pmc_cpu_is_powered() - check if CPU partition is powered | |
587 | * @cpuid: CPU partition ID | |
588 | */ | |
70293ed0 | 589 | bool tegra_pmc_cpu_is_powered(unsigned int cpuid) |
7232398a TR |
590 | { |
591 | int id; | |
592 | ||
593 | id = tegra_get_cpu_powergate_id(cpuid); | |
594 | if (id < 0) | |
595 | return false; | |
596 | ||
597 | return tegra_powergate_is_powered(id); | |
598 | } | |
599 | ||
600 | /** | |
601 | * tegra_pmc_cpu_power_on() - power on CPU partition | |
602 | * @cpuid: CPU partition ID | |
603 | */ | |
70293ed0 | 604 | int tegra_pmc_cpu_power_on(unsigned int cpuid) |
7232398a TR |
605 | { |
606 | int id; | |
607 | ||
608 | id = tegra_get_cpu_powergate_id(cpuid); | |
609 | if (id < 0) | |
610 | return id; | |
611 | ||
612 | return tegra_powergate_set(id, true); | |
613 | } | |
614 | ||
615 | /** | |
616 | * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition | |
617 | * @cpuid: CPU partition ID | |
618 | */ | |
70293ed0 | 619 | int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) |
7232398a TR |
620 | { |
621 | int id; | |
622 | ||
623 | id = tegra_get_cpu_powergate_id(cpuid); | |
624 | if (id < 0) | |
625 | return id; | |
626 | ||
627 | return tegra_powergate_remove_clamping(id); | |
628 | } | |
629 | #endif /* CONFIG_SMP */ | |
630 | ||
7892158a DR |
631 | static int tegra_pmc_restart_notify(struct notifier_block *this, |
632 | unsigned long action, void *data) | |
7232398a | 633 | { |
7892158a | 634 | const char *cmd = data; |
7232398a TR |
635 | u32 value; |
636 | ||
637 | value = tegra_pmc_readl(PMC_SCRATCH0); | |
638 | value &= ~PMC_SCRATCH0_MODE_MASK; | |
639 | ||
640 | if (cmd) { | |
641 | if (strcmp(cmd, "recovery") == 0) | |
642 | value |= PMC_SCRATCH0_MODE_RECOVERY; | |
643 | ||
644 | if (strcmp(cmd, "bootloader") == 0) | |
645 | value |= PMC_SCRATCH0_MODE_BOOTLOADER; | |
646 | ||
647 | if (strcmp(cmd, "forced-recovery") == 0) | |
648 | value |= PMC_SCRATCH0_MODE_RCM; | |
649 | } | |
650 | ||
651 | tegra_pmc_writel(value, PMC_SCRATCH0); | |
652 | ||
f5353c60 TR |
653 | /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ |
654 | value = tegra_pmc_readl(PMC_CNTRL); | |
655 | value |= PMC_CNTRL_MAIN_RST; | |
656 | tegra_pmc_writel(value, PMC_CNTRL); | |
7892158a DR |
657 | |
658 | return NOTIFY_DONE; | |
7232398a TR |
659 | } |
660 | ||
7892158a DR |
661 | static struct notifier_block tegra_pmc_restart_handler = { |
662 | .notifier_call = tegra_pmc_restart_notify, | |
663 | .priority = 128, | |
664 | }; | |
665 | ||
7232398a TR |
666 | static int powergate_show(struct seq_file *s, void *data) |
667 | { | |
668 | unsigned int i; | |
c3ea2972 | 669 | int status; |
7232398a TR |
670 | |
671 | seq_printf(s, " powergate powered\n"); | |
672 | seq_printf(s, "------------------\n"); | |
673 | ||
674 | for (i = 0; i < pmc->soc->num_powergates; i++) { | |
c3ea2972 JH |
675 | status = tegra_powergate_is_powered(i); |
676 | if (status < 0) | |
7232398a TR |
677 | continue; |
678 | ||
679 | seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], | |
c3ea2972 | 680 | status ? "yes" : "no"); |
7232398a TR |
681 | } |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | static int powergate_open(struct inode *inode, struct file *file) | |
687 | { | |
688 | return single_open(file, powergate_show, inode->i_private); | |
689 | } | |
690 | ||
691 | static const struct file_operations powergate_fops = { | |
692 | .open = powergate_open, | |
693 | .read = seq_read, | |
694 | .llseek = seq_lseek, | |
695 | .release = single_release, | |
696 | }; | |
697 | ||
698 | static int tegra_powergate_debugfs_init(void) | |
699 | { | |
3195ac6d JH |
700 | pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, |
701 | &powergate_fops); | |
702 | if (!pmc->debugfs) | |
7232398a TR |
703 | return -ENOMEM; |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
a3804512 JH |
708 | static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, |
709 | struct device_node *np) | |
710 | { | |
711 | struct clk *clk; | |
712 | unsigned int i, count; | |
713 | int err; | |
714 | ||
715 | count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); | |
716 | if (count == 0) | |
717 | return -ENODEV; | |
718 | ||
719 | pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); | |
720 | if (!pg->clks) | |
721 | return -ENOMEM; | |
722 | ||
723 | for (i = 0; i < count; i++) { | |
724 | pg->clks[i] = of_clk_get(np, i); | |
725 | if (IS_ERR(pg->clks[i])) { | |
726 | err = PTR_ERR(pg->clks[i]); | |
727 | goto err; | |
728 | } | |
729 | } | |
730 | ||
731 | pg->num_clks = count; | |
732 | ||
733 | return 0; | |
734 | ||
735 | err: | |
736 | while (i--) | |
737 | clk_put(pg->clks[i]); | |
738 | kfree(pg->clks); | |
739 | ||
740 | return err; | |
741 | } | |
742 | ||
743 | static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, | |
05cfb988 | 744 | struct device_node *np, bool off) |
a3804512 JH |
745 | { |
746 | struct reset_control *rst; | |
747 | unsigned int i, count; | |
748 | int err; | |
749 | ||
750 | count = of_count_phandle_with_args(np, "resets", "#reset-cells"); | |
751 | if (count == 0) | |
752 | return -ENODEV; | |
753 | ||
754 | pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL); | |
755 | if (!pg->resets) | |
756 | return -ENOMEM; | |
757 | ||
758 | for (i = 0; i < count; i++) { | |
759 | pg->resets[i] = of_reset_control_get_by_index(np, i); | |
760 | if (IS_ERR(pg->resets[i])) { | |
761 | err = PTR_ERR(pg->resets[i]); | |
762 | goto error; | |
763 | } | |
05cfb988 JH |
764 | |
765 | if (off) | |
766 | err = reset_control_assert(pg->resets[i]); | |
767 | else | |
768 | err = reset_control_deassert(pg->resets[i]); | |
769 | ||
770 | if (err) { | |
771 | reset_control_put(pg->resets[i]); | |
772 | goto error; | |
773 | } | |
a3804512 JH |
774 | } |
775 | ||
776 | pg->num_resets = count; | |
777 | ||
778 | return 0; | |
779 | ||
780 | error: | |
781 | while (i--) | |
782 | reset_control_put(pg->resets[i]); | |
783 | kfree(pg->resets); | |
784 | ||
785 | return err; | |
786 | } | |
787 | ||
788 | static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) | |
789 | { | |
790 | struct tegra_powergate *pg; | |
791 | bool off; | |
792 | int id; | |
793 | ||
794 | pg = kzalloc(sizeof(*pg), GFP_KERNEL); | |
795 | if (!pg) | |
796 | goto error; | |
797 | ||
798 | id = tegra_powergate_lookup(pmc, np->name); | |
799 | if (id < 0) | |
800 | goto free_mem; | |
801 | ||
802 | /* | |
803 | * Clear the bit for this powergate so it cannot be managed | |
804 | * directly via the legacy APIs for controlling powergates. | |
805 | */ | |
806 | clear_bit(id, pmc->powergates_available); | |
807 | ||
808 | pg->id = id; | |
809 | pg->genpd.name = np->name; | |
810 | pg->genpd.power_off = tegra_genpd_power_off; | |
811 | pg->genpd.power_on = tegra_genpd_power_on; | |
812 | pg->pmc = pmc; | |
813 | ||
05cfb988 JH |
814 | off = !tegra_powergate_is_powered(pg->id); |
815 | ||
a3804512 JH |
816 | if (tegra_powergate_of_get_clks(pg, np)) |
817 | goto set_available; | |
818 | ||
05cfb988 | 819 | if (tegra_powergate_of_get_resets(pg, np, off)) |
a3804512 JH |
820 | goto remove_clks; |
821 | ||
a3804512 JH |
822 | pm_genpd_init(&pg->genpd, NULL, off); |
823 | ||
824 | if (of_genpd_add_provider_simple(np, &pg->genpd)) | |
825 | goto remove_resets; | |
826 | ||
827 | dev_dbg(pmc->dev, "added power domain %s\n", pg->genpd.name); | |
828 | ||
829 | return; | |
830 | ||
831 | remove_resets: | |
832 | while (pg->num_resets--) | |
833 | reset_control_put(pg->resets[pg->num_resets]); | |
834 | kfree(pg->resets); | |
835 | ||
836 | remove_clks: | |
837 | while (pg->num_clks--) | |
838 | clk_put(pg->clks[pg->num_clks]); | |
839 | kfree(pg->clks); | |
840 | ||
841 | set_available: | |
842 | set_bit(id, pmc->powergates_available); | |
843 | ||
844 | free_mem: | |
845 | kfree(pg); | |
846 | ||
847 | error: | |
848 | dev_err(pmc->dev, "failed to create power domain for %s\n", np->name); | |
849 | } | |
850 | ||
851 | static void tegra_powergate_init(struct tegra_pmc *pmc) | |
852 | { | |
853 | struct device_node *np, *child; | |
854 | ||
855 | np = of_get_child_by_name(pmc->dev->of_node, "powergates"); | |
856 | if (!np) | |
857 | return; | |
858 | ||
859 | for_each_child_of_node(np, child) { | |
860 | tegra_powergate_add(pmc, child); | |
861 | of_node_put(child); | |
862 | } | |
863 | ||
864 | of_node_put(np); | |
865 | } | |
866 | ||
70293ed0 | 867 | static int tegra_io_rail_prepare(unsigned int id, unsigned long *request, |
7232398a TR |
868 | unsigned long *status, unsigned int *bit) |
869 | { | |
870 | unsigned long rate, value; | |
7232398a TR |
871 | |
872 | *bit = id % 32; | |
873 | ||
874 | /* | |
875 | * There are two sets of 30 bits to select IO rails, but bits 30 and | |
876 | * 31 are control bits rather than IO rail selection bits. | |
877 | */ | |
878 | if (id > 63 || *bit == 30 || *bit == 31) | |
879 | return -EINVAL; | |
880 | ||
881 | if (id < 32) { | |
882 | *status = IO_DPD_STATUS; | |
883 | *request = IO_DPD_REQ; | |
884 | } else { | |
885 | *status = IO_DPD2_STATUS; | |
886 | *request = IO_DPD2_REQ; | |
887 | } | |
888 | ||
592431b0 | 889 | rate = clk_get_rate(pmc->clk); |
7232398a TR |
890 | |
891 | tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); | |
892 | ||
893 | /* must be at least 200 ns, in APB (PCLK) clock cycles */ | |
894 | value = DIV_ROUND_UP(1000000000, rate); | |
895 | value = DIV_ROUND_UP(200, value); | |
896 | tegra_pmc_writel(value, SEL_DPD_TIM); | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, | |
902 | unsigned long val, unsigned long timeout) | |
903 | { | |
904 | unsigned long value; | |
905 | ||
906 | timeout = jiffies + msecs_to_jiffies(timeout); | |
907 | ||
908 | while (time_after(timeout, jiffies)) { | |
909 | value = tegra_pmc_readl(offset); | |
910 | if ((value & mask) == val) | |
911 | return 0; | |
912 | ||
913 | usleep_range(250, 1000); | |
914 | } | |
915 | ||
916 | return -ETIMEDOUT; | |
917 | } | |
918 | ||
919 | static void tegra_io_rail_unprepare(void) | |
920 | { | |
921 | tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); | |
922 | } | |
923 | ||
70293ed0 | 924 | int tegra_io_rail_power_on(unsigned int id) |
7232398a TR |
925 | { |
926 | unsigned long request, status, value; | |
927 | unsigned int bit, mask; | |
928 | int err; | |
929 | ||
e8cf6616 JH |
930 | mutex_lock(&pmc->powergates_lock); |
931 | ||
7232398a | 932 | err = tegra_io_rail_prepare(id, &request, &status, &bit); |
e8cf6616 JH |
933 | if (err) |
934 | goto error; | |
7232398a TR |
935 | |
936 | mask = 1 << bit; | |
937 | ||
938 | value = tegra_pmc_readl(request); | |
939 | value |= mask; | |
940 | value &= ~IO_DPD_REQ_CODE_MASK; | |
941 | value |= IO_DPD_REQ_CODE_OFF; | |
942 | tegra_pmc_writel(value, request); | |
943 | ||
944 | err = tegra_io_rail_poll(status, mask, 0, 250); | |
e8cf6616 | 945 | if (err) { |
592431b0 | 946 | pr_info("tegra_io_rail_poll() failed: %d\n", err); |
e8cf6616 | 947 | goto error; |
592431b0 | 948 | } |
7232398a TR |
949 | |
950 | tegra_io_rail_unprepare(); | |
951 | ||
e8cf6616 JH |
952 | error: |
953 | mutex_unlock(&pmc->powergates_lock); | |
954 | ||
955 | return err; | |
7232398a TR |
956 | } |
957 | EXPORT_SYMBOL(tegra_io_rail_power_on); | |
958 | ||
70293ed0 | 959 | int tegra_io_rail_power_off(unsigned int id) |
7232398a TR |
960 | { |
961 | unsigned long request, status, value; | |
962 | unsigned int bit, mask; | |
963 | int err; | |
964 | ||
e8cf6616 JH |
965 | mutex_lock(&pmc->powergates_lock); |
966 | ||
7232398a | 967 | err = tegra_io_rail_prepare(id, &request, &status, &bit); |
e8cf6616 | 968 | if (err) { |
592431b0 | 969 | pr_info("tegra_io_rail_prepare() failed: %d\n", err); |
e8cf6616 | 970 | goto error; |
592431b0 | 971 | } |
7232398a TR |
972 | |
973 | mask = 1 << bit; | |
974 | ||
975 | value = tegra_pmc_readl(request); | |
976 | value |= mask; | |
977 | value &= ~IO_DPD_REQ_CODE_MASK; | |
978 | value |= IO_DPD_REQ_CODE_ON; | |
979 | tegra_pmc_writel(value, request); | |
980 | ||
981 | err = tegra_io_rail_poll(status, mask, mask, 250); | |
e8cf6616 JH |
982 | if (err) |
983 | goto error; | |
7232398a TR |
984 | |
985 | tegra_io_rail_unprepare(); | |
986 | ||
e8cf6616 JH |
987 | error: |
988 | mutex_unlock(&pmc->powergates_lock); | |
989 | ||
990 | return err; | |
7232398a TR |
991 | } |
992 | EXPORT_SYMBOL(tegra_io_rail_power_off); | |
993 | ||
994 | #ifdef CONFIG_PM_SLEEP | |
995 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) | |
996 | { | |
997 | return pmc->suspend_mode; | |
998 | } | |
999 | ||
1000 | void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) | |
1001 | { | |
1002 | if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) | |
1003 | return; | |
1004 | ||
1005 | pmc->suspend_mode = mode; | |
1006 | } | |
1007 | ||
1008 | void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) | |
1009 | { | |
1010 | unsigned long long rate = 0; | |
1011 | u32 value; | |
1012 | ||
1013 | switch (mode) { | |
1014 | case TEGRA_SUSPEND_LP1: | |
1015 | rate = 32768; | |
1016 | break; | |
1017 | ||
1018 | case TEGRA_SUSPEND_LP2: | |
1019 | rate = clk_get_rate(pmc->clk); | |
1020 | break; | |
1021 | ||
1022 | default: | |
1023 | break; | |
1024 | } | |
1025 | ||
1026 | if (WARN_ON_ONCE(rate == 0)) | |
1027 | rate = 100000000; | |
1028 | ||
1029 | if (rate != pmc->rate) { | |
1030 | u64 ticks; | |
1031 | ||
1032 | ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; | |
1033 | do_div(ticks, USEC_PER_SEC); | |
1034 | tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); | |
1035 | ||
1036 | ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; | |
1037 | do_div(ticks, USEC_PER_SEC); | |
1038 | tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); | |
1039 | ||
1040 | wmb(); | |
1041 | ||
1042 | pmc->rate = rate; | |
1043 | } | |
1044 | ||
1045 | value = tegra_pmc_readl(PMC_CNTRL); | |
1046 | value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; | |
1047 | value |= PMC_CNTRL_CPU_PWRREQ_OE; | |
1048 | tegra_pmc_writel(value, PMC_CNTRL); | |
1049 | } | |
1050 | #endif | |
1051 | ||
1052 | static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) | |
1053 | { | |
1054 | u32 value, values[2]; | |
1055 | ||
1056 | if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { | |
1057 | } else { | |
1058 | switch (value) { | |
1059 | case 0: | |
1060 | pmc->suspend_mode = TEGRA_SUSPEND_LP0; | |
1061 | break; | |
1062 | ||
1063 | case 1: | |
1064 | pmc->suspend_mode = TEGRA_SUSPEND_LP1; | |
1065 | break; | |
1066 | ||
1067 | case 2: | |
1068 | pmc->suspend_mode = TEGRA_SUSPEND_LP2; | |
1069 | break; | |
1070 | ||
1071 | default: | |
1072 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1073 | break; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); | |
1078 | ||
1079 | if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) | |
1080 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1081 | ||
1082 | pmc->cpu_good_time = value; | |
1083 | ||
1084 | if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) | |
1085 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1086 | ||
1087 | pmc->cpu_off_time = value; | |
1088 | ||
1089 | if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", | |
1090 | values, ARRAY_SIZE(values))) | |
1091 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1092 | ||
1093 | pmc->core_osc_time = values[0]; | |
1094 | pmc->core_pmu_time = values[1]; | |
1095 | ||
1096 | if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) | |
1097 | pmc->suspend_mode = TEGRA_SUSPEND_NONE; | |
1098 | ||
1099 | pmc->core_off_time = value; | |
1100 | ||
1101 | pmc->corereq_high = of_property_read_bool(np, | |
1102 | "nvidia,core-power-req-active-high"); | |
1103 | ||
1104 | pmc->sysclkreq_high = of_property_read_bool(np, | |
1105 | "nvidia,sys-clock-req-active-high"); | |
1106 | ||
1107 | pmc->combined_req = of_property_read_bool(np, | |
1108 | "nvidia,combined-power-req"); | |
1109 | ||
1110 | pmc->cpu_pwr_good_en = of_property_read_bool(np, | |
1111 | "nvidia,cpu-pwr-good-en"); | |
1112 | ||
1113 | if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, | |
1114 | ARRAY_SIZE(values))) | |
1115 | if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) | |
1116 | pmc->suspend_mode = TEGRA_SUSPEND_LP1; | |
1117 | ||
1118 | pmc->lp0_vec_phys = values[0]; | |
1119 | pmc->lp0_vec_size = values[1]; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static void tegra_pmc_init(struct tegra_pmc *pmc) | |
1125 | { | |
1126 | u32 value; | |
1127 | ||
1128 | /* Always enable CPU power request */ | |
1129 | value = tegra_pmc_readl(PMC_CNTRL); | |
1130 | value |= PMC_CNTRL_CPU_PWRREQ_OE; | |
1131 | tegra_pmc_writel(value, PMC_CNTRL); | |
1132 | ||
1133 | value = tegra_pmc_readl(PMC_CNTRL); | |
1134 | ||
1135 | if (pmc->sysclkreq_high) | |
1136 | value &= ~PMC_CNTRL_SYSCLK_POLARITY; | |
1137 | else | |
1138 | value |= PMC_CNTRL_SYSCLK_POLARITY; | |
1139 | ||
1140 | /* configure the output polarity while the request is tristated */ | |
1141 | tegra_pmc_writel(value, PMC_CNTRL); | |
1142 | ||
1143 | /* now enable the request */ | |
1144 | value = tegra_pmc_readl(PMC_CNTRL); | |
1145 | value |= PMC_CNTRL_SYSCLK_OE; | |
1146 | tegra_pmc_writel(value, PMC_CNTRL); | |
1147 | } | |
1148 | ||
1e52efdf | 1149 | static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) |
3568df3d MP |
1150 | { |
1151 | static const char disabled[] = "emergency thermal reset disabled"; | |
1152 | u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; | |
1153 | struct device *dev = pmc->dev; | |
1154 | struct device_node *np; | |
1155 | u32 value, checksum; | |
1156 | ||
1157 | if (!pmc->soc->has_tsense_reset) | |
95169cd2 | 1158 | return; |
3568df3d MP |
1159 | |
1160 | np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); | |
1161 | if (!np) { | |
1162 | dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); | |
95169cd2 | 1163 | return; |
3568df3d MP |
1164 | } |
1165 | ||
1166 | if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { | |
1167 | dev_err(dev, "I2C controller ID missing, %s.\n", disabled); | |
1168 | goto out; | |
1169 | } | |
1170 | ||
1171 | if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { | |
1172 | dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); | |
1173 | goto out; | |
1174 | } | |
1175 | ||
1176 | if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { | |
1177 | dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); | |
1178 | goto out; | |
1179 | } | |
1180 | ||
1181 | if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { | |
1182 | dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); | |
1183 | goto out; | |
1184 | } | |
1185 | ||
1186 | if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) | |
1187 | pinmux = 0; | |
1188 | ||
1189 | value = tegra_pmc_readl(PMC_SENSOR_CTRL); | |
1190 | value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; | |
1191 | tegra_pmc_writel(value, PMC_SENSOR_CTRL); | |
1192 | ||
1193 | value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | | |
1194 | (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); | |
1195 | tegra_pmc_writel(value, PMC_SCRATCH54); | |
1196 | ||
1197 | value = PMC_SCRATCH55_RESET_TEGRA; | |
1198 | value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; | |
1199 | value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; | |
1200 | value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; | |
1201 | ||
1202 | /* | |
1203 | * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will | |
1204 | * contain the checksum and are currently zero, so they are not added. | |
1205 | */ | |
1206 | checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) | |
1207 | + ((value >> 24) & 0xff); | |
1208 | checksum &= 0xff; | |
1209 | checksum = 0x100 - checksum; | |
1210 | ||
1211 | value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; | |
1212 | ||
1213 | tegra_pmc_writel(value, PMC_SCRATCH55); | |
1214 | ||
1215 | value = tegra_pmc_readl(PMC_SENSOR_CTRL); | |
1216 | value |= PMC_SENSOR_CTRL_ENABLE_RST; | |
1217 | tegra_pmc_writel(value, PMC_SENSOR_CTRL); | |
1218 | ||
1219 | dev_info(pmc->dev, "emergency thermal reset enabled\n"); | |
1220 | ||
1221 | out: | |
1222 | of_node_put(np); | |
3568df3d MP |
1223 | } |
1224 | ||
7232398a TR |
1225 | static int tegra_pmc_probe(struct platform_device *pdev) |
1226 | { | |
e8cf6616 | 1227 | void __iomem *base; |
7232398a TR |
1228 | struct resource *res; |
1229 | int err; | |
1230 | ||
1231 | err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); | |
1232 | if (err < 0) | |
1233 | return err; | |
1234 | ||
1235 | /* take over the memory region from the early initialization */ | |
1236 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0259f522 JH |
1237 | base = devm_ioremap_resource(&pdev->dev, res); |
1238 | if (IS_ERR(base)) | |
1239 | return PTR_ERR(base); | |
7232398a TR |
1240 | |
1241 | pmc->clk = devm_clk_get(&pdev->dev, "pclk"); | |
1242 | if (IS_ERR(pmc->clk)) { | |
1243 | err = PTR_ERR(pmc->clk); | |
1244 | dev_err(&pdev->dev, "failed to get pclk: %d\n", err); | |
1245 | return err; | |
1246 | } | |
1247 | ||
3568df3d MP |
1248 | pmc->dev = &pdev->dev; |
1249 | ||
7232398a TR |
1250 | tegra_pmc_init(pmc); |
1251 | ||
3568df3d MP |
1252 | tegra_pmc_init_tsense_reset(pmc); |
1253 | ||
7232398a TR |
1254 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { |
1255 | err = tegra_powergate_debugfs_init(); | |
1256 | if (err < 0) | |
1257 | return err; | |
7892158a DR |
1258 | } |
1259 | ||
1260 | err = register_restart_handler(&tegra_pmc_restart_handler); | |
1261 | if (err) { | |
3195ac6d | 1262 | debugfs_remove(pmc->debugfs); |
7892158a DR |
1263 | dev_err(&pdev->dev, "unable to register restart handler, %d\n", |
1264 | err); | |
1265 | return err; | |
7232398a TR |
1266 | } |
1267 | ||
a3804512 JH |
1268 | tegra_powergate_init(pmc); |
1269 | ||
e8cf6616 JH |
1270 | mutex_lock(&pmc->powergates_lock); |
1271 | iounmap(pmc->base); | |
0259f522 | 1272 | pmc->base = base; |
e8cf6616 | 1273 | mutex_unlock(&pmc->powergates_lock); |
0259f522 | 1274 | |
7232398a TR |
1275 | return 0; |
1276 | } | |
1277 | ||
2b20b616 | 1278 | #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) |
7232398a TR |
1279 | static int tegra_pmc_suspend(struct device *dev) |
1280 | { | |
1281 | tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); | |
1282 | ||
1283 | return 0; | |
1284 | } | |
1285 | ||
1286 | static int tegra_pmc_resume(struct device *dev) | |
1287 | { | |
1288 | tegra_pmc_writel(0x0, PMC_SCRATCH41); | |
1289 | ||
1290 | return 0; | |
1291 | } | |
7232398a TR |
1292 | |
1293 | static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); | |
1294 | ||
2b20b616 PW |
1295 | #endif |
1296 | ||
7232398a TR |
1297 | static const char * const tegra20_powergates[] = { |
1298 | [TEGRA_POWERGATE_CPU] = "cpu", | |
1299 | [TEGRA_POWERGATE_3D] = "3d", | |
1300 | [TEGRA_POWERGATE_VENC] = "venc", | |
1301 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
1302 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
1303 | [TEGRA_POWERGATE_L2] = "l2", | |
1304 | [TEGRA_POWERGATE_MPE] = "mpe", | |
1305 | }; | |
1306 | ||
1307 | static const struct tegra_pmc_soc tegra20_pmc_soc = { | |
1308 | .num_powergates = ARRAY_SIZE(tegra20_powergates), | |
1309 | .powergates = tegra20_powergates, | |
1310 | .num_cpu_powergates = 0, | |
1311 | .cpu_powergates = NULL, | |
3568df3d | 1312 | .has_tsense_reset = false, |
a9a40a4a | 1313 | .has_gpu_clamps = false, |
7232398a TR |
1314 | }; |
1315 | ||
1316 | static const char * const tegra30_powergates[] = { | |
1317 | [TEGRA_POWERGATE_CPU] = "cpu0", | |
1318 | [TEGRA_POWERGATE_3D] = "3d0", | |
1319 | [TEGRA_POWERGATE_VENC] = "venc", | |
1320 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
1321 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
1322 | [TEGRA_POWERGATE_L2] = "l2", | |
1323 | [TEGRA_POWERGATE_MPE] = "mpe", | |
1324 | [TEGRA_POWERGATE_HEG] = "heg", | |
1325 | [TEGRA_POWERGATE_SATA] = "sata", | |
1326 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
1327 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
1328 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
1329 | [TEGRA_POWERGATE_CELP] = "celp", | |
1330 | [TEGRA_POWERGATE_3D1] = "3d1", | |
1331 | }; | |
1332 | ||
1333 | static const u8 tegra30_cpu_powergates[] = { | |
1334 | TEGRA_POWERGATE_CPU, | |
1335 | TEGRA_POWERGATE_CPU1, | |
1336 | TEGRA_POWERGATE_CPU2, | |
1337 | TEGRA_POWERGATE_CPU3, | |
1338 | }; | |
1339 | ||
1340 | static const struct tegra_pmc_soc tegra30_pmc_soc = { | |
1341 | .num_powergates = ARRAY_SIZE(tegra30_powergates), | |
1342 | .powergates = tegra30_powergates, | |
1343 | .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), | |
1344 | .cpu_powergates = tegra30_cpu_powergates, | |
3568df3d | 1345 | .has_tsense_reset = true, |
a9a40a4a | 1346 | .has_gpu_clamps = false, |
7232398a TR |
1347 | }; |
1348 | ||
1349 | static const char * const tegra114_powergates[] = { | |
1350 | [TEGRA_POWERGATE_CPU] = "crail", | |
1351 | [TEGRA_POWERGATE_3D] = "3d", | |
1352 | [TEGRA_POWERGATE_VENC] = "venc", | |
1353 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
1354 | [TEGRA_POWERGATE_MPE] = "mpe", | |
1355 | [TEGRA_POWERGATE_HEG] = "heg", | |
1356 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
1357 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
1358 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
1359 | [TEGRA_POWERGATE_CELP] = "celp", | |
1360 | [TEGRA_POWERGATE_CPU0] = "cpu0", | |
1361 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
1362 | [TEGRA_POWERGATE_C1NC] = "c1nc", | |
1363 | [TEGRA_POWERGATE_DIS] = "dis", | |
1364 | [TEGRA_POWERGATE_DISB] = "disb", | |
1365 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
1366 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
1367 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
1368 | }; | |
1369 | ||
1370 | static const u8 tegra114_cpu_powergates[] = { | |
1371 | TEGRA_POWERGATE_CPU0, | |
1372 | TEGRA_POWERGATE_CPU1, | |
1373 | TEGRA_POWERGATE_CPU2, | |
1374 | TEGRA_POWERGATE_CPU3, | |
1375 | }; | |
1376 | ||
1377 | static const struct tegra_pmc_soc tegra114_pmc_soc = { | |
1378 | .num_powergates = ARRAY_SIZE(tegra114_powergates), | |
1379 | .powergates = tegra114_powergates, | |
1380 | .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), | |
1381 | .cpu_powergates = tegra114_cpu_powergates, | |
3568df3d | 1382 | .has_tsense_reset = true, |
a9a40a4a | 1383 | .has_gpu_clamps = false, |
7232398a TR |
1384 | }; |
1385 | ||
1386 | static const char * const tegra124_powergates[] = { | |
1387 | [TEGRA_POWERGATE_CPU] = "crail", | |
1388 | [TEGRA_POWERGATE_3D] = "3d", | |
1389 | [TEGRA_POWERGATE_VENC] = "venc", | |
1390 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
1391 | [TEGRA_POWERGATE_VDEC] = "vdec", | |
7232398a TR |
1392 | [TEGRA_POWERGATE_MPE] = "mpe", |
1393 | [TEGRA_POWERGATE_HEG] = "heg", | |
1394 | [TEGRA_POWERGATE_SATA] = "sata", | |
1395 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
1396 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
1397 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
1398 | [TEGRA_POWERGATE_CELP] = "celp", | |
1399 | [TEGRA_POWERGATE_CPU0] = "cpu0", | |
1400 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
1401 | [TEGRA_POWERGATE_C1NC] = "c1nc", | |
1402 | [TEGRA_POWERGATE_SOR] = "sor", | |
1403 | [TEGRA_POWERGATE_DIS] = "dis", | |
1404 | [TEGRA_POWERGATE_DISB] = "disb", | |
1405 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
1406 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
1407 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
1408 | [TEGRA_POWERGATE_VIC] = "vic", | |
1409 | [TEGRA_POWERGATE_IRAM] = "iram", | |
1410 | }; | |
1411 | ||
1412 | static const u8 tegra124_cpu_powergates[] = { | |
1413 | TEGRA_POWERGATE_CPU0, | |
1414 | TEGRA_POWERGATE_CPU1, | |
1415 | TEGRA_POWERGATE_CPU2, | |
1416 | TEGRA_POWERGATE_CPU3, | |
1417 | }; | |
1418 | ||
1419 | static const struct tegra_pmc_soc tegra124_pmc_soc = { | |
1420 | .num_powergates = ARRAY_SIZE(tegra124_powergates), | |
1421 | .powergates = tegra124_powergates, | |
1422 | .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), | |
1423 | .cpu_powergates = tegra124_cpu_powergates, | |
3568df3d | 1424 | .has_tsense_reset = true, |
a9a40a4a | 1425 | .has_gpu_clamps = true, |
7232398a TR |
1426 | }; |
1427 | ||
c2fe4694 TR |
1428 | static const char * const tegra210_powergates[] = { |
1429 | [TEGRA_POWERGATE_CPU] = "crail", | |
1430 | [TEGRA_POWERGATE_3D] = "3d", | |
1431 | [TEGRA_POWERGATE_VENC] = "venc", | |
1432 | [TEGRA_POWERGATE_PCIE] = "pcie", | |
c2fe4694 | 1433 | [TEGRA_POWERGATE_MPE] = "mpe", |
c2fe4694 TR |
1434 | [TEGRA_POWERGATE_SATA] = "sata", |
1435 | [TEGRA_POWERGATE_CPU1] = "cpu1", | |
1436 | [TEGRA_POWERGATE_CPU2] = "cpu2", | |
1437 | [TEGRA_POWERGATE_CPU3] = "cpu3", | |
c2fe4694 TR |
1438 | [TEGRA_POWERGATE_CPU0] = "cpu0", |
1439 | [TEGRA_POWERGATE_C0NC] = "c0nc", | |
c2fe4694 TR |
1440 | [TEGRA_POWERGATE_SOR] = "sor", |
1441 | [TEGRA_POWERGATE_DIS] = "dis", | |
1442 | [TEGRA_POWERGATE_DISB] = "disb", | |
1443 | [TEGRA_POWERGATE_XUSBA] = "xusba", | |
1444 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | |
1445 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | |
1446 | [TEGRA_POWERGATE_VIC] = "vic", | |
1447 | [TEGRA_POWERGATE_IRAM] = "iram", | |
1448 | [TEGRA_POWERGATE_NVDEC] = "nvdec", | |
1449 | [TEGRA_POWERGATE_NVJPG] = "nvjpg", | |
1450 | [TEGRA_POWERGATE_AUD] = "aud", | |
1451 | [TEGRA_POWERGATE_DFD] = "dfd", | |
1452 | [TEGRA_POWERGATE_VE2] = "ve2", | |
1453 | }; | |
1454 | ||
1455 | static const u8 tegra210_cpu_powergates[] = { | |
1456 | TEGRA_POWERGATE_CPU0, | |
1457 | TEGRA_POWERGATE_CPU1, | |
1458 | TEGRA_POWERGATE_CPU2, | |
1459 | TEGRA_POWERGATE_CPU3, | |
1460 | }; | |
1461 | ||
1462 | static const struct tegra_pmc_soc tegra210_pmc_soc = { | |
1463 | .num_powergates = ARRAY_SIZE(tegra210_powergates), | |
1464 | .powergates = tegra210_powergates, | |
1465 | .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), | |
1466 | .cpu_powergates = tegra210_cpu_powergates, | |
1467 | .has_tsense_reset = true, | |
1468 | .has_gpu_clamps = true, | |
1469 | }; | |
1470 | ||
7232398a | 1471 | static const struct of_device_id tegra_pmc_match[] = { |
c2fe4694 | 1472 | { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, |
7d71e903 | 1473 | { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, |
7232398a TR |
1474 | { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, |
1475 | { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, | |
1476 | { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, | |
1477 | { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, | |
1478 | { } | |
1479 | }; | |
1480 | ||
1481 | static struct platform_driver tegra_pmc_driver = { | |
1482 | .driver = { | |
1483 | .name = "tegra-pmc", | |
1484 | .suppress_bind_attrs = true, | |
1485 | .of_match_table = tegra_pmc_match, | |
2b20b616 | 1486 | #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) |
7232398a | 1487 | .pm = &tegra_pmc_pm_ops, |
2b20b616 | 1488 | #endif |
7232398a TR |
1489 | }, |
1490 | .probe = tegra_pmc_probe, | |
1491 | }; | |
7d4d9ed6 | 1492 | builtin_platform_driver(tegra_pmc_driver); |
7232398a TR |
1493 | |
1494 | /* | |
1495 | * Early initialization to allow access to registers in the very early boot | |
1496 | * process. | |
1497 | */ | |
1498 | static int __init tegra_pmc_early_init(void) | |
1499 | { | |
1500 | const struct of_device_id *match; | |
1501 | struct device_node *np; | |
1502 | struct resource regs; | |
a3804512 | 1503 | unsigned int i; |
7232398a TR |
1504 | bool invert; |
1505 | u32 value; | |
1506 | ||
61fd284b JH |
1507 | mutex_init(&pmc->powergates_lock); |
1508 | ||
7232398a TR |
1509 | np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); |
1510 | if (!np) { | |
7d71e903 TR |
1511 | /* |
1512 | * Fall back to legacy initialization for 32-bit ARM only. All | |
1513 | * 64-bit ARM device tree files for Tegra are required to have | |
1514 | * a PMC node. | |
1515 | * | |
1516 | * This is for backwards-compatibility with old device trees | |
1517 | * that didn't contain a PMC node. Note that in this case the | |
1518 | * SoC data can't be matched and therefore powergating is | |
1519 | * disabled. | |
1520 | */ | |
1521 | if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { | |
1522 | pr_warn("DT node not found, powergating disabled\n"); | |
1523 | ||
1524 | regs.start = 0x7000e400; | |
1525 | regs.end = 0x7000e7ff; | |
1526 | regs.flags = IORESOURCE_MEM; | |
1527 | ||
1528 | pr_warn("Using memory region %pR\n", ®s); | |
1529 | } else { | |
1530 | /* | |
1531 | * At this point we're not running on Tegra, so play | |
1532 | * nice with multi-platform kernels. | |
1533 | */ | |
1534 | return 0; | |
1535 | } | |
7232398a | 1536 | } else { |
7d71e903 TR |
1537 | /* |
1538 | * Extract information from the device tree if we've found a | |
1539 | * matching node. | |
1540 | */ | |
1541 | if (of_address_to_resource(np, 0, ®s) < 0) { | |
1542 | pr_err("failed to get PMC registers\n"); | |
1543 | return -ENXIO; | |
1544 | } | |
7232398a TR |
1545 | } |
1546 | ||
1547 | pmc->base = ioremap_nocache(regs.start, resource_size(®s)); | |
1548 | if (!pmc->base) { | |
1549 | pr_err("failed to map PMC registers\n"); | |
1550 | return -ENXIO; | |
1551 | } | |
1552 | ||
11131895 | 1553 | if (np) { |
718a2426 JH |
1554 | pmc->soc = match->data; |
1555 | ||
11131895 JH |
1556 | /* Create a bit-map of the available and valid partitions */ |
1557 | for (i = 0; i < pmc->soc->num_powergates; i++) | |
1558 | if (pmc->soc->powergates[i]) | |
1559 | set_bit(i, pmc->powergates_available); | |
7232398a | 1560 | |
11131895 JH |
1561 | /* |
1562 | * Invert the interrupt polarity if a PMC device tree node | |
1563 | * exists and contains the nvidia,invert-interrupt property. | |
1564 | */ | |
1565 | invert = of_property_read_bool(np, "nvidia,invert-interrupt"); | |
7232398a | 1566 | |
11131895 | 1567 | value = tegra_pmc_readl(PMC_CNTRL); |
7232398a | 1568 | |
11131895 JH |
1569 | if (invert) |
1570 | value |= PMC_CNTRL_INTR_POLARITY; | |
1571 | else | |
1572 | value &= ~PMC_CNTRL_INTR_POLARITY; | |
1573 | ||
1574 | tegra_pmc_writel(value, PMC_CNTRL); | |
1575 | } | |
7232398a TR |
1576 | |
1577 | return 0; | |
1578 | } | |
1579 | early_initcall(tegra_pmc_early_init); |