Commit | Line | Data |
---|---|---|
00b8fd23 | 1 | /* |
57cc0979 | 2 | * MPC52xx PSC in SPI mode driver. |
00b8fd23 DC |
3 | * |
4 | * Maintainer: Dragos Carp | |
5 | * | |
6 | * Copyright (C) 2006 TOPTICA Photonics AG. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/interrupt.h> | |
18 | ||
19 | #if defined(CONFIG_PPC_MERGE) | |
76ef7dd0 | 20 | #include <linux/of_platform.h> |
00b8fd23 DC |
21 | #else |
22 | #include <linux/platform_device.h> | |
23 | #endif | |
24 | ||
25 | #include <linux/workqueue.h> | |
26 | #include <linux/completion.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/spi/spi.h> | |
30 | #include <linux/fsl_devices.h> | |
31 | ||
32 | #include <asm/mpc52xx.h> | |
33 | #include <asm/mpc52xx_psc.h> | |
34 | ||
35 | #define MCLK 20000000 /* PSC port MClk in hz */ | |
36 | ||
37 | struct mpc52xx_psc_spi { | |
38 | /* fsl_spi_platform data */ | |
39 | void (*activate_cs)(u8, u8); | |
40 | void (*deactivate_cs)(u8, u8); | |
41 | u32 sysclk; | |
42 | ||
43 | /* driver internal data */ | |
44 | struct mpc52xx_psc __iomem *psc; | |
4874cc1b | 45 | struct mpc52xx_psc_fifo __iomem *fifo; |
00b8fd23 DC |
46 | unsigned int irq; |
47 | u8 bits_per_word; | |
48 | u8 busy; | |
49 | ||
50 | struct workqueue_struct *workqueue; | |
51 | struct work_struct work; | |
52 | ||
53 | struct list_head queue; | |
54 | spinlock_t lock; | |
55 | ||
56 | struct completion done; | |
57 | }; | |
58 | ||
59 | /* controller state */ | |
60 | struct mpc52xx_psc_spi_cs { | |
61 | int bits_per_word; | |
62 | int speed_hz; | |
63 | }; | |
64 | ||
65 | /* set clock freq, clock ramp, bits per work | |
66 | * if t is NULL then reset the values to the default values | |
67 | */ | |
68 | static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi, | |
69 | struct spi_transfer *t) | |
70 | { | |
71 | struct mpc52xx_psc_spi_cs *cs = spi->controller_state; | |
72 | ||
73 | cs->speed_hz = (t && t->speed_hz) | |
74 | ? t->speed_hz : spi->max_speed_hz; | |
75 | cs->bits_per_word = (t && t->bits_per_word) | |
76 | ? t->bits_per_word : spi->bits_per_word; | |
77 | cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; | |
78 | return 0; | |
79 | } | |
80 | ||
81 | static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi) | |
82 | { | |
83 | struct mpc52xx_psc_spi_cs *cs = spi->controller_state; | |
84 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
85 | struct mpc52xx_psc __iomem *psc = mps->psc; | |
86 | u32 sicr; | |
87 | u16 ccr; | |
88 | ||
89 | sicr = in_be32(&psc->sicr); | |
90 | ||
91 | /* Set clock phase and polarity */ | |
92 | if (spi->mode & SPI_CPHA) | |
93 | sicr |= 0x00001000; | |
94 | else | |
95 | sicr &= ~0x00001000; | |
96 | if (spi->mode & SPI_CPOL) | |
97 | sicr |= 0x00002000; | |
98 | else | |
99 | sicr &= ~0x00002000; | |
100 | ||
101 | if (spi->mode & SPI_LSB_FIRST) | |
102 | sicr |= 0x10000000; | |
103 | else | |
104 | sicr &= ~0x10000000; | |
105 | out_be32(&psc->sicr, sicr); | |
106 | ||
107 | /* Set clock frequency and bits per word | |
108 | * Because psc->ccr is defined as 16bit register instead of 32bit | |
109 | * just set the lower byte of BitClkDiv | |
110 | */ | |
111 | ccr = in_be16(&psc->ccr); | |
112 | ccr &= 0xFF00; | |
113 | if (cs->speed_hz) | |
114 | ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; | |
115 | else /* by default SPI Clk 1MHz */ | |
116 | ccr |= (MCLK / 1000000 - 1) & 0xFF; | |
117 | out_be16(&psc->ccr, ccr); | |
118 | mps->bits_per_word = cs->bits_per_word; | |
119 | ||
120 | if (mps->activate_cs) | |
121 | mps->activate_cs(spi->chip_select, | |
122 | (spi->mode & SPI_CS_HIGH) ? 1 : 0); | |
123 | } | |
124 | ||
125 | static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi) | |
126 | { | |
127 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
128 | ||
129 | if (mps->deactivate_cs) | |
130 | mps->deactivate_cs(spi->chip_select, | |
131 | (spi->mode & SPI_CS_HIGH) ? 1 : 0); | |
132 | } | |
133 | ||
134 | #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1) | |
135 | /* wake up when 80% fifo full */ | |
136 | #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100) | |
137 | ||
138 | static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi, | |
139 | struct spi_transfer *t) | |
140 | { | |
141 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
142 | struct mpc52xx_psc __iomem *psc = mps->psc; | |
4874cc1b | 143 | struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; |
00b8fd23 DC |
144 | unsigned rb = 0; /* number of bytes receieved */ |
145 | unsigned sb = 0; /* number of bytes sent */ | |
146 | unsigned char *rx_buf = (unsigned char *)t->rx_buf; | |
147 | unsigned char *tx_buf = (unsigned char *)t->tx_buf; | |
148 | unsigned rfalarm; | |
149 | unsigned send_at_once = MPC52xx_PSC_BUFSIZE; | |
150 | unsigned recv_at_once; | |
00b8fd23 DC |
151 | |
152 | if (!t->tx_buf && !t->rx_buf && t->len) | |
153 | return -EINVAL; | |
154 | ||
155 | /* enable transmiter/receiver */ | |
156 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); | |
157 | while (rb < t->len) { | |
158 | if (t->len - rb > MPC52xx_PSC_BUFSIZE) { | |
159 | rfalarm = MPC52xx_PSC_RFALARM; | |
160 | } else { | |
161 | send_at_once = t->len - sb; | |
162 | rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb); | |
163 | } | |
164 | ||
165 | dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once); | |
9a7867e1 LF |
166 | for (; send_at_once; sb++, send_at_once--) { |
167 | /* set EOF flag before the last word is sent */ | |
168 | if (send_at_once == 1) | |
169 | out_8(&psc->ircr2, 0x01); | |
170 | ||
171 | if (tx_buf) | |
00b8fd23 | 172 | out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]); |
9a7867e1 | 173 | else |
00b8fd23 | 174 | out_8(&psc->mpc52xx_psc_buffer_8, 0); |
00b8fd23 DC |
175 | } |
176 | ||
177 | ||
3a4fa0a2 | 178 | /* enable interrupts and wait for wake up |
00b8fd23 DC |
179 | * if just one byte is expected the Rx FIFO genererates no |
180 | * FFULL interrupt, so activate the RxRDY interrupt | |
181 | */ | |
182 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); | |
183 | if (t->len - rb == 1) { | |
184 | out_8(&psc->mode, 0); | |
185 | } else { | |
186 | out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); | |
4874cc1b | 187 | out_be16(&fifo->rfalarm, rfalarm); |
00b8fd23 DC |
188 | } |
189 | out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY); | |
190 | wait_for_completion(&mps->done); | |
4874cc1b | 191 | recv_at_once = in_be16(&fifo->rfnum); |
00b8fd23 DC |
192 | dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once); |
193 | ||
194 | send_at_once = recv_at_once; | |
195 | if (rx_buf) { | |
196 | for (; recv_at_once; rb++, recv_at_once--) | |
197 | rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8); | |
198 | } else { | |
199 | for (; recv_at_once; rb++, recv_at_once--) | |
200 | in_8(&psc->mpc52xx_psc_buffer_8); | |
201 | } | |
202 | } | |
203 | /* disable transmiter/receiver */ | |
204 | out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | static void mpc52xx_psc_spi_work(struct work_struct *work) | |
210 | { | |
211 | struct mpc52xx_psc_spi *mps = | |
212 | container_of(work, struct mpc52xx_psc_spi, work); | |
213 | ||
214 | spin_lock_irq(&mps->lock); | |
215 | mps->busy = 1; | |
216 | while (!list_empty(&mps->queue)) { | |
217 | struct spi_message *m; | |
218 | struct spi_device *spi; | |
219 | struct spi_transfer *t = NULL; | |
220 | unsigned cs_change; | |
221 | int status; | |
222 | ||
223 | m = container_of(mps->queue.next, struct spi_message, queue); | |
224 | list_del_init(&m->queue); | |
225 | spin_unlock_irq(&mps->lock); | |
226 | ||
227 | spi = m->spi; | |
228 | cs_change = 1; | |
229 | status = 0; | |
230 | list_for_each_entry (t, &m->transfers, transfer_list) { | |
231 | if (t->bits_per_word || t->speed_hz) { | |
232 | status = mpc52xx_psc_spi_transfer_setup(spi, t); | |
233 | if (status < 0) | |
234 | break; | |
235 | } | |
236 | ||
237 | if (cs_change) | |
238 | mpc52xx_psc_spi_activate_cs(spi); | |
239 | cs_change = t->cs_change; | |
240 | ||
241 | status = mpc52xx_psc_spi_transfer_rxtx(spi, t); | |
242 | if (status) | |
243 | break; | |
244 | m->actual_length += t->len; | |
245 | ||
246 | if (t->delay_usecs) | |
247 | udelay(t->delay_usecs); | |
248 | ||
249 | if (cs_change) | |
250 | mpc52xx_psc_spi_deactivate_cs(spi); | |
251 | } | |
252 | ||
253 | m->status = status; | |
254 | m->complete(m->context); | |
255 | ||
256 | if (status || !cs_change) | |
257 | mpc52xx_psc_spi_deactivate_cs(spi); | |
258 | ||
259 | mpc52xx_psc_spi_transfer_setup(spi, NULL); | |
260 | ||
261 | spin_lock_irq(&mps->lock); | |
262 | } | |
263 | mps->busy = 0; | |
264 | spin_unlock_irq(&mps->lock); | |
265 | } | |
266 | ||
dccd573b DB |
267 | /* the spi->mode bits understood by this driver: */ |
268 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST) | |
269 | ||
00b8fd23 DC |
270 | static int mpc52xx_psc_spi_setup(struct spi_device *spi) |
271 | { | |
272 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
273 | struct mpc52xx_psc_spi_cs *cs = spi->controller_state; | |
274 | unsigned long flags; | |
275 | ||
276 | if (spi->bits_per_word%8) | |
277 | return -EINVAL; | |
278 | ||
dccd573b DB |
279 | if (spi->mode & ~MODEBITS) { |
280 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
281 | spi->mode & ~MODEBITS); | |
282 | return -EINVAL; | |
283 | } | |
284 | ||
00b8fd23 DC |
285 | if (!cs) { |
286 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
287 | if (!cs) | |
288 | return -ENOMEM; | |
289 | spi->controller_state = cs; | |
290 | } | |
291 | ||
292 | cs->bits_per_word = spi->bits_per_word; | |
293 | cs->speed_hz = spi->max_speed_hz; | |
294 | ||
295 | spin_lock_irqsave(&mps->lock, flags); | |
296 | if (!mps->busy) | |
297 | mpc52xx_psc_spi_deactivate_cs(spi); | |
298 | spin_unlock_irqrestore(&mps->lock, flags); | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | static int mpc52xx_psc_spi_transfer(struct spi_device *spi, | |
304 | struct spi_message *m) | |
305 | { | |
306 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); | |
307 | unsigned long flags; | |
308 | ||
309 | m->actual_length = 0; | |
310 | m->status = -EINPROGRESS; | |
311 | ||
312 | spin_lock_irqsave(&mps->lock, flags); | |
313 | list_add_tail(&m->queue, &mps->queue); | |
314 | queue_work(mps->workqueue, &mps->work); | |
315 | spin_unlock_irqrestore(&mps->lock, flags); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static void mpc52xx_psc_spi_cleanup(struct spi_device *spi) | |
321 | { | |
322 | kfree(spi->controller_state); | |
323 | } | |
324 | ||
325 | static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps) | |
326 | { | |
00b8fd23 | 327 | struct mpc52xx_psc __iomem *psc = mps->psc; |
4874cc1b | 328 | struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; |
00b8fd23 DC |
329 | u32 mclken_div; |
330 | int ret = 0; | |
331 | ||
00b8fd23 | 332 | /* default sysclk is 512MHz */ |
4fb4c558 GL |
333 | mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; |
334 | mpc52xx_set_psc_clkdiv(psc_id, mclken_div); | |
00b8fd23 DC |
335 | |
336 | /* Reset the PSC into a known state */ | |
337 | out_8(&psc->command, MPC52xx_PSC_RST_RX); | |
338 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
339 | out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); | |
340 | ||
341 | /* Disable interrupts, interrupts are based on alarm level */ | |
342 | out_be16(&psc->mpc52xx_psc_imr, 0); | |
343 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); | |
4874cc1b | 344 | out_8(&fifo->rfcntl, 0); |
00b8fd23 DC |
345 | out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); |
346 | ||
347 | /* Configure 8bit codec mode as a SPI master and use EOF flags */ | |
348 | /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */ | |
349 | out_be32(&psc->sicr, 0x0180C800); | |
350 | out_be16(&psc->ccr, 0x070F); /* by default SPI Clk 1MHz */ | |
351 | ||
352 | /* Set 2ms DTL delay */ | |
353 | out_8(&psc->ctur, 0x00); | |
354 | out_8(&psc->ctlr, 0x84); | |
355 | ||
356 | mps->bits_per_word = 8; | |
357 | ||
00b8fd23 DC |
358 | return ret; |
359 | } | |
360 | ||
361 | static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id) | |
362 | { | |
363 | struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id; | |
364 | struct mpc52xx_psc __iomem *psc = mps->psc; | |
365 | ||
366 | /* disable interrupt and wake up the work queue */ | |
367 | if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) { | |
368 | out_be16(&psc->mpc52xx_psc_imr, 0); | |
369 | complete(&mps->done); | |
370 | return IRQ_HANDLED; | |
371 | } | |
372 | return IRQ_NONE; | |
373 | } | |
374 | ||
375 | /* bus_num is used only for the case dev->platform_data == NULL */ | |
376 | static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, | |
377 | u32 size, unsigned int irq, s16 bus_num) | |
378 | { | |
379 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
380 | struct mpc52xx_psc_spi *mps; | |
381 | struct spi_master *master; | |
382 | int ret; | |
383 | ||
00b8fd23 DC |
384 | master = spi_alloc_master(dev, sizeof *mps); |
385 | if (master == NULL) | |
386 | return -ENOMEM; | |
387 | ||
388 | dev_set_drvdata(dev, master); | |
389 | mps = spi_master_get_devdata(master); | |
390 | ||
391 | mps->irq = irq; | |
392 | if (pdata == NULL) { | |
393 | dev_warn(dev, "probe called without platform data, no " | |
394 | "(de)activate_cs function will be called\n"); | |
395 | mps->activate_cs = NULL; | |
396 | mps->deactivate_cs = NULL; | |
397 | mps->sysclk = 0; | |
398 | master->bus_num = bus_num; | |
399 | master->num_chipselect = 255; | |
400 | } else { | |
401 | mps->activate_cs = pdata->activate_cs; | |
402 | mps->deactivate_cs = pdata->deactivate_cs; | |
403 | mps->sysclk = pdata->sysclk; | |
404 | master->bus_num = pdata->bus_num; | |
405 | master->num_chipselect = pdata->max_chipselect; | |
406 | } | |
407 | master->setup = mpc52xx_psc_spi_setup; | |
408 | master->transfer = mpc52xx_psc_spi_transfer; | |
409 | master->cleanup = mpc52xx_psc_spi_cleanup; | |
410 | ||
411 | mps->psc = ioremap(regaddr, size); | |
412 | if (!mps->psc) { | |
413 | dev_err(dev, "could not ioremap I/O port range\n"); | |
414 | ret = -EFAULT; | |
415 | goto free_master; | |
416 | } | |
4874cc1b GL |
417 | /* On the 5200, fifo regs are immediately ajacent to the psc regs */ |
418 | mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc); | |
00b8fd23 DC |
419 | |
420 | ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi", | |
421 | mps); | |
422 | if (ret) | |
423 | goto free_master; | |
424 | ||
425 | ret = mpc52xx_psc_spi_port_config(master->bus_num, mps); | |
426 | if (ret < 0) | |
427 | goto free_irq; | |
428 | ||
429 | spin_lock_init(&mps->lock); | |
430 | init_completion(&mps->done); | |
431 | INIT_WORK(&mps->work, mpc52xx_psc_spi_work); | |
432 | INIT_LIST_HEAD(&mps->queue); | |
433 | ||
434 | mps->workqueue = create_singlethread_workqueue( | |
49dce689 | 435 | master->dev.parent->bus_id); |
00b8fd23 DC |
436 | if (mps->workqueue == NULL) { |
437 | ret = -EBUSY; | |
438 | goto free_irq; | |
439 | } | |
440 | ||
441 | ret = spi_register_master(master); | |
442 | if (ret < 0) | |
443 | goto unreg_master; | |
444 | ||
445 | return ret; | |
446 | ||
447 | unreg_master: | |
448 | destroy_workqueue(mps->workqueue); | |
449 | free_irq: | |
450 | free_irq(mps->irq, mps); | |
451 | free_master: | |
452 | if (mps->psc) | |
453 | iounmap(mps->psc); | |
454 | spi_master_put(master); | |
455 | ||
456 | return ret; | |
457 | } | |
458 | ||
459 | static int __exit mpc52xx_psc_spi_do_remove(struct device *dev) | |
460 | { | |
461 | struct spi_master *master = dev_get_drvdata(dev); | |
462 | struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master); | |
463 | ||
464 | flush_workqueue(mps->workqueue); | |
465 | destroy_workqueue(mps->workqueue); | |
466 | spi_unregister_master(master); | |
467 | free_irq(mps->irq, mps); | |
468 | if (mps->psc) | |
469 | iounmap(mps->psc); | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | #if !defined(CONFIG_PPC_MERGE) | |
475 | static int __init mpc52xx_psc_spi_probe(struct platform_device *dev) | |
476 | { | |
477 | switch(dev->id) { | |
478 | case 1: | |
479 | case 2: | |
480 | case 3: | |
481 | case 6: | |
482 | return mpc52xx_psc_spi_do_probe(&dev->dev, | |
483 | MPC52xx_PA(MPC52xx_PSCx_OFFSET(dev->id)), | |
484 | MPC52xx_PSC_SIZE, platform_get_irq(dev, 0), dev->id); | |
485 | default: | |
486 | return -EINVAL; | |
487 | } | |
488 | } | |
489 | ||
490 | static int __exit mpc52xx_psc_spi_remove(struct platform_device *dev) | |
491 | { | |
492 | return mpc52xx_psc_spi_do_remove(&dev->dev); | |
493 | } | |
494 | ||
7e38c3c4 KS |
495 | /* work with hotplug and coldplug */ |
496 | MODULE_ALIAS("platform:mpc52xx-psc-spi"); | |
497 | ||
00b8fd23 DC |
498 | static struct platform_driver mpc52xx_psc_spi_platform_driver = { |
499 | .remove = __exit_p(mpc52xx_psc_spi_remove), | |
500 | .driver = { | |
501 | .name = "mpc52xx-psc-spi", | |
502 | .owner = THIS_MODULE, | |
503 | }, | |
504 | }; | |
505 | ||
506 | static int __init mpc52xx_psc_spi_init(void) | |
507 | { | |
508 | return platform_driver_probe(&mpc52xx_psc_spi_platform_driver, | |
509 | mpc52xx_psc_spi_probe); | |
510 | } | |
511 | module_init(mpc52xx_psc_spi_init); | |
512 | ||
513 | static void __exit mpc52xx_psc_spi_exit(void) | |
514 | { | |
515 | platform_driver_unregister(&mpc52xx_psc_spi_platform_driver); | |
516 | } | |
517 | module_exit(mpc52xx_psc_spi_exit); | |
518 | ||
519 | #else /* defined(CONFIG_PPC_MERGE) */ | |
520 | ||
521 | static int __init mpc52xx_psc_spi_of_probe(struct of_device *op, | |
522 | const struct of_device_id *match) | |
523 | { | |
524 | const u32 *regaddr_p; | |
525 | u64 regaddr64, size64; | |
526 | s16 id = -1; | |
527 | ||
528 | regaddr_p = of_get_address(op->node, 0, &size64, NULL); | |
529 | if (!regaddr_p) { | |
530 | printk(KERN_ERR "Invalid PSC address\n"); | |
531 | return -EINVAL; | |
532 | } | |
533 | regaddr64 = of_translate_address(op->node, regaddr_p); | |
534 | ||
8888735f | 535 | /* get PSC id (1..6, used by port_config) */ |
00b8fd23 | 536 | if (op->dev.platform_data == NULL) { |
8888735f | 537 | const u32 *psc_nump; |
00b8fd23 | 538 | |
8888735f DP |
539 | psc_nump = of_get_property(op->node, "cell-index", NULL); |
540 | if (!psc_nump || *psc_nump > 5) { | |
541 | printk(KERN_ERR "mpc52xx_psc_spi: Device node %s has invalid " | |
542 | "cell-index property\n", op->node->full_name); | |
543 | return -EINVAL; | |
00b8fd23 | 544 | } |
8888735f | 545 | id = *psc_nump + 1; |
00b8fd23 DC |
546 | } |
547 | ||
548 | return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64, | |
549 | irq_of_parse_and_map(op->node, 0), id); | |
550 | } | |
551 | ||
552 | static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op) | |
553 | { | |
554 | return mpc52xx_psc_spi_do_remove(&op->dev); | |
555 | } | |
556 | ||
557 | static struct of_device_id mpc52xx_psc_spi_of_match[] = { | |
66ffbe49 GL |
558 | { .compatible = "fsl,mpc5200-psc-spi", }, |
559 | { .compatible = "mpc5200-psc-spi", }, /* old */ | |
560 | {} | |
00b8fd23 DC |
561 | }; |
562 | ||
563 | MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match); | |
564 | ||
565 | static struct of_platform_driver mpc52xx_psc_spi_of_driver = { | |
566 | .owner = THIS_MODULE, | |
567 | .name = "mpc52xx-psc-spi", | |
568 | .match_table = mpc52xx_psc_spi_of_match, | |
569 | .probe = mpc52xx_psc_spi_of_probe, | |
570 | .remove = __exit_p(mpc52xx_psc_spi_of_remove), | |
571 | .driver = { | |
572 | .name = "mpc52xx-psc-spi", | |
573 | .owner = THIS_MODULE, | |
574 | }, | |
575 | }; | |
576 | ||
577 | static int __init mpc52xx_psc_spi_init(void) | |
578 | { | |
579 | return of_register_platform_driver(&mpc52xx_psc_spi_of_driver); | |
580 | } | |
581 | module_init(mpc52xx_psc_spi_init); | |
582 | ||
583 | static void __exit mpc52xx_psc_spi_exit(void) | |
584 | { | |
585 | of_unregister_platform_driver(&mpc52xx_psc_spi_of_driver); | |
586 | } | |
587 | module_exit(mpc52xx_psc_spi_exit); | |
588 | ||
589 | #endif /* defined(CONFIG_PPC_MERGE) */ | |
590 | ||
591 | MODULE_AUTHOR("Dragos Carp"); | |
592 | MODULE_DESCRIPTION("MPC52xx PSC SPI Driver"); | |
593 | MODULE_LICENSE("GPL"); |