[deliverable/linux.git] / drivers / spi / spi-ath79.c

/*
 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
 *
 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 *
 * This driver has been based on the spi-gpio.c:
 *	Copyright (C) 2006,2008 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79_spi_platform.h>

#define DRV_NAME	"ath79-spi"

#define ATH79_SPI_RRW_DELAY_FACTOR	12000
#define MHZ				(1000 * 1000)

struct ath79_spi {
	struct spi_bitbang	bitbang;
	u32			ioc_base;
	u32			reg_ctrl;
	void __iomem		*base;
	struct clk		*clk;
	unsigned		rrw_delay;
};

static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
{
	return ioread32(sp->base + reg);
}

static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
{
	iowrite32(val, sp->base + reg);
}

static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
{
	return spi_master_get_devdata(spi->master);
}

static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
{
	if (nsecs > sp->rrw_delay)
		ndelay(nsecs - sp->rrw_delay);
}

static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;

	if (is_active) {
		/* set initial clock polarity */
		if (spi->mode & SPI_CPOL)
			sp->ioc_base |= AR71XX_SPI_IOC_CLK;
		else
			sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

	if (spi->chip_select) {
		/* SPI is normally active-low */
		gpio_set_value(spi->cs_gpio, cs_high);
	} else {
		if (cs_high)
			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
		else
			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

}

static void ath79_spi_enable(struct ath79_spi *sp)
{
	/* enable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);

	/* save CTRL register */
	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);

	/* TODO: setup speed? */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
}

static void ath79_spi_disable(struct ath79_spi *sp)
{
	/* restore CTRL register */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	/* disable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
}

static int ath79_spi_setup_cs(struct spi_device *spi)
{
	int status;

	if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
		return -EINVAL;

	status = 0;
	if (spi->chip_select) {
		unsigned long flags;

		flags = GPIOF_DIR_OUT;
		if (spi->mode & SPI_CS_HIGH)
			flags |= GPIOF_INIT_LOW;
		else
			flags |= GPIOF_INIT_HIGH;

		status = gpio_request_one(spi->cs_gpio, flags,
					  dev_name(&spi->dev));
	}

	return status;
}

static void ath79_spi_cleanup_cs(struct spi_device *spi)
{
	if (spi->chip_select) {
		gpio_free(spi->cs_gpio);
	}
}

static int ath79_spi_setup(struct spi_device *spi)
{
	int status = 0;

	if (!spi->controller_state) {
		status = ath79_spi_setup_cs(spi);
		if (status)
			return status;
	}

	status = spi_bitbang_setup(spi);
	if (status && !spi->controller_state)
		ath79_spi_cleanup_cs(spi);

	return status;
}

static void ath79_spi_cleanup(struct spi_device *spi)
{
	ath79_spi_cleanup_cs(spi);
	spi_bitbang_cleanup(spi);
}

static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
			       u32 word, u8 bits)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	u32 ioc = sp->ioc_base;

	/* clock starts at inactive polarity */
	for (word <<= (32 - bits); likely(bits); bits--) {
		u32 out;

		if (word & (1 << 31))
			out = ioc | AR71XX_SPI_IOC_DO;
		else
			out = ioc & ~AR71XX_SPI_IOC_DO;

		/* setup MSB (to slave) on trailing edge */
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
		ath79_spi_delay(sp, nsecs);
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
		ath79_spi_delay(sp, nsecs);
		if (bits == 1)
			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);

		word <<= 1;
	}

	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}

static int ath79_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct ath79_spi *sp;
	struct ath79_spi_platform_data *pdata;
	struct resource	*r;
	unsigned long rate;
	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	if (master == NULL) {
		dev_err(&pdev->dev, "failed to allocate spi master\n");
		return -ENOMEM;
	}

	sp = spi_master_get_devdata(master);
	master->dev.of_node = pdev->dev.of_node;
	platform_set_drvdata(pdev, sp);

	pdata = dev_get_platdata(&pdev->dev);

	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
	master->setup = ath79_spi_setup;
	master->cleanup = ath79_spi_cleanup;
	if (pdata) {
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->num_chipselect;
	}

	sp->bitbang.master = master;
	sp->bitbang.chipselect = ath79_spi_chipselect;
	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
	sp->bitbang.flags = SPI_CS_HIGH;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENOENT;
		goto err_put_master;
	}

	sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!sp->base) {
		ret = -ENXIO;
		goto err_put_master;
	}

	sp->clk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(sp->clk)) {
		ret = PTR_ERR(sp->clk);
		goto err_put_master;
	}

	ret = clk_prepare_enable(sp->clk);
	if (ret)
		goto err_put_master;

	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	if (!rate) {
		ret = -EINVAL;
		goto err_clk_disable;
	}

	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
		sp->rrw_delay);

	ath79_spi_enable(sp);
	ret = spi_bitbang_start(&sp->bitbang);
	if (ret)
		goto err_disable;

	return 0;

err_disable:
	ath79_spi_disable(sp);
err_clk_disable:
	clk_disable_unprepare(sp->clk);
err_put_master:
	spi_master_put(sp->bitbang.master);

	return ret;
}

static int ath79_spi_remove(struct platform_device *pdev)
{
	struct ath79_spi *sp = platform_get_drvdata(pdev);

	spi_bitbang_stop(&sp->bitbang);
	ath79_spi_disable(sp);
	clk_disable_unprepare(sp->clk);
	spi_master_put(sp->bitbang.master);

	return 0;
}

static void ath79_spi_shutdown(struct platform_device *pdev)
{
	ath79_spi_remove(pdev);
}

static const struct of_device_id ath79_spi_of_match[] = {
	{ .compatible = "qca,ar7100-spi", },
	{ },
};

static struct platform_driver ath79_spi_driver = {
	.probe		= ath79_spi_probe,
	.remove		= ath79_spi_remove,
	.shutdown	= ath79_spi_shutdown,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = ath79_spi_of_match,
	},
};
module_platform_driver(ath79_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
8efaef4d GJ	1	/*
	2	* SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
	3	*
	4	* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	5	*
	6	* This driver has been based on the spi-gpio.c:
	7	* Copyright (C) 2006,2008 David Brownell
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
807cc4b1	16	#include <linux/module.h>
8efaef4d GJ	17	#include <linux/delay.h>
8efaef4d GJ	18	#include <linux/spinlock.h>
8efaef4d GJ	19	#include <linux/platform_device.h>
	20	#include <linux/io.h>
	21	#include <linux/spi/spi.h>
	22	#include <linux/spi/spi_bitbang.h>
	23	#include <linux/bitops.h>
	24	#include <linux/gpio.h>
440114fd GJ	25	#include <linux/clk.h>
440114fd GJ	26	#include <linux/err.h>
8efaef4d GJ	27
	28	#include <asm/mach-ath79/ar71xx_regs.h>
	29	#include <asm/mach-ath79/ath79_spi_platform.h>
	30
	31	#define DRV_NAME "ath79-spi"
	32
440114fd GJ	33	#define ATH79_SPI_RRW_DELAY_FACTOR 12000
	34	#define MHZ (1000 * 1000)
	35
8efaef4d GJ	36	struct ath79_spi {
	37	struct spi_bitbang bitbang;
	38	u32 ioc_base;
	39	u32 reg_ctrl;
	40	void __iomem *base;
440114fd GJ	41	struct clk *clk;
440114fd GJ	42	unsigned rrw_delay;
8efaef4d GJ	43	};
	44
	45	static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
	46	{
	47	return ioread32(sp->base + reg);
	48	}
	49
	50	static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
	51	{
	52	iowrite32(val, sp->base + reg);
	53	}
	54
	55	static inline struct ath79_spi ath79_spidev_to_sp(struct spi_device spi)
	56	{
	57	return spi_master_get_devdata(spi->master);
	58	}
	59
440114fd GJ	60	static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
	61	{
	62	if (nsecs > sp->rrw_delay)
	63	ndelay(nsecs - sp->rrw_delay);
	64	}
	65
8efaef4d GJ	66	static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
	67	{
	68	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	69	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
	70
	71	if (is_active) {
	72	/* set initial clock polarity */
	73	if (spi->mode & SPI_CPOL)
	74	sp->ioc_base \|= AR71XX_SPI_IOC_CLK;
	75	else
	76	sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
	77
	78	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	79	}
	80
	81	if (spi->chip_select) {
8efaef4d	82	/* SPI is normally active-low */
85f62476	83	gpio_set_value(spi->cs_gpio, cs_high);
8efaef4d GJ	84	} else {
	85	if (cs_high)
	86	sp->ioc_base \|= AR71XX_SPI_IOC_CS0;
	87	else
	88	sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
	89
	90	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	91	}
	92
	93	}
	94
c4a31f43	95	static void ath79_spi_enable(struct ath79_spi *sp)
8efaef4d	96	{
8efaef4d GJ	97	/* enable GPIO mode */
	98	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
	99
	100	/* save CTRL register */
	101	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	102	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
	103
	104	/* TODO: setup speed? */
	105	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
c4a31f43 GJ	106	}
	107
	108	static void ath79_spi_disable(struct ath79_spi *sp)
	109	{
	110	/* restore CTRL register */
	111	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	112	/* disable GPIO mode */
	113	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
	114	}
	115
	116	static int ath79_spi_setup_cs(struct spi_device *spi)
	117	{
c4a31f43 GJ	118	int status;
c4a31f43 GJ	119
85f62476	120	if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
c4a31f43	121	return -EINVAL;
8efaef4d	122
95d79419	123	status = 0;
8efaef4d	124	if (spi->chip_select) {
95d79419 GJ	125	unsigned long flags;
	126
	127	flags = GPIOF_DIR_OUT;
	128	if (spi->mode & SPI_CS_HIGH)
95d79419	129	flags \|= GPIOF_INIT_LOW;
61d1cf16 GJ	130	else
61d1cf16 GJ	131	flags \|= GPIOF_INIT_HIGH;
95d79419	132
85f62476	133	status = gpio_request_one(spi->cs_gpio, flags,
95d79419	134	dev_name(&spi->dev));
8efaef4d GJ	135	}
8efaef4d GJ	136
95d79419	137	return status;
8efaef4d GJ	138	}
	139
	140	static void ath79_spi_cleanup_cs(struct spi_device *spi)
	141	{
8efaef4d	142	if (spi->chip_select) {
85f62476	143	gpio_free(spi->cs_gpio);
8efaef4d	144	}
8efaef4d GJ	145	}
	146
	147	static int ath79_spi_setup(struct spi_device *spi)
	148	{
	149	int status = 0;
	150
8efaef4d GJ	151	if (!spi->controller_state) {
	152	status = ath79_spi_setup_cs(spi);
	153	if (status)
	154	return status;
	155	}
	156
	157	status = spi_bitbang_setup(spi);
	158	if (status && !spi->controller_state)
	159	ath79_spi_cleanup_cs(spi);
	160
	161	return status;
	162	}
	163
	164	static void ath79_spi_cleanup(struct spi_device *spi)
	165	{
	166	ath79_spi_cleanup_cs(spi);
	167	spi_bitbang_cleanup(spi);
	168	}
	169
	170	static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
	171	u32 word, u8 bits)
	172	{
	173	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	174	u32 ioc = sp->ioc_base;
	175
	176	/* clock starts at inactive polarity */
	177	for (word <<= (32 - bits); likely(bits); bits--) {
	178	u32 out;
	179
	180	if (word & (1 << 31))
	181	out = ioc \| AR71XX_SPI_IOC_DO;
	182	else
	183	out = ioc & ~AR71XX_SPI_IOC_DO;
	184
	185	/* setup MSB (to slave) on trailing edge */
	186	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
440114fd	187	ath79_spi_delay(sp, nsecs);
8efaef4d	188	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out \| AR71XX_SPI_IOC_CLK);
440114fd	189	ath79_spi_delay(sp, nsecs);
72611db0 GJ	190	if (bits == 1)
72611db0 GJ	191	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
8efaef4d GJ	192
	193	word <<= 1;
	194	}
	195
	196	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
	197	}
	198
fd4a319b	199	static int ath79_spi_probe(struct platform_device *pdev)
8efaef4d GJ	200	{
	201	struct spi_master *master;
	202	struct ath79_spi *sp;
	203	struct ath79_spi_platform_data *pdata;
	204	struct resource *r;
440114fd	205	unsigned long rate;
8efaef4d GJ	206	int ret;
	207
	208	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	209	if (master == NULL) {
	210	dev_err(&pdev->dev, "failed to allocate spi master\n");
	211	return -ENOMEM;
	212	}
	213
	214	sp = spi_master_get_devdata(master);
85f62476	215	master->dev.of_node = pdev->dev.of_node;
8efaef4d GJ	216	platform_set_drvdata(pdev, sp);
8efaef4d GJ	217
8074cf06	218	pdata = dev_get_platdata(&pdev->dev);
8efaef4d	219
24778be2	220	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
8efaef4d GJ	221	master->setup = ath79_spi_setup;
	222	master->cleanup = ath79_spi_cleanup;
	223	if (pdata) {
	224	master->bus_num = pdata->bus_num;
	225	master->num_chipselect = pdata->num_chipselect;
8efaef4d GJ	226	}
8efaef4d GJ	227
94c69f76	228	sp->bitbang.master = master;
8efaef4d GJ	229	sp->bitbang.chipselect = ath79_spi_chipselect;
	230	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	231	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
	232	sp->bitbang.flags = SPI_CS_HIGH;
	233
	234	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	235	if (r == NULL) {
	236	ret = -ENOENT;
	237	goto err_put_master;
	238	}
	239
a6f4c8e0	240	sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
8efaef4d GJ	241	if (!sp->base) {
	242	ret = -ENXIO;
	243	goto err_put_master;
	244	}
	245
a6f4c8e0	246	sp->clk = devm_clk_get(&pdev->dev, "ahb");
440114fd GJ	247	if (IS_ERR(sp->clk)) {
440114fd GJ	248	ret = PTR_ERR(sp->clk);
a6f4c8e0	249	goto err_put_master;
440114fd GJ	250	}
440114fd GJ	251
3e19acdc	252	ret = clk_prepare_enable(sp->clk);
440114fd	253	if (ret)
a6f4c8e0	254	goto err_put_master;
440114fd GJ	255
	256	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	257	if (!rate) {
	258	ret = -EINVAL;
	259	goto err_clk_disable;
	260	}
	261
	262	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	263	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
	264	sp->rrw_delay);
	265
c4a31f43	266	ath79_spi_enable(sp);
8efaef4d GJ	267	ret = spi_bitbang_start(&sp->bitbang);
8efaef4d GJ	268	if (ret)
c4a31f43	269	goto err_disable;
8efaef4d GJ	270
	271	return 0;
	272
c4a31f43 GJ	273	err_disable:
c4a31f43 GJ	274	ath79_spi_disable(sp);
440114fd	275	err_clk_disable:
3e19acdc	276	clk_disable_unprepare(sp->clk);
8efaef4d	277	err_put_master:
8efaef4d GJ	278	spi_master_put(sp->bitbang.master);
	279
	280	return ret;
	281	}
	282
fd4a319b	283	static int ath79_spi_remove(struct platform_device *pdev)
8efaef4d GJ	284	{
	285	struct ath79_spi *sp = platform_get_drvdata(pdev);
	286
	287	spi_bitbang_stop(&sp->bitbang);
c4a31f43	288	ath79_spi_disable(sp);
3e19acdc	289	clk_disable_unprepare(sp->clk);
8efaef4d GJ	290	spi_master_put(sp->bitbang.master);
	291
	292	return 0;
	293	}
	294
7410e848 GJ	295	static void ath79_spi_shutdown(struct platform_device *pdev)
	296	{
	297	ath79_spi_remove(pdev);
	298	}
	299
85f62476 AB	300	static const struct of_device_id ath79_spi_of_match[] = {
	301	{ .compatible = "qca,ar7100-spi", },
	302	{ },
	303	};
	304
8efaef4d GJ	305	static struct platform_driver ath79_spi_driver = {
8efaef4d GJ	306	.probe = ath79_spi_probe,
fd4a319b	307	.remove = ath79_spi_remove,
7410e848	308	.shutdown = ath79_spi_shutdown,
8efaef4d GJ	309	.driver = {
8efaef4d GJ	310	.name = DRV_NAME,
85f62476	311	.of_match_table = ath79_spi_of_match,
8efaef4d GJ	312	},
8efaef4d GJ	313	};
940ab889	314	module_platform_driver(ath79_spi_driver);
8efaef4d GJ	315
	316	MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
	317	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	318	MODULE_LICENSE("GPL v2");
	319	MODULE_ALIAS("platform:" DRV_NAME);