Commit | Line | Data |
---|---|---|
754ce4f2 HS |
1 | /* |
2 | * Driver for Atmel AT32 and AT91 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
1ccc404a | 18 | #include <linux/dmaengine.h> |
754ce4f2 HS |
19 | #include <linux/err.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/spi/spi.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
bcd2360c | 23 | #include <linux/platform_data/atmel.h> |
1ccc404a | 24 | #include <linux/platform_data/dma-atmel.h> |
850a5b67 | 25 | #include <linux/of.h> |
754ce4f2 | 26 | |
d4820b74 WY |
27 | #include <linux/io.h> |
28 | #include <linux/gpio.h> | |
bb2d1c36 | 29 | |
ca632f55 GL |
30 | /* SPI register offsets */ |
31 | #define SPI_CR 0x0000 | |
32 | #define SPI_MR 0x0004 | |
33 | #define SPI_RDR 0x0008 | |
34 | #define SPI_TDR 0x000c | |
35 | #define SPI_SR 0x0010 | |
36 | #define SPI_IER 0x0014 | |
37 | #define SPI_IDR 0x0018 | |
38 | #define SPI_IMR 0x001c | |
39 | #define SPI_CSR0 0x0030 | |
40 | #define SPI_CSR1 0x0034 | |
41 | #define SPI_CSR2 0x0038 | |
42 | #define SPI_CSR3 0x003c | |
d4820b74 | 43 | #define SPI_VERSION 0x00fc |
ca632f55 GL |
44 | #define SPI_RPR 0x0100 |
45 | #define SPI_RCR 0x0104 | |
46 | #define SPI_TPR 0x0108 | |
47 | #define SPI_TCR 0x010c | |
48 | #define SPI_RNPR 0x0110 | |
49 | #define SPI_RNCR 0x0114 | |
50 | #define SPI_TNPR 0x0118 | |
51 | #define SPI_TNCR 0x011c | |
52 | #define SPI_PTCR 0x0120 | |
53 | #define SPI_PTSR 0x0124 | |
54 | ||
55 | /* Bitfields in CR */ | |
56 | #define SPI_SPIEN_OFFSET 0 | |
57 | #define SPI_SPIEN_SIZE 1 | |
58 | #define SPI_SPIDIS_OFFSET 1 | |
59 | #define SPI_SPIDIS_SIZE 1 | |
60 | #define SPI_SWRST_OFFSET 7 | |
61 | #define SPI_SWRST_SIZE 1 | |
62 | #define SPI_LASTXFER_OFFSET 24 | |
63 | #define SPI_LASTXFER_SIZE 1 | |
64 | ||
65 | /* Bitfields in MR */ | |
66 | #define SPI_MSTR_OFFSET 0 | |
67 | #define SPI_MSTR_SIZE 1 | |
68 | #define SPI_PS_OFFSET 1 | |
69 | #define SPI_PS_SIZE 1 | |
70 | #define SPI_PCSDEC_OFFSET 2 | |
71 | #define SPI_PCSDEC_SIZE 1 | |
72 | #define SPI_FDIV_OFFSET 3 | |
73 | #define SPI_FDIV_SIZE 1 | |
74 | #define SPI_MODFDIS_OFFSET 4 | |
75 | #define SPI_MODFDIS_SIZE 1 | |
d4820b74 WY |
76 | #define SPI_WDRBT_OFFSET 5 |
77 | #define SPI_WDRBT_SIZE 1 | |
ca632f55 GL |
78 | #define SPI_LLB_OFFSET 7 |
79 | #define SPI_LLB_SIZE 1 | |
80 | #define SPI_PCS_OFFSET 16 | |
81 | #define SPI_PCS_SIZE 4 | |
82 | #define SPI_DLYBCS_OFFSET 24 | |
83 | #define SPI_DLYBCS_SIZE 8 | |
84 | ||
85 | /* Bitfields in RDR */ | |
86 | #define SPI_RD_OFFSET 0 | |
87 | #define SPI_RD_SIZE 16 | |
88 | ||
89 | /* Bitfields in TDR */ | |
90 | #define SPI_TD_OFFSET 0 | |
91 | #define SPI_TD_SIZE 16 | |
92 | ||
93 | /* Bitfields in SR */ | |
94 | #define SPI_RDRF_OFFSET 0 | |
95 | #define SPI_RDRF_SIZE 1 | |
96 | #define SPI_TDRE_OFFSET 1 | |
97 | #define SPI_TDRE_SIZE 1 | |
98 | #define SPI_MODF_OFFSET 2 | |
99 | #define SPI_MODF_SIZE 1 | |
100 | #define SPI_OVRES_OFFSET 3 | |
101 | #define SPI_OVRES_SIZE 1 | |
102 | #define SPI_ENDRX_OFFSET 4 | |
103 | #define SPI_ENDRX_SIZE 1 | |
104 | #define SPI_ENDTX_OFFSET 5 | |
105 | #define SPI_ENDTX_SIZE 1 | |
106 | #define SPI_RXBUFF_OFFSET 6 | |
107 | #define SPI_RXBUFF_SIZE 1 | |
108 | #define SPI_TXBUFE_OFFSET 7 | |
109 | #define SPI_TXBUFE_SIZE 1 | |
110 | #define SPI_NSSR_OFFSET 8 | |
111 | #define SPI_NSSR_SIZE 1 | |
112 | #define SPI_TXEMPTY_OFFSET 9 | |
113 | #define SPI_TXEMPTY_SIZE 1 | |
114 | #define SPI_SPIENS_OFFSET 16 | |
115 | #define SPI_SPIENS_SIZE 1 | |
116 | ||
117 | /* Bitfields in CSR0 */ | |
118 | #define SPI_CPOL_OFFSET 0 | |
119 | #define SPI_CPOL_SIZE 1 | |
120 | #define SPI_NCPHA_OFFSET 1 | |
121 | #define SPI_NCPHA_SIZE 1 | |
122 | #define SPI_CSAAT_OFFSET 3 | |
123 | #define SPI_CSAAT_SIZE 1 | |
124 | #define SPI_BITS_OFFSET 4 | |
125 | #define SPI_BITS_SIZE 4 | |
126 | #define SPI_SCBR_OFFSET 8 | |
127 | #define SPI_SCBR_SIZE 8 | |
128 | #define SPI_DLYBS_OFFSET 16 | |
129 | #define SPI_DLYBS_SIZE 8 | |
130 | #define SPI_DLYBCT_OFFSET 24 | |
131 | #define SPI_DLYBCT_SIZE 8 | |
132 | ||
133 | /* Bitfields in RCR */ | |
134 | #define SPI_RXCTR_OFFSET 0 | |
135 | #define SPI_RXCTR_SIZE 16 | |
136 | ||
137 | /* Bitfields in TCR */ | |
138 | #define SPI_TXCTR_OFFSET 0 | |
139 | #define SPI_TXCTR_SIZE 16 | |
140 | ||
141 | /* Bitfields in RNCR */ | |
142 | #define SPI_RXNCR_OFFSET 0 | |
143 | #define SPI_RXNCR_SIZE 16 | |
144 | ||
145 | /* Bitfields in TNCR */ | |
146 | #define SPI_TXNCR_OFFSET 0 | |
147 | #define SPI_TXNCR_SIZE 16 | |
148 | ||
149 | /* Bitfields in PTCR */ | |
150 | #define SPI_RXTEN_OFFSET 0 | |
151 | #define SPI_RXTEN_SIZE 1 | |
152 | #define SPI_RXTDIS_OFFSET 1 | |
153 | #define SPI_RXTDIS_SIZE 1 | |
154 | #define SPI_TXTEN_OFFSET 8 | |
155 | #define SPI_TXTEN_SIZE 1 | |
156 | #define SPI_TXTDIS_OFFSET 9 | |
157 | #define SPI_TXTDIS_SIZE 1 | |
158 | ||
159 | /* Constants for BITS */ | |
160 | #define SPI_BITS_8_BPT 0 | |
161 | #define SPI_BITS_9_BPT 1 | |
162 | #define SPI_BITS_10_BPT 2 | |
163 | #define SPI_BITS_11_BPT 3 | |
164 | #define SPI_BITS_12_BPT 4 | |
165 | #define SPI_BITS_13_BPT 5 | |
166 | #define SPI_BITS_14_BPT 6 | |
167 | #define SPI_BITS_15_BPT 7 | |
168 | #define SPI_BITS_16_BPT 8 | |
169 | ||
170 | /* Bit manipulation macros */ | |
171 | #define SPI_BIT(name) \ | |
172 | (1 << SPI_##name##_OFFSET) | |
a536d765 | 173 | #define SPI_BF(name, value) \ |
ca632f55 | 174 | (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) |
a536d765 | 175 | #define SPI_BFEXT(name, value) \ |
ca632f55 | 176 | (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) |
a536d765 SK |
177 | #define SPI_BFINS(name, value, old) \ |
178 | (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ | |
179 | | SPI_BF(name, value)) | |
ca632f55 GL |
180 | |
181 | /* Register access macros */ | |
a536d765 | 182 | #define spi_readl(port, reg) \ |
ca632f55 | 183 | __raw_readl((port)->regs + SPI_##reg) |
a536d765 | 184 | #define spi_writel(port, reg, value) \ |
ca632f55 GL |
185 | __raw_writel((value), (port)->regs + SPI_##reg) |
186 | ||
1ccc404a NF |
187 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
188 | * cache operations; better heuristics consider wordsize and bitrate. | |
189 | */ | |
190 | #define DMA_MIN_BYTES 16 | |
191 | ||
8090d6d1 WY |
192 | #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) |
193 | ||
1ccc404a NF |
194 | struct atmel_spi_dma { |
195 | struct dma_chan *chan_rx; | |
196 | struct dma_chan *chan_tx; | |
197 | struct scatterlist sgrx; | |
198 | struct scatterlist sgtx; | |
199 | struct dma_async_tx_descriptor *data_desc_rx; | |
200 | struct dma_async_tx_descriptor *data_desc_tx; | |
201 | ||
202 | struct at_dma_slave dma_slave; | |
203 | }; | |
204 | ||
d4820b74 WY |
205 | struct atmel_spi_caps { |
206 | bool is_spi2; | |
207 | bool has_wdrbt; | |
208 | bool has_dma_support; | |
209 | }; | |
754ce4f2 HS |
210 | |
211 | /* | |
212 | * The core SPI transfer engine just talks to a register bank to set up | |
213 | * DMA transfers; transfer queue progress is driven by IRQs. The clock | |
214 | * framework provides the base clock, subdivided for each spi_device. | |
754ce4f2 HS |
215 | */ |
216 | struct atmel_spi { | |
217 | spinlock_t lock; | |
8aad7924 | 218 | unsigned long flags; |
754ce4f2 | 219 | |
dfab30ee | 220 | phys_addr_t phybase; |
754ce4f2 HS |
221 | void __iomem *regs; |
222 | int irq; | |
223 | struct clk *clk; | |
224 | struct platform_device *pdev; | |
754ce4f2 | 225 | |
754ce4f2 | 226 | struct spi_transfer *current_transfer; |
154443c7 | 227 | unsigned long current_remaining_bytes; |
823cd045 | 228 | int done_status; |
754ce4f2 | 229 | |
8090d6d1 WY |
230 | struct completion xfer_completion; |
231 | ||
1ccc404a | 232 | /* scratch buffer */ |
754ce4f2 HS |
233 | void *buffer; |
234 | dma_addr_t buffer_dma; | |
d4820b74 WY |
235 | |
236 | struct atmel_spi_caps caps; | |
1ccc404a NF |
237 | |
238 | bool use_dma; | |
239 | bool use_pdc; | |
240 | /* dmaengine data */ | |
241 | struct atmel_spi_dma dma; | |
8090d6d1 WY |
242 | |
243 | bool keep_cs; | |
244 | bool cs_active; | |
754ce4f2 HS |
245 | }; |
246 | ||
5ee36c98 HS |
247 | /* Controller-specific per-slave state */ |
248 | struct atmel_spi_device { | |
249 | unsigned int npcs_pin; | |
250 | u32 csr; | |
251 | }; | |
252 | ||
754ce4f2 HS |
253 | #define BUFFER_SIZE PAGE_SIZE |
254 | #define INVALID_DMA_ADDRESS 0xffffffff | |
255 | ||
5bfa26ca HS |
256 | /* |
257 | * Version 2 of the SPI controller has | |
258 | * - CR.LASTXFER | |
259 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) | |
260 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) | |
261 | * - SPI_CSRx.CSAAT | |
262 | * - SPI_CSRx.SBCR allows faster clocking | |
5bfa26ca | 263 | */ |
d4820b74 | 264 | static bool atmel_spi_is_v2(struct atmel_spi *as) |
5bfa26ca | 265 | { |
d4820b74 | 266 | return as->caps.is_spi2; |
5bfa26ca HS |
267 | } |
268 | ||
754ce4f2 HS |
269 | /* |
270 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby | |
271 | * they assume that spi slave device state will not change on deselect, so | |
defbd3b4 DB |
272 | * that automagic deselection is OK. ("NPCSx rises if no data is to be |
273 | * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer | |
274 | * controllers have CSAAT and friends. | |
754ce4f2 | 275 | * |
defbd3b4 DB |
276 | * Since the CSAAT functionality is a bit weird on newer controllers as |
277 | * well, we use GPIO to control nCSx pins on all controllers, updating | |
278 | * MR.PCS to avoid confusing the controller. Using GPIOs also lets us | |
279 | * support active-high chipselects despite the controller's belief that | |
280 | * only active-low devices/systems exists. | |
281 | * | |
282 | * However, at91rm9200 has a second erratum whereby nCS0 doesn't work | |
283 | * right when driven with GPIO. ("Mode Fault does not allow more than one | |
284 | * Master on Chip Select 0.") No workaround exists for that ... so for | |
285 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, | |
286 | * and (c) will trigger that first erratum in some cases. | |
754ce4f2 HS |
287 | */ |
288 | ||
defbd3b4 | 289 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 290 | { |
5ee36c98 | 291 | struct atmel_spi_device *asd = spi->controller_state; |
754ce4f2 | 292 | unsigned active = spi->mode & SPI_CS_HIGH; |
defbd3b4 DB |
293 | u32 mr; |
294 | ||
d4820b74 | 295 | if (atmel_spi_is_v2(as)) { |
97ed465b WY |
296 | spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr); |
297 | /* For the low SPI version, there is a issue that PDC transfer | |
298 | * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS | |
5ee36c98 HS |
299 | */ |
300 | spi_writel(as, CSR0, asd->csr); | |
d4820b74 | 301 | if (as->caps.has_wdrbt) { |
97ed465b WY |
302 | spi_writel(as, MR, |
303 | SPI_BF(PCS, ~(0x01 << spi->chip_select)) | |
304 | | SPI_BIT(WDRBT) | |
305 | | SPI_BIT(MODFDIS) | |
306 | | SPI_BIT(MSTR)); | |
d4820b74 | 307 | } else { |
97ed465b WY |
308 | spi_writel(as, MR, |
309 | SPI_BF(PCS, ~(0x01 << spi->chip_select)) | |
310 | | SPI_BIT(MODFDIS) | |
311 | | SPI_BIT(MSTR)); | |
d4820b74 | 312 | } |
1ccc404a | 313 | |
5ee36c98 HS |
314 | mr = spi_readl(as, MR); |
315 | gpio_set_value(asd->npcs_pin, active); | |
316 | } else { | |
317 | u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; | |
318 | int i; | |
319 | u32 csr; | |
320 | ||
321 | /* Make sure clock polarity is correct */ | |
322 | for (i = 0; i < spi->master->num_chipselect; i++) { | |
323 | csr = spi_readl(as, CSR0 + 4 * i); | |
324 | if ((csr ^ cpol) & SPI_BIT(CPOL)) | |
325 | spi_writel(as, CSR0 + 4 * i, | |
326 | csr ^ SPI_BIT(CPOL)); | |
327 | } | |
328 | ||
329 | mr = spi_readl(as, MR); | |
330 | mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr); | |
331 | if (spi->chip_select != 0) | |
332 | gpio_set_value(asd->npcs_pin, active); | |
333 | spi_writel(as, MR, mr); | |
334 | } | |
defbd3b4 DB |
335 | |
336 | dev_dbg(&spi->dev, "activate %u%s, mr %08x\n", | |
5ee36c98 | 337 | asd->npcs_pin, active ? " (high)" : "", |
defbd3b4 | 338 | mr); |
754ce4f2 HS |
339 | } |
340 | ||
defbd3b4 | 341 | static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 342 | { |
5ee36c98 | 343 | struct atmel_spi_device *asd = spi->controller_state; |
754ce4f2 | 344 | unsigned active = spi->mode & SPI_CS_HIGH; |
defbd3b4 DB |
345 | u32 mr; |
346 | ||
347 | /* only deactivate *this* device; sometimes transfers to | |
348 | * another device may be active when this routine is called. | |
349 | */ | |
350 | mr = spi_readl(as, MR); | |
351 | if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) { | |
352 | mr = SPI_BFINS(PCS, 0xf, mr); | |
353 | spi_writel(as, MR, mr); | |
354 | } | |
754ce4f2 | 355 | |
defbd3b4 | 356 | dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n", |
5ee36c98 | 357 | asd->npcs_pin, active ? " (low)" : "", |
defbd3b4 DB |
358 | mr); |
359 | ||
d4820b74 | 360 | if (atmel_spi_is_v2(as) || spi->chip_select != 0) |
5ee36c98 | 361 | gpio_set_value(asd->npcs_pin, !active); |
754ce4f2 HS |
362 | } |
363 | ||
6c07ef29 | 364 | static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock) |
8aad7924 NF |
365 | { |
366 | spin_lock_irqsave(&as->lock, as->flags); | |
367 | } | |
368 | ||
6c07ef29 | 369 | static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock) |
8aad7924 NF |
370 | { |
371 | spin_unlock_irqrestore(&as->lock, as->flags); | |
372 | } | |
373 | ||
1ccc404a NF |
374 | static inline bool atmel_spi_use_dma(struct atmel_spi *as, |
375 | struct spi_transfer *xfer) | |
376 | { | |
377 | return as->use_dma && xfer->len >= DMA_MIN_BYTES; | |
378 | } | |
379 | ||
1ccc404a NF |
380 | static int atmel_spi_dma_slave_config(struct atmel_spi *as, |
381 | struct dma_slave_config *slave_config, | |
382 | u8 bits_per_word) | |
383 | { | |
384 | int err = 0; | |
385 | ||
386 | if (bits_per_word > 8) { | |
387 | slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
388 | slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
389 | } else { | |
390 | slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
391 | slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
392 | } | |
393 | ||
394 | slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR; | |
395 | slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR; | |
396 | slave_config->src_maxburst = 1; | |
397 | slave_config->dst_maxburst = 1; | |
398 | slave_config->device_fc = false; | |
399 | ||
400 | slave_config->direction = DMA_MEM_TO_DEV; | |
401 | if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) { | |
402 | dev_err(&as->pdev->dev, | |
403 | "failed to configure tx dma channel\n"); | |
404 | err = -EINVAL; | |
405 | } | |
406 | ||
407 | slave_config->direction = DMA_DEV_TO_MEM; | |
408 | if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) { | |
409 | dev_err(&as->pdev->dev, | |
410 | "failed to configure rx dma channel\n"); | |
411 | err = -EINVAL; | |
412 | } | |
413 | ||
414 | return err; | |
415 | } | |
416 | ||
2f767a9f | 417 | static bool filter(struct dma_chan *chan, void *pdata) |
1ccc404a | 418 | { |
2f767a9f RG |
419 | struct atmel_spi_dma *sl_pdata = pdata; |
420 | struct at_dma_slave *sl; | |
1ccc404a | 421 | |
2f767a9f RG |
422 | if (!sl_pdata) |
423 | return false; | |
424 | ||
425 | sl = &sl_pdata->dma_slave; | |
1ccc404a NF |
426 | if (sl->dma_dev == chan->device->dev) { |
427 | chan->private = sl; | |
428 | return true; | |
429 | } else { | |
430 | return false; | |
431 | } | |
432 | } | |
433 | ||
434 | static int atmel_spi_configure_dma(struct atmel_spi *as) | |
435 | { | |
1ccc404a | 436 | struct dma_slave_config slave_config; |
2f767a9f | 437 | struct device *dev = &as->pdev->dev; |
1ccc404a NF |
438 | int err; |
439 | ||
2f767a9f RG |
440 | dma_cap_mask_t mask; |
441 | dma_cap_zero(mask); | |
442 | dma_cap_set(DMA_SLAVE, mask); | |
1ccc404a | 443 | |
2f767a9f RG |
444 | as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter, |
445 | &as->dma, | |
446 | dev, "tx"); | |
447 | if (!as->dma.chan_tx) { | |
448 | dev_err(dev, | |
449 | "DMA TX channel not available, SPI unable to use DMA\n"); | |
450 | err = -EBUSY; | |
451 | goto error; | |
1ccc404a | 452 | } |
2f767a9f RG |
453 | |
454 | as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter, | |
455 | &as->dma, | |
456 | dev, "rx"); | |
457 | ||
458 | if (!as->dma.chan_rx) { | |
459 | dev_err(dev, | |
460 | "DMA RX channel not available, SPI unable to use DMA\n"); | |
1ccc404a NF |
461 | err = -EBUSY; |
462 | goto error; | |
463 | } | |
464 | ||
465 | err = atmel_spi_dma_slave_config(as, &slave_config, 8); | |
466 | if (err) | |
467 | goto error; | |
468 | ||
469 | dev_info(&as->pdev->dev, | |
470 | "Using %s (tx) and %s (rx) for DMA transfers\n", | |
471 | dma_chan_name(as->dma.chan_tx), | |
472 | dma_chan_name(as->dma.chan_rx)); | |
473 | return 0; | |
474 | error: | |
475 | if (as->dma.chan_rx) | |
476 | dma_release_channel(as->dma.chan_rx); | |
477 | if (as->dma.chan_tx) | |
478 | dma_release_channel(as->dma.chan_tx); | |
479 | return err; | |
480 | } | |
481 | ||
482 | static void atmel_spi_stop_dma(struct atmel_spi *as) | |
483 | { | |
484 | if (as->dma.chan_rx) | |
485 | as->dma.chan_rx->device->device_control(as->dma.chan_rx, | |
486 | DMA_TERMINATE_ALL, 0); | |
487 | if (as->dma.chan_tx) | |
488 | as->dma.chan_tx->device->device_control(as->dma.chan_tx, | |
489 | DMA_TERMINATE_ALL, 0); | |
490 | } | |
491 | ||
492 | static void atmel_spi_release_dma(struct atmel_spi *as) | |
493 | { | |
494 | if (as->dma.chan_rx) | |
495 | dma_release_channel(as->dma.chan_rx); | |
496 | if (as->dma.chan_tx) | |
497 | dma_release_channel(as->dma.chan_tx); | |
498 | } | |
499 | ||
500 | /* This function is called by the DMA driver from tasklet context */ | |
501 | static void dma_callback(void *data) | |
502 | { | |
503 | struct spi_master *master = data; | |
504 | struct atmel_spi *as = spi_master_get_devdata(master); | |
505 | ||
8090d6d1 | 506 | complete(&as->xfer_completion); |
1ccc404a NF |
507 | } |
508 | ||
509 | /* | |
510 | * Next transfer using PIO. | |
1ccc404a NF |
511 | */ |
512 | static void atmel_spi_next_xfer_pio(struct spi_master *master, | |
513 | struct spi_transfer *xfer) | |
514 | { | |
515 | struct atmel_spi *as = spi_master_get_devdata(master); | |
8090d6d1 | 516 | unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; |
1ccc404a NF |
517 | |
518 | dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n"); | |
519 | ||
1ccc404a NF |
520 | /* Make sure data is not remaining in RDR */ |
521 | spi_readl(as, RDR); | |
522 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) { | |
523 | spi_readl(as, RDR); | |
524 | cpu_relax(); | |
525 | } | |
526 | ||
8090d6d1 | 527 | if (xfer->tx_buf) { |
f557c98b | 528 | if (xfer->bits_per_word > 8) |
8090d6d1 | 529 | spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); |
f557c98b | 530 | else |
8090d6d1 WY |
531 | spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos)); |
532 | } else { | |
1ccc404a | 533 | spi_writel(as, TDR, 0); |
8090d6d1 | 534 | } |
1ccc404a NF |
535 | |
536 | dev_dbg(master->dev.parent, | |
f557c98b RG |
537 | " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", |
538 | xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, | |
539 | xfer->bits_per_word); | |
1ccc404a NF |
540 | |
541 | /* Enable relevant interrupts */ | |
542 | spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES)); | |
543 | } | |
544 | ||
545 | /* | |
546 | * Submit next transfer for DMA. | |
1ccc404a NF |
547 | */ |
548 | static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, | |
549 | struct spi_transfer *xfer, | |
550 | u32 *plen) | |
551 | { | |
552 | struct atmel_spi *as = spi_master_get_devdata(master); | |
553 | struct dma_chan *rxchan = as->dma.chan_rx; | |
554 | struct dma_chan *txchan = as->dma.chan_tx; | |
555 | struct dma_async_tx_descriptor *rxdesc; | |
556 | struct dma_async_tx_descriptor *txdesc; | |
557 | struct dma_slave_config slave_config; | |
558 | dma_cookie_t cookie; | |
559 | u32 len = *plen; | |
560 | ||
561 | dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); | |
562 | ||
563 | /* Check that the channels are available */ | |
564 | if (!rxchan || !txchan) | |
565 | return -ENODEV; | |
566 | ||
567 | /* release lock for DMA operations */ | |
568 | atmel_spi_unlock(as); | |
569 | ||
570 | /* prepare the RX dma transfer */ | |
571 | sg_init_table(&as->dma.sgrx, 1); | |
572 | if (xfer->rx_buf) { | |
573 | as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen; | |
574 | } else { | |
575 | as->dma.sgrx.dma_address = as->buffer_dma; | |
576 | if (len > BUFFER_SIZE) | |
577 | len = BUFFER_SIZE; | |
578 | } | |
579 | ||
580 | /* prepare the TX dma transfer */ | |
581 | sg_init_table(&as->dma.sgtx, 1); | |
582 | if (xfer->tx_buf) { | |
583 | as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen; | |
584 | } else { | |
585 | as->dma.sgtx.dma_address = as->buffer_dma; | |
586 | if (len > BUFFER_SIZE) | |
587 | len = BUFFER_SIZE; | |
588 | memset(as->buffer, 0, len); | |
589 | } | |
590 | ||
591 | sg_dma_len(&as->dma.sgtx) = len; | |
592 | sg_dma_len(&as->dma.sgrx) = len; | |
593 | ||
594 | *plen = len; | |
595 | ||
596 | if (atmel_spi_dma_slave_config(as, &slave_config, 8)) | |
597 | goto err_exit; | |
598 | ||
599 | /* Send both scatterlists */ | |
600 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, | |
601 | &as->dma.sgrx, | |
602 | 1, | |
603 | DMA_FROM_DEVICE, | |
604 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK, | |
605 | NULL); | |
606 | if (!rxdesc) | |
607 | goto err_dma; | |
608 | ||
609 | txdesc = txchan->device->device_prep_slave_sg(txchan, | |
610 | &as->dma.sgtx, | |
611 | 1, | |
612 | DMA_TO_DEVICE, | |
613 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK, | |
614 | NULL); | |
615 | if (!txdesc) | |
616 | goto err_dma; | |
617 | ||
618 | dev_dbg(master->dev.parent, | |
2de024b7 EG |
619 | " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", |
620 | xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma, | |
621 | xfer->rx_buf, (unsigned long long)xfer->rx_dma); | |
1ccc404a NF |
622 | |
623 | /* Enable relevant interrupts */ | |
624 | spi_writel(as, IER, SPI_BIT(OVRES)); | |
625 | ||
626 | /* Put the callback on the RX transfer only, that should finish last */ | |
627 | rxdesc->callback = dma_callback; | |
628 | rxdesc->callback_param = master; | |
629 | ||
630 | /* Submit and fire RX and TX with TX last so we're ready to read! */ | |
631 | cookie = rxdesc->tx_submit(rxdesc); | |
632 | if (dma_submit_error(cookie)) | |
633 | goto err_dma; | |
634 | cookie = txdesc->tx_submit(txdesc); | |
635 | if (dma_submit_error(cookie)) | |
636 | goto err_dma; | |
637 | rxchan->device->device_issue_pending(rxchan); | |
638 | txchan->device->device_issue_pending(txchan); | |
639 | ||
640 | /* take back lock */ | |
641 | atmel_spi_lock(as); | |
642 | return 0; | |
643 | ||
644 | err_dma: | |
645 | spi_writel(as, IDR, SPI_BIT(OVRES)); | |
646 | atmel_spi_stop_dma(as); | |
647 | err_exit: | |
648 | atmel_spi_lock(as); | |
649 | return -ENOMEM; | |
650 | } | |
651 | ||
154443c7 SE |
652 | static void atmel_spi_next_xfer_data(struct spi_master *master, |
653 | struct spi_transfer *xfer, | |
654 | dma_addr_t *tx_dma, | |
655 | dma_addr_t *rx_dma, | |
656 | u32 *plen) | |
657 | { | |
658 | struct atmel_spi *as = spi_master_get_devdata(master); | |
659 | u32 len = *plen; | |
660 | ||
661 | /* use scratch buffer only when rx or tx data is unspecified */ | |
662 | if (xfer->rx_buf) | |
6aed4ee9 | 663 | *rx_dma = xfer->rx_dma + xfer->len - *plen; |
154443c7 SE |
664 | else { |
665 | *rx_dma = as->buffer_dma; | |
666 | if (len > BUFFER_SIZE) | |
667 | len = BUFFER_SIZE; | |
668 | } | |
1ccc404a | 669 | |
154443c7 | 670 | if (xfer->tx_buf) |
6aed4ee9 | 671 | *tx_dma = xfer->tx_dma + xfer->len - *plen; |
154443c7 SE |
672 | else { |
673 | *tx_dma = as->buffer_dma; | |
674 | if (len > BUFFER_SIZE) | |
675 | len = BUFFER_SIZE; | |
676 | memset(as->buffer, 0, len); | |
677 | dma_sync_single_for_device(&as->pdev->dev, | |
678 | as->buffer_dma, len, DMA_TO_DEVICE); | |
679 | } | |
680 | ||
681 | *plen = len; | |
682 | } | |
683 | ||
d3b72c7e RG |
684 | static int atmel_spi_set_xfer_speed(struct atmel_spi *as, |
685 | struct spi_device *spi, | |
686 | struct spi_transfer *xfer) | |
687 | { | |
688 | u32 scbr, csr; | |
689 | unsigned long bus_hz; | |
690 | ||
691 | /* v1 chips start out at half the peripheral bus speed. */ | |
692 | bus_hz = clk_get_rate(as->clk); | |
693 | if (!atmel_spi_is_v2(as)) | |
694 | bus_hz /= 2; | |
695 | ||
696 | /* | |
697 | * Calculate the lowest divider that satisfies the | |
698 | * constraint, assuming div32/fdiv/mbz == 0. | |
699 | */ | |
700 | if (xfer->speed_hz) | |
701 | scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz); | |
702 | else | |
703 | /* | |
704 | * This can happend if max_speed is null. | |
705 | * In this case, we set the lowest possible speed | |
706 | */ | |
707 | scbr = 0xff; | |
708 | ||
709 | /* | |
710 | * If the resulting divider doesn't fit into the | |
711 | * register bitfield, we can't satisfy the constraint. | |
712 | */ | |
713 | if (scbr >= (1 << SPI_SCBR_SIZE)) { | |
714 | dev_err(&spi->dev, | |
715 | "setup: %d Hz too slow, scbr %u; min %ld Hz\n", | |
716 | xfer->speed_hz, scbr, bus_hz/255); | |
717 | return -EINVAL; | |
718 | } | |
719 | if (scbr == 0) { | |
720 | dev_err(&spi->dev, | |
721 | "setup: %d Hz too high, scbr %u; max %ld Hz\n", | |
722 | xfer->speed_hz, scbr, bus_hz); | |
723 | return -EINVAL; | |
724 | } | |
725 | csr = spi_readl(as, CSR0 + 4 * spi->chip_select); | |
726 | csr = SPI_BFINS(SCBR, scbr, csr); | |
727 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
754ce4f2 | 732 | /* |
1ccc404a | 733 | * Submit next transfer for PDC. |
754ce4f2 HS |
734 | * lock is held, spi irq is blocked |
735 | */ | |
1ccc404a | 736 | static void atmel_spi_pdc_next_xfer(struct spi_master *master, |
8090d6d1 WY |
737 | struct spi_message *msg, |
738 | struct spi_transfer *xfer) | |
754ce4f2 HS |
739 | { |
740 | struct atmel_spi *as = spi_master_get_devdata(master); | |
8090d6d1 | 741 | u32 len; |
754ce4f2 HS |
742 | dma_addr_t tx_dma, rx_dma; |
743 | ||
8090d6d1 | 744 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
754ce4f2 | 745 | |
8090d6d1 WY |
746 | len = as->current_remaining_bytes; |
747 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); | |
748 | as->current_remaining_bytes -= len; | |
754ce4f2 | 749 | |
8090d6d1 WY |
750 | spi_writel(as, RPR, rx_dma); |
751 | spi_writel(as, TPR, tx_dma); | |
754ce4f2 | 752 | |
8090d6d1 WY |
753 | if (msg->spi->bits_per_word > 8) |
754 | len >>= 1; | |
755 | spi_writel(as, RCR, len); | |
756 | spi_writel(as, TCR, len); | |
754ce4f2 | 757 | |
8090d6d1 WY |
758 | dev_dbg(&msg->spi->dev, |
759 | " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", | |
760 | xfer, xfer->len, xfer->tx_buf, | |
761 | (unsigned long long)xfer->tx_dma, xfer->rx_buf, | |
762 | (unsigned long long)xfer->rx_dma); | |
dc329442 | 763 | |
8090d6d1 WY |
764 | if (as->current_remaining_bytes) { |
765 | len = as->current_remaining_bytes; | |
154443c7 | 766 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); |
8090d6d1 | 767 | as->current_remaining_bytes -= len; |
754ce4f2 | 768 | |
154443c7 SE |
769 | spi_writel(as, RNPR, rx_dma); |
770 | spi_writel(as, TNPR, tx_dma); | |
754ce4f2 | 771 | |
154443c7 SE |
772 | if (msg->spi->bits_per_word > 8) |
773 | len >>= 1; | |
774 | spi_writel(as, RNCR, len); | |
775 | spi_writel(as, TNCR, len); | |
8bacb219 HS |
776 | |
777 | dev_dbg(&msg->spi->dev, | |
2de024b7 EG |
778 | " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", |
779 | xfer, xfer->len, xfer->tx_buf, | |
780 | (unsigned long long)xfer->tx_dma, xfer->rx_buf, | |
781 | (unsigned long long)xfer->rx_dma); | |
154443c7 SE |
782 | } |
783 | ||
784 | /* REVISIT: We're waiting for ENDRX before we start the next | |
754ce4f2 HS |
785 | * transfer because we need to handle some difficult timing |
786 | * issues otherwise. If we wait for ENDTX in one transfer and | |
787 | * then starts waiting for ENDRX in the next, it's difficult | |
788 | * to tell the difference between the ENDRX interrupt we're | |
789 | * actually waiting for and the ENDRX interrupt of the | |
790 | * previous transfer. | |
791 | * | |
792 | * It should be doable, though. Just not now... | |
793 | */ | |
8090d6d1 | 794 | spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); |
754ce4f2 HS |
795 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); |
796 | } | |
797 | ||
8da0859a DB |
798 | /* |
799 | * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: | |
800 | * - The buffer is either valid for CPU access, else NULL | |
b595076a | 801 | * - If the buffer is valid, so is its DMA address |
8da0859a | 802 | * |
b595076a | 803 | * This driver manages the dma address unless message->is_dma_mapped. |
8da0859a DB |
804 | */ |
805 | static int | |
754ce4f2 HS |
806 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) |
807 | { | |
8da0859a DB |
808 | struct device *dev = &as->pdev->dev; |
809 | ||
754ce4f2 | 810 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; |
8da0859a | 811 | if (xfer->tx_buf) { |
214b574a JCPV |
812 | /* tx_buf is a const void* where we need a void * for the dma |
813 | * mapping */ | |
814 | void *nonconst_tx = (void *)xfer->tx_buf; | |
815 | ||
8da0859a | 816 | xfer->tx_dma = dma_map_single(dev, |
214b574a | 817 | nonconst_tx, xfer->len, |
754ce4f2 | 818 | DMA_TO_DEVICE); |
8d8bb39b | 819 | if (dma_mapping_error(dev, xfer->tx_dma)) |
8da0859a DB |
820 | return -ENOMEM; |
821 | } | |
822 | if (xfer->rx_buf) { | |
823 | xfer->rx_dma = dma_map_single(dev, | |
754ce4f2 HS |
824 | xfer->rx_buf, xfer->len, |
825 | DMA_FROM_DEVICE); | |
8d8bb39b | 826 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
8da0859a DB |
827 | if (xfer->tx_buf) |
828 | dma_unmap_single(dev, | |
829 | xfer->tx_dma, xfer->len, | |
830 | DMA_TO_DEVICE); | |
831 | return -ENOMEM; | |
832 | } | |
833 | } | |
834 | return 0; | |
754ce4f2 HS |
835 | } |
836 | ||
837 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, | |
838 | struct spi_transfer *xfer) | |
839 | { | |
840 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 841 | dma_unmap_single(master->dev.parent, xfer->tx_dma, |
754ce4f2 HS |
842 | xfer->len, DMA_TO_DEVICE); |
843 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 844 | dma_unmap_single(master->dev.parent, xfer->rx_dma, |
754ce4f2 HS |
845 | xfer->len, DMA_FROM_DEVICE); |
846 | } | |
847 | ||
1ccc404a NF |
848 | static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as) |
849 | { | |
850 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
851 | } | |
852 | ||
1ccc404a | 853 | /* Called from IRQ |
1ccc404a NF |
854 | * |
855 | * Must update "current_remaining_bytes" to keep track of data | |
856 | * to transfer. | |
857 | */ | |
858 | static void | |
859 | atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) | |
860 | { | |
1ccc404a | 861 | u8 *rxp; |
f557c98b | 862 | u16 *rxp16; |
1ccc404a NF |
863 | unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; |
864 | ||
865 | if (xfer->rx_buf) { | |
f557c98b RG |
866 | if (xfer->bits_per_word > 8) { |
867 | rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); | |
868 | *rxp16 = spi_readl(as, RDR); | |
869 | } else { | |
870 | rxp = ((u8 *)xfer->rx_buf) + xfer_pos; | |
871 | *rxp = spi_readl(as, RDR); | |
872 | } | |
1ccc404a NF |
873 | } else { |
874 | spi_readl(as, RDR); | |
875 | } | |
f557c98b RG |
876 | if (xfer->bits_per_word > 8) { |
877 | as->current_remaining_bytes -= 2; | |
878 | if (as->current_remaining_bytes < 0) | |
879 | as->current_remaining_bytes = 0; | |
880 | } else { | |
881 | as->current_remaining_bytes--; | |
882 | } | |
1ccc404a NF |
883 | } |
884 | ||
885 | /* Interrupt | |
886 | * | |
887 | * No need for locking in this Interrupt handler: done_status is the | |
8090d6d1 | 888 | * only information modified. |
1ccc404a NF |
889 | */ |
890 | static irqreturn_t | |
891 | atmel_spi_pio_interrupt(int irq, void *dev_id) | |
892 | { | |
893 | struct spi_master *master = dev_id; | |
894 | struct atmel_spi *as = spi_master_get_devdata(master); | |
895 | u32 status, pending, imr; | |
896 | struct spi_transfer *xfer; | |
897 | int ret = IRQ_NONE; | |
898 | ||
899 | imr = spi_readl(as, IMR); | |
900 | status = spi_readl(as, SR); | |
901 | pending = status & imr; | |
902 | ||
903 | if (pending & SPI_BIT(OVRES)) { | |
904 | ret = IRQ_HANDLED; | |
905 | spi_writel(as, IDR, SPI_BIT(OVRES)); | |
906 | dev_warn(master->dev.parent, "overrun\n"); | |
907 | ||
908 | /* | |
909 | * When we get an overrun, we disregard the current | |
910 | * transfer. Data will not be copied back from any | |
911 | * bounce buffer and msg->actual_len will not be | |
912 | * updated with the last xfer. | |
913 | * | |
914 | * We will also not process any remaning transfers in | |
915 | * the message. | |
1ccc404a NF |
916 | */ |
917 | as->done_status = -EIO; | |
918 | smp_wmb(); | |
919 | ||
920 | /* Clear any overrun happening while cleaning up */ | |
921 | spi_readl(as, SR); | |
922 | ||
8090d6d1 | 923 | complete(&as->xfer_completion); |
1ccc404a NF |
924 | |
925 | } else if (pending & SPI_BIT(RDRF)) { | |
926 | atmel_spi_lock(as); | |
927 | ||
928 | if (as->current_remaining_bytes) { | |
929 | ret = IRQ_HANDLED; | |
930 | xfer = as->current_transfer; | |
931 | atmel_spi_pump_pio_data(as, xfer); | |
8090d6d1 | 932 | if (!as->current_remaining_bytes) |
1ccc404a | 933 | spi_writel(as, IDR, pending); |
8090d6d1 WY |
934 | |
935 | complete(&as->xfer_completion); | |
1ccc404a NF |
936 | } |
937 | ||
938 | atmel_spi_unlock(as); | |
939 | } else { | |
940 | WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending); | |
941 | ret = IRQ_HANDLED; | |
942 | spi_writel(as, IDR, pending); | |
943 | } | |
944 | ||
945 | return ret; | |
754ce4f2 HS |
946 | } |
947 | ||
948 | static irqreturn_t | |
1ccc404a | 949 | atmel_spi_pdc_interrupt(int irq, void *dev_id) |
754ce4f2 HS |
950 | { |
951 | struct spi_master *master = dev_id; | |
952 | struct atmel_spi *as = spi_master_get_devdata(master); | |
754ce4f2 HS |
953 | u32 status, pending, imr; |
954 | int ret = IRQ_NONE; | |
955 | ||
754ce4f2 HS |
956 | imr = spi_readl(as, IMR); |
957 | status = spi_readl(as, SR); | |
958 | pending = status & imr; | |
959 | ||
960 | if (pending & SPI_BIT(OVRES)) { | |
754ce4f2 HS |
961 | |
962 | ret = IRQ_HANDLED; | |
963 | ||
dc329442 | 964 | spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) |
754ce4f2 HS |
965 | | SPI_BIT(OVRES))); |
966 | ||
754ce4f2 HS |
967 | /* Clear any overrun happening while cleaning up */ |
968 | spi_readl(as, SR); | |
969 | ||
823cd045 | 970 | as->done_status = -EIO; |
8090d6d1 WY |
971 | |
972 | complete(&as->xfer_completion); | |
973 | ||
dc329442 | 974 | } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { |
754ce4f2 HS |
975 | ret = IRQ_HANDLED; |
976 | ||
977 | spi_writel(as, IDR, pending); | |
978 | ||
8090d6d1 | 979 | complete(&as->xfer_completion); |
754ce4f2 HS |
980 | } |
981 | ||
754ce4f2 HS |
982 | return ret; |
983 | } | |
984 | ||
754ce4f2 HS |
985 | static int atmel_spi_setup(struct spi_device *spi) |
986 | { | |
987 | struct atmel_spi *as; | |
5ee36c98 | 988 | struct atmel_spi_device *asd; |
d3b72c7e | 989 | u32 csr; |
754ce4f2 | 990 | unsigned int bits = spi->bits_per_word; |
754ce4f2 HS |
991 | unsigned int npcs_pin; |
992 | int ret; | |
993 | ||
994 | as = spi_master_get_devdata(spi->master); | |
995 | ||
754ce4f2 HS |
996 | if (spi->chip_select > spi->master->num_chipselect) { |
997 | dev_dbg(&spi->dev, | |
998 | "setup: invalid chipselect %u (%u defined)\n", | |
999 | spi->chip_select, spi->master->num_chipselect); | |
1000 | return -EINVAL; | |
1001 | } | |
1002 | ||
defbd3b4 | 1003 | /* see notes above re chipselect */ |
d4820b74 | 1004 | if (!atmel_spi_is_v2(as) |
defbd3b4 DB |
1005 | && spi->chip_select == 0 |
1006 | && (spi->mode & SPI_CS_HIGH)) { | |
1007 | dev_dbg(&spi->dev, "setup: can't be active-high\n"); | |
1008 | return -EINVAL; | |
1009 | } | |
1010 | ||
d3b72c7e | 1011 | csr = SPI_BF(BITS, bits - 8); |
754ce4f2 HS |
1012 | if (spi->mode & SPI_CPOL) |
1013 | csr |= SPI_BIT(CPOL); | |
1014 | if (!(spi->mode & SPI_CPHA)) | |
1015 | csr |= SPI_BIT(NCPHA); | |
1016 | ||
1eed29df HS |
1017 | /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. |
1018 | * | |
1019 | * DLYBCT would add delays between words, slowing down transfers. | |
1020 | * It could potentially be useful to cope with DMA bottlenecks, but | |
1021 | * in those cases it's probably best to just use a lower bitrate. | |
1022 | */ | |
1023 | csr |= SPI_BF(DLYBS, 0); | |
1024 | csr |= SPI_BF(DLYBCT, 0); | |
754ce4f2 HS |
1025 | |
1026 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ | |
1027 | npcs_pin = (unsigned int)spi->controller_data; | |
850a5b67 JCPV |
1028 | |
1029 | if (gpio_is_valid(spi->cs_gpio)) | |
1030 | npcs_pin = spi->cs_gpio; | |
1031 | ||
5ee36c98 HS |
1032 | asd = spi->controller_state; |
1033 | if (!asd) { | |
1034 | asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); | |
1035 | if (!asd) | |
1036 | return -ENOMEM; | |
1037 | ||
6c7377ab | 1038 | ret = gpio_request(npcs_pin, dev_name(&spi->dev)); |
5ee36c98 HS |
1039 | if (ret) { |
1040 | kfree(asd); | |
754ce4f2 | 1041 | return ret; |
5ee36c98 HS |
1042 | } |
1043 | ||
1044 | asd->npcs_pin = npcs_pin; | |
1045 | spi->controller_state = asd; | |
28735a72 | 1046 | gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); |
754ce4f2 HS |
1047 | } |
1048 | ||
5ee36c98 HS |
1049 | asd->csr = csr; |
1050 | ||
754ce4f2 | 1051 | dev_dbg(&spi->dev, |
d3b72c7e RG |
1052 | "setup: bpw %u mode 0x%x -> csr%d %08x\n", |
1053 | bits, spi->mode, spi->chip_select, csr); | |
754ce4f2 | 1054 | |
d4820b74 | 1055 | if (!atmel_spi_is_v2(as)) |
5ee36c98 | 1056 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); |
754ce4f2 HS |
1057 | |
1058 | return 0; | |
1059 | } | |
1060 | ||
8090d6d1 WY |
1061 | static int atmel_spi_one_transfer(struct spi_master *master, |
1062 | struct spi_message *msg, | |
1063 | struct spi_transfer *xfer) | |
754ce4f2 HS |
1064 | { |
1065 | struct atmel_spi *as; | |
8090d6d1 | 1066 | struct spi_device *spi = msg->spi; |
b9d228f9 | 1067 | u8 bits; |
8090d6d1 | 1068 | u32 len; |
b9d228f9 | 1069 | struct atmel_spi_device *asd; |
8090d6d1 WY |
1070 | int timeout; |
1071 | int ret; | |
754ce4f2 | 1072 | |
8090d6d1 | 1073 | as = spi_master_get_devdata(master); |
754ce4f2 | 1074 | |
8090d6d1 WY |
1075 | if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { |
1076 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); | |
754ce4f2 | 1077 | return -EINVAL; |
8090d6d1 | 1078 | } |
754ce4f2 | 1079 | |
8090d6d1 WY |
1080 | if (xfer->bits_per_word) { |
1081 | asd = spi->controller_state; | |
1082 | bits = (asd->csr >> 4) & 0xf; | |
1083 | if (bits != xfer->bits_per_word - 8) { | |
1084 | dev_dbg(&spi->dev, | |
1085 | "you can't yet change bits_per_word in transfers\n"); | |
1086 | return -ENOPROTOOPT; | |
1087 | } | |
1088 | } | |
754ce4f2 | 1089 | |
8090d6d1 WY |
1090 | /* |
1091 | * DMA map early, for performance (empties dcache ASAP) and | |
1092 | * better fault reporting. | |
1093 | */ | |
1094 | if ((!msg->is_dma_mapped) | |
1095 | && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) { | |
1096 | if (atmel_spi_dma_map_xfer(as, xfer) < 0) | |
1097 | return -ENOMEM; | |
1098 | } | |
1099 | ||
1100 | atmel_spi_set_xfer_speed(as, msg->spi, xfer); | |
754ce4f2 | 1101 | |
8090d6d1 WY |
1102 | as->done_status = 0; |
1103 | as->current_transfer = xfer; | |
1104 | as->current_remaining_bytes = xfer->len; | |
1105 | while (as->current_remaining_bytes) { | |
1106 | reinit_completion(&as->xfer_completion); | |
1107 | ||
1108 | if (as->use_pdc) { | |
1109 | atmel_spi_pdc_next_xfer(master, msg, xfer); | |
1110 | } else if (atmel_spi_use_dma(as, xfer)) { | |
1111 | len = as->current_remaining_bytes; | |
1112 | ret = atmel_spi_next_xfer_dma_submit(master, | |
1113 | xfer, &len); | |
1114 | if (ret) { | |
1115 | dev_err(&spi->dev, | |
1116 | "unable to use DMA, fallback to PIO\n"); | |
1117 | atmel_spi_next_xfer_pio(master, xfer); | |
1118 | } else { | |
1119 | as->current_remaining_bytes -= len; | |
b9d228f9 | 1120 | } |
8090d6d1 WY |
1121 | } else { |
1122 | atmel_spi_next_xfer_pio(master, xfer); | |
b9d228f9 MB |
1123 | } |
1124 | ||
8090d6d1 WY |
1125 | ret = wait_for_completion_timeout(&as->xfer_completion, |
1126 | SPI_DMA_TIMEOUT); | |
1127 | if (WARN_ON(ret == 0)) { | |
1128 | dev_err(&spi->dev, | |
1129 | "spi trasfer timeout, err %d\n", ret); | |
1130 | as->done_status = -EIO; | |
1131 | } else { | |
1132 | ret = 0; | |
f557c98b RG |
1133 | } |
1134 | ||
8090d6d1 WY |
1135 | if (as->done_status) |
1136 | break; | |
1137 | } | |
1138 | ||
1139 | if (as->done_status) { | |
1140 | if (as->use_pdc) { | |
1141 | dev_warn(master->dev.parent, | |
1142 | "overrun (%u/%u remaining)\n", | |
1143 | spi_readl(as, TCR), spi_readl(as, RCR)); | |
1144 | ||
1145 | /* | |
1146 | * Clean up DMA registers and make sure the data | |
1147 | * registers are empty. | |
1148 | */ | |
1149 | spi_writel(as, RNCR, 0); | |
1150 | spi_writel(as, TNCR, 0); | |
1151 | spi_writel(as, RCR, 0); | |
1152 | spi_writel(as, TCR, 0); | |
1153 | for (timeout = 1000; timeout; timeout--) | |
1154 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) | |
1155 | break; | |
1156 | if (!timeout) | |
1157 | dev_warn(master->dev.parent, | |
1158 | "timeout waiting for TXEMPTY"); | |
1159 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) | |
1160 | spi_readl(as, RDR); | |
1161 | ||
1162 | /* Clear any overrun happening while cleaning up */ | |
1163 | spi_readl(as, SR); | |
1164 | ||
1165 | } else if (atmel_spi_use_dma(as, xfer)) { | |
1166 | atmel_spi_stop_dma(as); | |
1167 | } | |
1168 | ||
1169 | if (!msg->is_dma_mapped | |
1170 | && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) | |
1171 | atmel_spi_dma_unmap_xfer(master, xfer); | |
1172 | ||
1173 | return 0; | |
1174 | ||
1175 | } else { | |
1176 | /* only update length if no error */ | |
1177 | msg->actual_length += xfer->len; | |
1178 | } | |
1179 | ||
1180 | if (!msg->is_dma_mapped | |
1181 | && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) | |
1182 | atmel_spi_dma_unmap_xfer(master, xfer); | |
1183 | ||
1184 | if (xfer->delay_usecs) | |
1185 | udelay(xfer->delay_usecs); | |
1186 | ||
1187 | if (xfer->cs_change) { | |
1188 | if (list_is_last(&xfer->transfer_list, | |
1189 | &msg->transfers)) { | |
1190 | as->keep_cs = true; | |
1191 | } else { | |
1192 | as->cs_active = !as->cs_active; | |
1193 | if (as->cs_active) | |
1194 | cs_activate(as, msg->spi); | |
1195 | else | |
1196 | cs_deactivate(as, msg->spi); | |
8da0859a | 1197 | } |
754ce4f2 HS |
1198 | } |
1199 | ||
8090d6d1 WY |
1200 | return 0; |
1201 | } | |
1202 | ||
1203 | static int atmel_spi_transfer_one_message(struct spi_master *master, | |
1204 | struct spi_message *msg) | |
1205 | { | |
1206 | struct atmel_spi *as; | |
1207 | struct spi_transfer *xfer; | |
1208 | struct spi_device *spi = msg->spi; | |
1209 | int ret = 0; | |
1210 | ||
1211 | as = spi_master_get_devdata(master); | |
1212 | ||
1213 | dev_dbg(&spi->dev, "new message %p submitted for %s\n", | |
1214 | msg, dev_name(&spi->dev)); | |
1215 | ||
8090d6d1 WY |
1216 | atmel_spi_lock(as); |
1217 | cs_activate(as, spi); | |
1218 | ||
1219 | as->cs_active = true; | |
1220 | as->keep_cs = false; | |
1221 | ||
1222 | msg->status = 0; | |
1223 | msg->actual_length = 0; | |
1224 | ||
1225 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
1226 | ret = atmel_spi_one_transfer(master, msg, xfer); | |
1227 | if (ret) | |
1228 | goto msg_done; | |
1229 | } | |
1230 | ||
1231 | if (as->use_pdc) | |
1232 | atmel_spi_disable_pdc_transfer(as); | |
1233 | ||
754ce4f2 | 1234 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
8090d6d1 | 1235 | dev_dbg(&spi->dev, |
754ce4f2 HS |
1236 | " xfer %p: len %u tx %p/%08x rx %p/%08x\n", |
1237 | xfer, xfer->len, | |
1238 | xfer->tx_buf, xfer->tx_dma, | |
1239 | xfer->rx_buf, xfer->rx_dma); | |
1240 | } | |
1241 | ||
8090d6d1 WY |
1242 | msg_done: |
1243 | if (!as->keep_cs) | |
1244 | cs_deactivate(as, msg->spi); | |
754ce4f2 | 1245 | |
8aad7924 | 1246 | atmel_spi_unlock(as); |
754ce4f2 | 1247 | |
8090d6d1 WY |
1248 | msg->status = as->done_status; |
1249 | spi_finalize_current_message(spi->master); | |
1250 | ||
1251 | return ret; | |
754ce4f2 HS |
1252 | } |
1253 | ||
bb2d1c36 | 1254 | static void atmel_spi_cleanup(struct spi_device *spi) |
754ce4f2 | 1255 | { |
5ee36c98 | 1256 | struct atmel_spi_device *asd = spi->controller_state; |
defbd3b4 | 1257 | unsigned gpio = (unsigned) spi->controller_data; |
defbd3b4 | 1258 | |
5ee36c98 | 1259 | if (!asd) |
defbd3b4 DB |
1260 | return; |
1261 | ||
5ee36c98 | 1262 | spi->controller_state = NULL; |
defbd3b4 | 1263 | gpio_free(gpio); |
5ee36c98 | 1264 | kfree(asd); |
754ce4f2 HS |
1265 | } |
1266 | ||
d4820b74 WY |
1267 | static inline unsigned int atmel_get_version(struct atmel_spi *as) |
1268 | { | |
1269 | return spi_readl(as, VERSION) & 0x00000fff; | |
1270 | } | |
1271 | ||
1272 | static void atmel_get_caps(struct atmel_spi *as) | |
1273 | { | |
1274 | unsigned int version; | |
1275 | ||
1276 | version = atmel_get_version(as); | |
1277 | dev_info(&as->pdev->dev, "version: 0x%x\n", version); | |
1278 | ||
1279 | as->caps.is_spi2 = version > 0x121; | |
1280 | as->caps.has_wdrbt = version >= 0x210; | |
1281 | as->caps.has_dma_support = version >= 0x212; | |
1282 | } | |
1283 | ||
754ce4f2 HS |
1284 | /*-------------------------------------------------------------------------*/ |
1285 | ||
fd4a319b | 1286 | static int atmel_spi_probe(struct platform_device *pdev) |
754ce4f2 HS |
1287 | { |
1288 | struct resource *regs; | |
1289 | int irq; | |
1290 | struct clk *clk; | |
1291 | int ret; | |
1292 | struct spi_master *master; | |
1293 | struct atmel_spi *as; | |
1294 | ||
1295 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1296 | if (!regs) | |
1297 | return -ENXIO; | |
1298 | ||
1299 | irq = platform_get_irq(pdev, 0); | |
1300 | if (irq < 0) | |
1301 | return irq; | |
1302 | ||
9f87d6f2 | 1303 | clk = devm_clk_get(&pdev->dev, "spi_clk"); |
754ce4f2 HS |
1304 | if (IS_ERR(clk)) |
1305 | return PTR_ERR(clk); | |
1306 | ||
1307 | /* setup spi core then atmel-specific driver state */ | |
1308 | ret = -ENOMEM; | |
a536d765 | 1309 | master = spi_alloc_master(&pdev->dev, sizeof(*as)); |
754ce4f2 HS |
1310 | if (!master) |
1311 | goto out_free; | |
1312 | ||
e7db06b5 DB |
1313 | /* the spi->mode bits understood by this driver: */ |
1314 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1315 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); |
850a5b67 | 1316 | master->dev.of_node = pdev->dev.of_node; |
754ce4f2 | 1317 | master->bus_num = pdev->id; |
850a5b67 | 1318 | master->num_chipselect = master->dev.of_node ? 0 : 4; |
754ce4f2 | 1319 | master->setup = atmel_spi_setup; |
8090d6d1 | 1320 | master->transfer_one_message = atmel_spi_transfer_one_message; |
754ce4f2 HS |
1321 | master->cleanup = atmel_spi_cleanup; |
1322 | platform_set_drvdata(pdev, master); | |
1323 | ||
1324 | as = spi_master_get_devdata(master); | |
1325 | ||
8da0859a DB |
1326 | /* |
1327 | * Scratch buffer is used for throwaway rx and tx data. | |
1328 | * It's coherent to minimize dcache pollution. | |
1329 | */ | |
754ce4f2 HS |
1330 | as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, |
1331 | &as->buffer_dma, GFP_KERNEL); | |
1332 | if (!as->buffer) | |
1333 | goto out_free; | |
1334 | ||
1335 | spin_lock_init(&as->lock); | |
1ccc404a | 1336 | |
754ce4f2 | 1337 | as->pdev = pdev; |
31407478 | 1338 | as->regs = devm_ioremap_resource(&pdev->dev, regs); |
543c954d WY |
1339 | if (IS_ERR(as->regs)) { |
1340 | ret = PTR_ERR(as->regs); | |
754ce4f2 | 1341 | goto out_free_buffer; |
543c954d | 1342 | } |
dfab30ee | 1343 | as->phybase = regs->start; |
754ce4f2 HS |
1344 | as->irq = irq; |
1345 | as->clk = clk; | |
754ce4f2 | 1346 | |
8090d6d1 WY |
1347 | init_completion(&as->xfer_completion); |
1348 | ||
d4820b74 WY |
1349 | atmel_get_caps(as); |
1350 | ||
1ccc404a NF |
1351 | as->use_dma = false; |
1352 | as->use_pdc = false; | |
1353 | if (as->caps.has_dma_support) { | |
1354 | if (atmel_spi_configure_dma(as) == 0) | |
1355 | as->use_dma = true; | |
1356 | } else { | |
1357 | as->use_pdc = true; | |
1358 | } | |
1359 | ||
1360 | if (as->caps.has_dma_support && !as->use_dma) | |
1361 | dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); | |
1362 | ||
1363 | if (as->use_pdc) { | |
9f87d6f2 JH |
1364 | ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt, |
1365 | 0, dev_name(&pdev->dev), master); | |
1ccc404a | 1366 | } else { |
9f87d6f2 JH |
1367 | ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt, |
1368 | 0, dev_name(&pdev->dev), master); | |
1ccc404a | 1369 | } |
754ce4f2 HS |
1370 | if (ret) |
1371 | goto out_unmap_regs; | |
1372 | ||
1373 | /* Initialize the hardware */ | |
dfec4a6e BB |
1374 | ret = clk_prepare_enable(clk); |
1375 | if (ret) | |
de8cc234 | 1376 | goto out_free_irq; |
754ce4f2 | 1377 | spi_writel(as, CR, SPI_BIT(SWRST)); |
50d7d5bf | 1378 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
d4820b74 WY |
1379 | if (as->caps.has_wdrbt) { |
1380 | spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) | |
1381 | | SPI_BIT(MSTR)); | |
1382 | } else { | |
1383 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); | |
1384 | } | |
1ccc404a NF |
1385 | |
1386 | if (as->use_pdc) | |
1387 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
754ce4f2 HS |
1388 | spi_writel(as, CR, SPI_BIT(SPIEN)); |
1389 | ||
1390 | /* go! */ | |
1391 | dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", | |
1392 | (unsigned long)regs->start, irq); | |
1393 | ||
9f87d6f2 | 1394 | ret = devm_spi_register_master(&pdev->dev, master); |
754ce4f2 | 1395 | if (ret) |
1ccc404a | 1396 | goto out_free_dma; |
754ce4f2 HS |
1397 | |
1398 | return 0; | |
1399 | ||
1ccc404a NF |
1400 | out_free_dma: |
1401 | if (as->use_dma) | |
1402 | atmel_spi_release_dma(as); | |
1403 | ||
754ce4f2 | 1404 | spi_writel(as, CR, SPI_BIT(SWRST)); |
50d7d5bf | 1405 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
dfec4a6e | 1406 | clk_disable_unprepare(clk); |
de8cc234 | 1407 | out_free_irq: |
754ce4f2 | 1408 | out_unmap_regs: |
754ce4f2 HS |
1409 | out_free_buffer: |
1410 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
1411 | as->buffer_dma); | |
1412 | out_free: | |
754ce4f2 HS |
1413 | spi_master_put(master); |
1414 | return ret; | |
1415 | } | |
1416 | ||
fd4a319b | 1417 | static int atmel_spi_remove(struct platform_device *pdev) |
754ce4f2 HS |
1418 | { |
1419 | struct spi_master *master = platform_get_drvdata(pdev); | |
1420 | struct atmel_spi *as = spi_master_get_devdata(master); | |
754ce4f2 HS |
1421 | |
1422 | /* reset the hardware and block queue progress */ | |
1423 | spin_lock_irq(&as->lock); | |
1ccc404a NF |
1424 | if (as->use_dma) { |
1425 | atmel_spi_stop_dma(as); | |
1426 | atmel_spi_release_dma(as); | |
1427 | } | |
1428 | ||
754ce4f2 | 1429 | spi_writel(as, CR, SPI_BIT(SWRST)); |
50d7d5bf | 1430 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
1431 | spi_readl(as, SR); |
1432 | spin_unlock_irq(&as->lock); | |
1433 | ||
754ce4f2 HS |
1434 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, |
1435 | as->buffer_dma); | |
1436 | ||
dfec4a6e | 1437 | clk_disable_unprepare(as->clk); |
754ce4f2 HS |
1438 | |
1439 | return 0; | |
1440 | } | |
1441 | ||
ec60dd37 JH |
1442 | #ifdef CONFIG_PM_SLEEP |
1443 | static int atmel_spi_suspend(struct device *dev) | |
754ce4f2 | 1444 | { |
ec60dd37 | 1445 | struct spi_master *master = dev_get_drvdata(dev); |
754ce4f2 HS |
1446 | struct atmel_spi *as = spi_master_get_devdata(master); |
1447 | ||
dfec4a6e | 1448 | clk_disable_unprepare(as->clk); |
754ce4f2 HS |
1449 | return 0; |
1450 | } | |
1451 | ||
ec60dd37 | 1452 | static int atmel_spi_resume(struct device *dev) |
754ce4f2 | 1453 | { |
ec60dd37 | 1454 | struct spi_master *master = dev_get_drvdata(dev); |
754ce4f2 HS |
1455 | struct atmel_spi *as = spi_master_get_devdata(master); |
1456 | ||
ec60dd37 | 1457 | clk_prepare_enable(as->clk); |
754ce4f2 HS |
1458 | return 0; |
1459 | } | |
1460 | ||
ec60dd37 JH |
1461 | static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume); |
1462 | ||
1463 | #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops) | |
754ce4f2 | 1464 | #else |
ec60dd37 | 1465 | #define ATMEL_SPI_PM_OPS NULL |
754ce4f2 HS |
1466 | #endif |
1467 | ||
850a5b67 JCPV |
1468 | #if defined(CONFIG_OF) |
1469 | static const struct of_device_id atmel_spi_dt_ids[] = { | |
1470 | { .compatible = "atmel,at91rm9200-spi" }, | |
1471 | { /* sentinel */ } | |
1472 | }; | |
1473 | ||
1474 | MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); | |
1475 | #endif | |
754ce4f2 HS |
1476 | |
1477 | static struct platform_driver atmel_spi_driver = { | |
1478 | .driver = { | |
1479 | .name = "atmel_spi", | |
1480 | .owner = THIS_MODULE, | |
ec60dd37 | 1481 | .pm = ATMEL_SPI_PM_OPS, |
850a5b67 | 1482 | .of_match_table = of_match_ptr(atmel_spi_dt_ids), |
754ce4f2 | 1483 | }, |
1cb201af | 1484 | .probe = atmel_spi_probe, |
2deff8d6 | 1485 | .remove = atmel_spi_remove, |
754ce4f2 | 1486 | }; |
940ab889 | 1487 | module_platform_driver(atmel_spi_driver); |
754ce4f2 HS |
1488 | |
1489 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | |
e05503ef | 1490 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
754ce4f2 | 1491 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 1492 | MODULE_ALIAS("platform:atmel_spi"); |