Commit | Line | Data |
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f8043872 CB |
1 | /* |
2 | * Driver for Broadcom BCM2835 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2012 Chris Boot | |
5 | * Copyright (C) 2013 Stephen Warren | |
e34ff011 | 6 | * Copyright (C) 2015 Martin Sperl |
f8043872 CB |
7 | * |
8 | * This driver is inspired by: | |
9 | * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> | |
10 | * spi-atmel.c, Copyright (C) 2006 Atmel Corporation | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
f8043872 CB |
21 | */ |
22 | ||
23 | #include <linux/clk.h> | |
24 | #include <linux/completion.h> | |
25 | #include <linux/delay.h> | |
3ecd37ed MS |
26 | #include <linux/dma-mapping.h> |
27 | #include <linux/dmaengine.h> | |
f8043872 CB |
28 | #include <linux/err.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/of.h> | |
3ecd37ed | 34 | #include <linux/of_address.h> |
f8043872 | 35 | #include <linux/of_device.h> |
3ecd37ed MS |
36 | #include <linux/of_gpio.h> |
37 | #include <linux/of_irq.h> | |
f8043872 CB |
38 | #include <linux/spi/spi.h> |
39 | ||
40 | /* SPI register offsets */ | |
41 | #define BCM2835_SPI_CS 0x00 | |
42 | #define BCM2835_SPI_FIFO 0x04 | |
43 | #define BCM2835_SPI_CLK 0x08 | |
44 | #define BCM2835_SPI_DLEN 0x0c | |
45 | #define BCM2835_SPI_LTOH 0x10 | |
46 | #define BCM2835_SPI_DC 0x14 | |
47 | ||
48 | /* Bitfields in CS */ | |
49 | #define BCM2835_SPI_CS_LEN_LONG 0x02000000 | |
50 | #define BCM2835_SPI_CS_DMA_LEN 0x01000000 | |
51 | #define BCM2835_SPI_CS_CSPOL2 0x00800000 | |
52 | #define BCM2835_SPI_CS_CSPOL1 0x00400000 | |
53 | #define BCM2835_SPI_CS_CSPOL0 0x00200000 | |
54 | #define BCM2835_SPI_CS_RXF 0x00100000 | |
55 | #define BCM2835_SPI_CS_RXR 0x00080000 | |
56 | #define BCM2835_SPI_CS_TXD 0x00040000 | |
57 | #define BCM2835_SPI_CS_RXD 0x00020000 | |
58 | #define BCM2835_SPI_CS_DONE 0x00010000 | |
59 | #define BCM2835_SPI_CS_LEN 0x00002000 | |
60 | #define BCM2835_SPI_CS_REN 0x00001000 | |
61 | #define BCM2835_SPI_CS_ADCS 0x00000800 | |
62 | #define BCM2835_SPI_CS_INTR 0x00000400 | |
63 | #define BCM2835_SPI_CS_INTD 0x00000200 | |
64 | #define BCM2835_SPI_CS_DMAEN 0x00000100 | |
65 | #define BCM2835_SPI_CS_TA 0x00000080 | |
66 | #define BCM2835_SPI_CS_CSPOL 0x00000040 | |
67 | #define BCM2835_SPI_CS_CLEAR_RX 0x00000020 | |
68 | #define BCM2835_SPI_CS_CLEAR_TX 0x00000010 | |
69 | #define BCM2835_SPI_CS_CPOL 0x00000008 | |
70 | #define BCM2835_SPI_CS_CPHA 0x00000004 | |
71 | #define BCM2835_SPI_CS_CS_10 0x00000002 | |
72 | #define BCM2835_SPI_CS_CS_01 0x00000001 | |
73 | ||
704f32d4 | 74 | #define BCM2835_SPI_POLLING_LIMIT_US 30 |
a750b124 | 75 | #define BCM2835_SPI_POLLING_JIFFIES 2 |
3ecd37ed | 76 | #define BCM2835_SPI_DMA_MIN_LENGTH 96 |
6935224d MS |
77 | #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
78 | | SPI_NO_CS | SPI_3WIRE) | |
f8043872 CB |
79 | |
80 | #define DRV_NAME "spi-bcm2835" | |
81 | ||
82 | struct bcm2835_spi { | |
83 | void __iomem *regs; | |
84 | struct clk *clk; | |
85 | int irq; | |
f8043872 CB |
86 | const u8 *tx_buf; |
87 | u8 *rx_buf; | |
e34ff011 MS |
88 | int tx_len; |
89 | int rx_len; | |
3ecd37ed | 90 | bool dma_pending; |
f8043872 CB |
91 | }; |
92 | ||
93 | static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) | |
94 | { | |
95 | return readl(bs->regs + reg); | |
96 | } | |
97 | ||
98 | static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) | |
99 | { | |
100 | writel(val, bs->regs + reg); | |
101 | } | |
102 | ||
4adf3129 | 103 | static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
104 | { |
105 | u8 byte; | |
106 | ||
e34ff011 MS |
107 | while ((bs->rx_len) && |
108 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) { | |
f8043872 CB |
109 | byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); |
110 | if (bs->rx_buf) | |
111 | *bs->rx_buf++ = byte; | |
e34ff011 | 112 | bs->rx_len--; |
f8043872 CB |
113 | } |
114 | } | |
115 | ||
4adf3129 | 116 | static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) |
f8043872 CB |
117 | { |
118 | u8 byte; | |
119 | ||
e34ff011 | 120 | while ((bs->tx_len) && |
4adf3129 | 121 | (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) { |
f8043872 CB |
122 | byte = bs->tx_buf ? *bs->tx_buf++ : 0; |
123 | bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); | |
e34ff011 | 124 | bs->tx_len--; |
f8043872 CB |
125 | } |
126 | } | |
127 | ||
e34ff011 MS |
128 | static void bcm2835_spi_reset_hw(struct spi_master *master) |
129 | { | |
130 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
131 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); | |
132 | ||
133 | /* Disable SPI interrupts and transfer */ | |
134 | cs &= ~(BCM2835_SPI_CS_INTR | | |
135 | BCM2835_SPI_CS_INTD | | |
3ecd37ed | 136 | BCM2835_SPI_CS_DMAEN | |
e34ff011 MS |
137 | BCM2835_SPI_CS_TA); |
138 | /* and reset RX/TX FIFOS */ | |
139 | cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; | |
140 | ||
141 | /* and reset the SPI_HW */ | |
142 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
3ecd37ed MS |
143 | /* as well as DLEN */ |
144 | bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); | |
e34ff011 MS |
145 | } |
146 | ||
f8043872 CB |
147 | static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) |
148 | { | |
149 | struct spi_master *master = dev_id; | |
150 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
f8043872 | 151 | |
4adf3129 MS |
152 | /* Read as many bytes as possible from FIFO */ |
153 | bcm2835_rd_fifo(bs); | |
e34ff011 MS |
154 | /* Write as many bytes as possible to FIFO */ |
155 | bcm2835_wr_fifo(bs); | |
156 | ||
157 | /* based on flags decide if we can finish the transfer */ | |
158 | if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) { | |
159 | /* Transfer complete - reset SPI HW */ | |
160 | bcm2835_spi_reset_hw(master); | |
161 | /* wake up the framework */ | |
162 | complete(&master->xfer_completion); | |
f8043872 CB |
163 | } |
164 | ||
4adf3129 | 165 | return IRQ_HANDLED; |
f8043872 CB |
166 | } |
167 | ||
704f32d4 MS |
168 | static int bcm2835_spi_transfer_one_irq(struct spi_master *master, |
169 | struct spi_device *spi, | |
170 | struct spi_transfer *tfr, | |
171 | u32 cs) | |
172 | { | |
173 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
174 | ||
175 | /* fill in fifo if we have gpio-cs | |
176 | * note that there have been rare events where the native-CS | |
177 | * flapped for <1us which may change the behaviour | |
178 | * with gpio-cs this does not happen, so it is implemented | |
179 | * only for this case | |
180 | */ | |
181 | if (gpio_is_valid(spi->cs_gpio)) { | |
182 | /* enable HW block, but without interrupts enabled | |
183 | * this would triggern an immediate interrupt | |
184 | */ | |
185 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
186 | cs | BCM2835_SPI_CS_TA); | |
187 | /* fill in tx fifo as much as possible */ | |
188 | bcm2835_wr_fifo(bs); | |
189 | } | |
190 | ||
191 | /* | |
192 | * Enable the HW block. This will immediately trigger a DONE (TX | |
193 | * empty) interrupt, upon which we will fill the TX FIFO with the | |
194 | * first TX bytes. Pre-filling the TX FIFO here to avoid the | |
195 | * interrupt doesn't work:-( | |
196 | */ | |
197 | cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; | |
198 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
199 | ||
200 | /* signal that we need to wait for completion */ | |
201 | return 1; | |
202 | } | |
203 | ||
3ecd37ed MS |
204 | /* |
205 | * DMA support | |
206 | * | |
207 | * this implementation has currently a few issues in so far as it does | |
208 | * not work arrount limitations of the HW. | |
209 | * | |
210 | * the main one being that DMA transfers are limited to 16 bit | |
211 | * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN | |
212 | * | |
213 | * also we currently assume that the scatter-gather fragments are | |
214 | * all multiple of 4 (except the last) - otherwise we would need | |
215 | * to reset the FIFO before subsequent transfers... | |
216 | * this also means that tx/rx transfers sg's need to be of equal size! | |
217 | * | |
218 | * there may be a few more border-cases we may need to address as well | |
219 | * but unfortunately this would mean splitting up the scatter-gather | |
220 | * list making it slightly unpractical... | |
221 | */ | |
222 | static void bcm2835_spi_dma_done(void *data) | |
223 | { | |
224 | struct spi_master *master = data; | |
225 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
226 | ||
227 | /* reset fifo and HW */ | |
228 | bcm2835_spi_reset_hw(master); | |
229 | ||
230 | /* and terminate tx-dma as we do not have an irq for it | |
231 | * because when the rx dma will terminate and this callback | |
232 | * is called the tx-dma must have finished - can't get to this | |
233 | * situation otherwise... | |
234 | */ | |
235 | dmaengine_terminate_all(master->dma_tx); | |
236 | ||
237 | /* mark as no longer pending */ | |
238 | bs->dma_pending = 0; | |
239 | ||
240 | /* and mark as completed */; | |
241 | complete(&master->xfer_completion); | |
242 | } | |
243 | ||
244 | static int bcm2835_spi_prepare_sg(struct spi_master *master, | |
245 | struct spi_transfer *tfr, | |
246 | bool is_tx) | |
247 | { | |
248 | struct dma_chan *chan; | |
249 | struct scatterlist *sgl; | |
250 | unsigned int nents; | |
251 | enum dma_transfer_direction dir; | |
252 | unsigned long flags; | |
253 | ||
254 | struct dma_async_tx_descriptor *desc; | |
255 | dma_cookie_t cookie; | |
256 | ||
257 | if (is_tx) { | |
258 | dir = DMA_MEM_TO_DEV; | |
259 | chan = master->dma_tx; | |
260 | nents = tfr->tx_sg.nents; | |
261 | sgl = tfr->tx_sg.sgl; | |
262 | flags = 0 /* no tx interrupt */; | |
263 | ||
264 | } else { | |
265 | dir = DMA_DEV_TO_MEM; | |
266 | chan = master->dma_rx; | |
267 | nents = tfr->rx_sg.nents; | |
268 | sgl = tfr->rx_sg.sgl; | |
269 | flags = DMA_PREP_INTERRUPT; | |
270 | } | |
271 | /* prepare the channel */ | |
272 | desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); | |
273 | if (!desc) | |
274 | return -EINVAL; | |
275 | ||
276 | /* set callback for rx */ | |
277 | if (!is_tx) { | |
278 | desc->callback = bcm2835_spi_dma_done; | |
279 | desc->callback_param = master; | |
280 | } | |
281 | ||
282 | /* submit it to DMA-engine */ | |
283 | cookie = dmaengine_submit(desc); | |
284 | ||
285 | return dma_submit_error(cookie); | |
286 | } | |
287 | ||
288 | static inline int bcm2835_check_sg_length(struct sg_table *sgt) | |
289 | { | |
290 | int i; | |
291 | struct scatterlist *sgl; | |
292 | ||
293 | /* check that the sg entries are word-sized (except for last) */ | |
294 | for_each_sg(sgt->sgl, sgl, (int)sgt->nents - 1, i) { | |
295 | if (sg_dma_len(sgl) % 4) | |
296 | return -EFAULT; | |
297 | } | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | static int bcm2835_spi_transfer_one_dma(struct spi_master *master, | |
303 | struct spi_device *spi, | |
304 | struct spi_transfer *tfr, | |
305 | u32 cs) | |
306 | { | |
307 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
308 | int ret; | |
309 | ||
310 | /* check that the scatter gather segments are all a multiple of 4 */ | |
311 | if (bcm2835_check_sg_length(&tfr->tx_sg) || | |
312 | bcm2835_check_sg_length(&tfr->rx_sg)) { | |
313 | dev_warn_once(&spi->dev, | |
314 | "scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n"); | |
315 | return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); | |
316 | } | |
317 | ||
318 | /* setup tx-DMA */ | |
319 | ret = bcm2835_spi_prepare_sg(master, tfr, true); | |
320 | if (ret) | |
321 | return ret; | |
322 | ||
323 | /* start TX early */ | |
324 | dma_async_issue_pending(master->dma_tx); | |
325 | ||
326 | /* mark as dma pending */ | |
327 | bs->dma_pending = 1; | |
328 | ||
329 | /* set the DMA length */ | |
330 | bcm2835_wr(bs, BCM2835_SPI_DLEN, tfr->len); | |
331 | ||
332 | /* start the HW */ | |
333 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
334 | cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); | |
335 | ||
336 | /* setup rx-DMA late - to run transfers while | |
337 | * mapping of the rx buffers still takes place | |
338 | * this saves 10us or more. | |
339 | */ | |
340 | ret = bcm2835_spi_prepare_sg(master, tfr, false); | |
341 | if (ret) { | |
342 | /* need to reset on errors */ | |
343 | dmaengine_terminate_all(master->dma_tx); | |
344 | bcm2835_spi_reset_hw(master); | |
345 | return ret; | |
346 | } | |
347 | ||
348 | /* start rx dma late */ | |
349 | dma_async_issue_pending(master->dma_rx); | |
350 | ||
351 | /* wait for wakeup in framework */ | |
352 | return 1; | |
353 | } | |
354 | ||
355 | static bool bcm2835_spi_can_dma(struct spi_master *master, | |
356 | struct spi_device *spi, | |
357 | struct spi_transfer *tfr) | |
358 | { | |
359 | /* only run for gpio_cs */ | |
360 | if (!gpio_is_valid(spi->cs_gpio)) | |
361 | return false; | |
362 | ||
363 | /* we start DMA efforts only on bigger transfers */ | |
364 | if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) | |
365 | return false; | |
366 | ||
367 | /* BCM2835_SPI_DLEN has defined a max transfer size as | |
368 | * 16 bit, so max is 65535 | |
369 | * we can revisit this by using an alternative transfer | |
370 | * method - ideally this would get done without any more | |
371 | * interaction... | |
372 | */ | |
373 | if (tfr->len > 65535) { | |
374 | dev_warn_once(&spi->dev, | |
375 | "transfer size of %d too big for dma-transfer\n", | |
376 | tfr->len); | |
377 | return false; | |
378 | } | |
379 | ||
380 | /* if we run rx/tx_buf with word aligned addresses then we are OK */ | |
381 | if (((u32)tfr->tx_buf % 4 == 0) && ((u32)tfr->tx_buf % 4 == 0)) | |
382 | return true; | |
383 | ||
384 | /* otherwise we only allow transfers within the same page | |
385 | * to avoid wasting time on dma_mapping when it is not practical | |
386 | */ | |
387 | if (((u32)tfr->tx_buf % SZ_4K) + tfr->len > SZ_4K) { | |
388 | dev_warn_once(&spi->dev, | |
389 | "Unaligned spi tx-transfer bridging page\n"); | |
390 | return false; | |
391 | } | |
392 | if (((u32)tfr->rx_buf % SZ_4K) + tfr->len > SZ_4K) { | |
393 | dev_warn_once(&spi->dev, | |
394 | "Unaligned spi tx-transfer bridging page\n"); | |
395 | return false; | |
396 | } | |
397 | ||
398 | /* return OK */ | |
399 | return true; | |
400 | } | |
401 | ||
402 | void bcm2835_dma_release(struct spi_master *master) | |
403 | { | |
404 | if (master->dma_tx) { | |
405 | dmaengine_terminate_all(master->dma_tx); | |
406 | dma_release_channel(master->dma_tx); | |
407 | master->dma_tx = NULL; | |
408 | } | |
409 | if (master->dma_rx) { | |
410 | dmaengine_terminate_all(master->dma_rx); | |
411 | dma_release_channel(master->dma_rx); | |
412 | master->dma_rx = NULL; | |
413 | } | |
414 | } | |
415 | ||
416 | void bcm2835_dma_init(struct spi_master *master, struct device *dev) | |
417 | { | |
418 | struct dma_slave_config slave_config; | |
419 | const __be32 *addr; | |
420 | dma_addr_t dma_reg_base; | |
421 | int ret; | |
422 | ||
423 | /* base address in dma-space */ | |
424 | addr = of_get_address(master->dev.of_node, 0, NULL, NULL); | |
425 | if (!addr) { | |
426 | dev_err(dev, "could not get DMA-register address - not using dma mode\n"); | |
427 | goto err; | |
428 | } | |
429 | dma_reg_base = be32_to_cpup(addr); | |
430 | ||
431 | /* get tx/rx dma */ | |
432 | master->dma_tx = dma_request_slave_channel(dev, "tx"); | |
433 | if (!master->dma_tx) { | |
434 | dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); | |
435 | goto err; | |
436 | } | |
437 | master->dma_rx = dma_request_slave_channel(dev, "rx"); | |
438 | if (!master->dma_rx) { | |
439 | dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); | |
440 | goto err_release; | |
441 | } | |
442 | ||
443 | /* configure DMAs */ | |
444 | slave_config.direction = DMA_MEM_TO_DEV; | |
445 | slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); | |
446 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
447 | ||
448 | ret = dmaengine_slave_config(master->dma_tx, &slave_config); | |
449 | if (ret) | |
450 | goto err_config; | |
451 | ||
452 | slave_config.direction = DMA_DEV_TO_MEM; | |
453 | slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); | |
454 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
455 | ||
456 | ret = dmaengine_slave_config(master->dma_rx, &slave_config); | |
457 | if (ret) | |
458 | goto err_config; | |
459 | ||
460 | /* all went well, so set can_dma */ | |
461 | master->can_dma = bcm2835_spi_can_dma; | |
462 | master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */ | |
463 | /* need to do TX AND RX DMA, so we need dummy buffers */ | |
464 | master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; | |
465 | ||
466 | return; | |
467 | ||
468 | err_config: | |
469 | dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", | |
470 | ret); | |
471 | err_release: | |
472 | bcm2835_dma_release(master); | |
473 | err: | |
474 | return; | |
475 | } | |
476 | ||
a750b124 MS |
477 | static int bcm2835_spi_transfer_one_poll(struct spi_master *master, |
478 | struct spi_device *spi, | |
479 | struct spi_transfer *tfr, | |
480 | u32 cs, | |
481 | unsigned long xfer_time_us) | |
482 | { | |
483 | struct bcm2835_spi *bs = spi_master_get_devdata(master); | |
484 | unsigned long timeout; | |
485 | ||
486 | /* enable HW block without interrupts */ | |
487 | bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); | |
488 | ||
489 | /* fill in the fifo before timeout calculations | |
490 | * if we are interrupted here, then the data is | |
491 | * getting transferred by the HW while we are interrupted | |
492 | */ | |
493 | bcm2835_wr_fifo(bs); | |
494 | ||
495 | /* set the timeout */ | |
496 | timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES; | |
497 | ||
498 | /* loop until finished the transfer */ | |
499 | while (bs->rx_len) { | |
500 | /* fill in tx fifo with remaining data */ | |
501 | bcm2835_wr_fifo(bs); | |
502 | ||
503 | /* read from fifo as much as possible */ | |
504 | bcm2835_rd_fifo(bs); | |
505 | ||
506 | /* if there is still data pending to read | |
507 | * then check the timeout | |
508 | */ | |
509 | if (bs->rx_len && time_after(jiffies, timeout)) { | |
510 | dev_dbg_ratelimited(&spi->dev, | |
511 | "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", | |
512 | jiffies - timeout, | |
513 | bs->tx_len, bs->rx_len); | |
514 | /* fall back to interrupt mode */ | |
515 | return bcm2835_spi_transfer_one_irq(master, spi, | |
516 | tfr, cs); | |
517 | } | |
518 | } | |
519 | ||
520 | /* Transfer complete - reset SPI HW */ | |
521 | bcm2835_spi_reset_hw(master); | |
522 | /* and return without waiting for completion */ | |
523 | return 0; | |
524 | } | |
525 | ||
e34ff011 MS |
526 | static int bcm2835_spi_transfer_one(struct spi_master *master, |
527 | struct spi_device *spi, | |
528 | struct spi_transfer *tfr) | |
f8043872 | 529 | { |
e34ff011 | 530 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
f8043872 | 531 | unsigned long spi_hz, clk_hz, cdiv; |
704f32d4 | 532 | unsigned long spi_used_hz, xfer_time_us; |
e34ff011 | 533 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
f8043872 | 534 | |
e34ff011 | 535 | /* set clock */ |
f8043872 CB |
536 | spi_hz = tfr->speed_hz; |
537 | clk_hz = clk_get_rate(bs->clk); | |
538 | ||
539 | if (spi_hz >= clk_hz / 2) { | |
540 | cdiv = 2; /* clk_hz/2 is the fastest we can go */ | |
541 | } else if (spi_hz) { | |
210b4923 MS |
542 | /* CDIV must be a multiple of two */ |
543 | cdiv = DIV_ROUND_UP(clk_hz, spi_hz); | |
544 | cdiv += (cdiv % 2); | |
f8043872 CB |
545 | |
546 | if (cdiv >= 65536) | |
547 | cdiv = 0; /* 0 is the slowest we can go */ | |
342f948a | 548 | } else { |
f8043872 | 549 | cdiv = 0; /* 0 is the slowest we can go */ |
342f948a | 550 | } |
704f32d4 | 551 | spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536); |
e34ff011 | 552 | bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); |
f8043872 | 553 | |
e34ff011 | 554 | /* handle all the modes */ |
6935224d MS |
555 | if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf)) |
556 | cs |= BCM2835_SPI_CS_REN; | |
f8043872 CB |
557 | if (spi->mode & SPI_CPOL) |
558 | cs |= BCM2835_SPI_CS_CPOL; | |
559 | if (spi->mode & SPI_CPHA) | |
560 | cs |= BCM2835_SPI_CS_CPHA; | |
561 | ||
e34ff011 MS |
562 | /* for gpio_cs set dummy CS so that no HW-CS get changed |
563 | * we can not run this in bcm2835_spi_set_cs, as it does | |
564 | * not get called for cs_gpio cases, so we need to do it here | |
565 | */ | |
566 | if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS)) | |
567 | cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; | |
f8043872 | 568 | |
e34ff011 | 569 | /* set transmit buffers and length */ |
f8043872 CB |
570 | bs->tx_buf = tfr->tx_buf; |
571 | bs->rx_buf = tfr->rx_buf; | |
e34ff011 MS |
572 | bs->tx_len = tfr->len; |
573 | bs->rx_len = tfr->len; | |
f8043872 | 574 | |
704f32d4 MS |
575 | /* calculate the estimated time in us the transfer runs */ |
576 | xfer_time_us = tfr->len | |
577 | * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ | |
578 | * 1000000 / spi_used_hz; | |
e3a2be30 | 579 | |
704f32d4 MS |
580 | /* for short requests run polling*/ |
581 | if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) | |
582 | return bcm2835_spi_transfer_one_poll(master, spi, tfr, | |
583 | cs, xfer_time_us); | |
f8043872 | 584 | |
3ecd37ed MS |
585 | /* run in dma mode if conditions are right */ |
586 | if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr)) | |
587 | return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs); | |
588 | ||
589 | /* run in interrupt-mode */ | |
704f32d4 | 590 | return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); |
f8043872 CB |
591 | } |
592 | ||
e34ff011 MS |
593 | static void bcm2835_spi_handle_err(struct spi_master *master, |
594 | struct spi_message *msg) | |
f8043872 | 595 | { |
3ecd37ed MS |
596 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
597 | ||
598 | /* if an error occurred and we have an active dma, then terminate */ | |
599 | if (bs->dma_pending) { | |
600 | dmaengine_terminate_all(master->dma_tx); | |
601 | dmaengine_terminate_all(master->dma_rx); | |
602 | bs->dma_pending = 0; | |
603 | } | |
604 | /* and reset */ | |
e34ff011 | 605 | bcm2835_spi_reset_hw(master); |
f8043872 CB |
606 | } |
607 | ||
e34ff011 | 608 | static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level) |
f8043872 | 609 | { |
e34ff011 MS |
610 | /* |
611 | * we can assume that we are "native" as per spi_set_cs | |
612 | * calling us ONLY when cs_gpio is not set | |
613 | * we can also assume that we are CS < 3 as per bcm2835_spi_setup | |
614 | * we would not get called because of error handling there. | |
615 | * the level passed is the electrical level not enabled/disabled | |
616 | * so it has to get translated back to enable/disable | |
617 | * see spi_set_cs in spi.c for the implementation | |
618 | */ | |
619 | ||
620 | struct spi_master *master = spi->master; | |
f8043872 | 621 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
e34ff011 MS |
622 | u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); |
623 | bool enable; | |
f8043872 | 624 | |
e34ff011 MS |
625 | /* calculate the enable flag from the passed gpio_level */ |
626 | enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level; | |
f8043872 | 627 | |
e34ff011 MS |
628 | /* set flags for "reverse" polarity in the registers */ |
629 | if (spi->mode & SPI_CS_HIGH) { | |
630 | /* set the correct CS-bits */ | |
631 | cs |= BCM2835_SPI_CS_CSPOL; | |
632 | cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select; | |
633 | } else { | |
634 | /* clean the CS-bits */ | |
635 | cs &= ~BCM2835_SPI_CS_CSPOL; | |
636 | cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select); | |
637 | } | |
f8043872 | 638 | |
e34ff011 MS |
639 | /* select the correct chip_select depending on disabled/enabled */ |
640 | if (enable) { | |
641 | /* set cs correctly */ | |
642 | if (spi->mode & SPI_NO_CS) { | |
643 | /* use the "undefined" chip-select */ | |
644 | cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; | |
645 | } else { | |
646 | /* set the chip select */ | |
647 | cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01); | |
648 | cs |= spi->chip_select; | |
649 | } | |
650 | } else { | |
651 | /* disable CSPOL which puts HW-CS into deselected state */ | |
652 | cs &= ~BCM2835_SPI_CS_CSPOL; | |
653 | /* use the "undefined" chip-select as precaution */ | |
654 | cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; | |
f8043872 CB |
655 | } |
656 | ||
e34ff011 MS |
657 | /* finally set the calculated flags in SPI_CS */ |
658 | bcm2835_wr(bs, BCM2835_SPI_CS, cs); | |
659 | } | |
f8043872 | 660 | |
a30a555d MS |
661 | static int chip_match_name(struct gpio_chip *chip, void *data) |
662 | { | |
663 | return !strcmp(chip->label, data); | |
664 | } | |
665 | ||
e34ff011 MS |
666 | static int bcm2835_spi_setup(struct spi_device *spi) |
667 | { | |
a30a555d MS |
668 | int err; |
669 | struct gpio_chip *chip; | |
e34ff011 MS |
670 | /* |
671 | * sanity checking the native-chipselects | |
672 | */ | |
673 | if (spi->mode & SPI_NO_CS) | |
674 | return 0; | |
675 | if (gpio_is_valid(spi->cs_gpio)) | |
676 | return 0; | |
a30a555d MS |
677 | if (spi->chip_select > 1) { |
678 | /* error in the case of native CS requested with CS > 1 | |
679 | * officially there is a CS2, but it is not documented | |
680 | * which GPIO is connected with that... | |
681 | */ | |
682 | dev_err(&spi->dev, | |
683 | "setup: only two native chip-selects are supported\n"); | |
684 | return -EINVAL; | |
685 | } | |
686 | /* now translate native cs to GPIO */ | |
687 | ||
688 | /* get the gpio chip for the base */ | |
689 | chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); | |
690 | if (!chip) | |
e34ff011 MS |
691 | return 0; |
692 | ||
a30a555d MS |
693 | /* and calculate the real CS */ |
694 | spi->cs_gpio = chip->base + 8 - spi->chip_select; | |
695 | ||
696 | /* and set up the "mode" and level */ | |
697 | dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", | |
698 | spi->chip_select, spi->cs_gpio); | |
699 | ||
700 | /* set up GPIO as output and pull to the correct level */ | |
701 | err = gpio_direction_output(spi->cs_gpio, | |
702 | (spi->mode & SPI_CS_HIGH) ? 0 : 1); | |
703 | if (err) { | |
704 | dev_err(&spi->dev, | |
705 | "could not set CS%i gpio %i as output: %i", | |
706 | spi->chip_select, spi->cs_gpio, err); | |
707 | return err; | |
708 | } | |
709 | /* the implementation of pinctrl-bcm2835 currently does not | |
710 | * set the GPIO value when using gpio_direction_output | |
711 | * so we are setting it here explicitly | |
712 | */ | |
713 | gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1); | |
714 | ||
715 | return 0; | |
f8043872 CB |
716 | } |
717 | ||
718 | static int bcm2835_spi_probe(struct platform_device *pdev) | |
719 | { | |
720 | struct spi_master *master; | |
721 | struct bcm2835_spi *bs; | |
722 | struct resource *res; | |
723 | int err; | |
724 | ||
725 | master = spi_alloc_master(&pdev->dev, sizeof(*bs)); | |
726 | if (!master) { | |
727 | dev_err(&pdev->dev, "spi_alloc_master() failed\n"); | |
728 | return -ENOMEM; | |
729 | } | |
730 | ||
731 | platform_set_drvdata(pdev, master); | |
732 | ||
733 | master->mode_bits = BCM2835_SPI_MODE_BITS; | |
c2b6a3a8 | 734 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
f8043872 | 735 | master->num_chipselect = 3; |
e34ff011 MS |
736 | master->setup = bcm2835_spi_setup; |
737 | master->set_cs = bcm2835_spi_set_cs; | |
738 | master->transfer_one = bcm2835_spi_transfer_one; | |
739 | master->handle_err = bcm2835_spi_handle_err; | |
f8043872 CB |
740 | master->dev.of_node = pdev->dev.of_node; |
741 | ||
742 | bs = spi_master_get_devdata(master); | |
743 | ||
f8043872 | 744 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2d6e75e8 LN |
745 | bs->regs = devm_ioremap_resource(&pdev->dev, res); |
746 | if (IS_ERR(bs->regs)) { | |
747 | err = PTR_ERR(bs->regs); | |
f8043872 CB |
748 | goto out_master_put; |
749 | } | |
750 | ||
751 | bs->clk = devm_clk_get(&pdev->dev, NULL); | |
752 | if (IS_ERR(bs->clk)) { | |
753 | err = PTR_ERR(bs->clk); | |
754 | dev_err(&pdev->dev, "could not get clk: %d\n", err); | |
755 | goto out_master_put; | |
756 | } | |
757 | ||
758 | bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); | |
759 | if (bs->irq <= 0) { | |
760 | dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); | |
761 | err = bs->irq ? bs->irq : -ENODEV; | |
762 | goto out_master_put; | |
763 | } | |
764 | ||
765 | clk_prepare_enable(bs->clk); | |
766 | ||
08bc0544 | 767 | err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, |
342f948a | 768 | dev_name(&pdev->dev), master); |
f8043872 CB |
769 | if (err) { |
770 | dev_err(&pdev->dev, "could not request IRQ: %d\n", err); | |
771 | goto out_clk_disable; | |
772 | } | |
773 | ||
3ecd37ed MS |
774 | bcm2835_dma_init(master, &pdev->dev); |
775 | ||
e34ff011 | 776 | /* initialise the hardware with the default polarities */ |
f8043872 CB |
777 | bcm2835_wr(bs, BCM2835_SPI_CS, |
778 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
779 | ||
247263db | 780 | err = devm_spi_register_master(&pdev->dev, master); |
f8043872 CB |
781 | if (err) { |
782 | dev_err(&pdev->dev, "could not register SPI master: %d\n", err); | |
08bc0544 | 783 | goto out_clk_disable; |
f8043872 CB |
784 | } |
785 | ||
786 | return 0; | |
787 | ||
f8043872 CB |
788 | out_clk_disable: |
789 | clk_disable_unprepare(bs->clk); | |
790 | out_master_put: | |
791 | spi_master_put(master); | |
792 | return err; | |
793 | } | |
794 | ||
795 | static int bcm2835_spi_remove(struct platform_device *pdev) | |
796 | { | |
e0b35b89 | 797 | struct spi_master *master = platform_get_drvdata(pdev); |
f8043872 CB |
798 | struct bcm2835_spi *bs = spi_master_get_devdata(master); |
799 | ||
f8043872 CB |
800 | /* Clear FIFOs, and disable the HW block */ |
801 | bcm2835_wr(bs, BCM2835_SPI_CS, | |
802 | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); | |
803 | ||
804 | clk_disable_unprepare(bs->clk); | |
f8043872 | 805 | |
3ecd37ed MS |
806 | bcm2835_dma_release(master); |
807 | ||
f8043872 CB |
808 | return 0; |
809 | } | |
810 | ||
811 | static const struct of_device_id bcm2835_spi_match[] = { | |
812 | { .compatible = "brcm,bcm2835-spi", }, | |
813 | {} | |
814 | }; | |
815 | MODULE_DEVICE_TABLE(of, bcm2835_spi_match); | |
816 | ||
817 | static struct platform_driver bcm2835_spi_driver = { | |
818 | .driver = { | |
819 | .name = DRV_NAME, | |
f8043872 CB |
820 | .of_match_table = bcm2835_spi_match, |
821 | }, | |
822 | .probe = bcm2835_spi_probe, | |
823 | .remove = bcm2835_spi_remove, | |
824 | }; | |
825 | module_platform_driver(bcm2835_spi_driver); | |
826 | ||
827 | MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); | |
828 | MODULE_AUTHOR("Chris Boot <bootc@bootc.net>"); | |
829 | MODULE_LICENSE("GPL v2"); |