Commit | Line | Data |
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b42dfed8 FF |
1 | /* |
2 | * Broadcom BCM63xx SPI controller support | |
3 | * | |
cde4384e | 4 | * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> |
b42dfed8 FF |
5 | * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the | |
19 | * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/spi/spi.h> | |
31 | #include <linux/completion.h> | |
32 | #include <linux/err.h> | |
cde4384e FF |
33 | #include <linux/workqueue.h> |
34 | #include <linux/pm_runtime.h> | |
b42dfed8 FF |
35 | |
36 | #include <bcm63xx_dev_spi.h> | |
37 | ||
38 | #define PFX KBUILD_MODNAME | |
b42dfed8 | 39 | |
b17de076 JG |
40 | #define BCM63XX_SPI_MAX_PREPEND 15 |
41 | ||
b42dfed8 | 42 | struct bcm63xx_spi { |
b42dfed8 FF |
43 | struct completion done; |
44 | ||
45 | void __iomem *regs; | |
46 | int irq; | |
47 | ||
48 | /* Platform data */ | |
49 | u32 speed_hz; | |
50 | unsigned fifo_size; | |
5a670445 FF |
51 | unsigned int msg_type_shift; |
52 | unsigned int msg_ctl_width; | |
b42dfed8 | 53 | |
b42dfed8 FF |
54 | /* data iomem */ |
55 | u8 __iomem *tx_io; | |
56 | const u8 __iomem *rx_io; | |
57 | ||
b42dfed8 FF |
58 | struct clk *clk; |
59 | struct platform_device *pdev; | |
60 | }; | |
61 | ||
62 | static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, | |
63 | unsigned int offset) | |
64 | { | |
65 | return bcm_readb(bs->regs + bcm63xx_spireg(offset)); | |
66 | } | |
67 | ||
68 | static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, | |
69 | unsigned int offset) | |
70 | { | |
71 | return bcm_readw(bs->regs + bcm63xx_spireg(offset)); | |
72 | } | |
73 | ||
74 | static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, | |
75 | u8 value, unsigned int offset) | |
76 | { | |
77 | bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); | |
78 | } | |
79 | ||
80 | static inline void bcm_spi_writew(struct bcm63xx_spi *bs, | |
81 | u16 value, unsigned int offset) | |
82 | { | |
83 | bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); | |
84 | } | |
85 | ||
86 | static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { | |
87 | { 20000000, SPI_CLK_20MHZ }, | |
88 | { 12500000, SPI_CLK_12_50MHZ }, | |
89 | { 6250000, SPI_CLK_6_250MHZ }, | |
90 | { 3125000, SPI_CLK_3_125MHZ }, | |
91 | { 1563000, SPI_CLK_1_563MHZ }, | |
92 | { 781000, SPI_CLK_0_781MHZ }, | |
93 | { 391000, SPI_CLK_0_391MHZ } | |
94 | }; | |
95 | ||
cde4384e FF |
96 | static int bcm63xx_spi_check_transfer(struct spi_device *spi, |
97 | struct spi_transfer *t) | |
b42dfed8 | 98 | { |
b42dfed8 | 99 | u8 bits_per_word; |
b42dfed8 FF |
100 | |
101 | bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; | |
b42dfed8 FF |
102 | if (bits_per_word != 8) { |
103 | dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", | |
104 | __func__, bits_per_word); | |
105 | return -EINVAL; | |
106 | } | |
107 | ||
108 | if (spi->chip_select > spi->master->num_chipselect) { | |
109 | dev_err(&spi->dev, "%s, unsupported slave %d\n", | |
110 | __func__, spi->chip_select); | |
111 | return -EINVAL; | |
112 | } | |
113 | ||
cde4384e FF |
114 | return 0; |
115 | } | |
116 | ||
117 | static void bcm63xx_spi_setup_transfer(struct spi_device *spi, | |
118 | struct spi_transfer *t) | |
119 | { | |
120 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); | |
121 | u32 hz; | |
122 | u8 clk_cfg, reg; | |
123 | int i; | |
124 | ||
125 | hz = (t) ? t->speed_hz : spi->max_speed_hz; | |
126 | ||
b42dfed8 FF |
127 | /* Find the closest clock configuration */ |
128 | for (i = 0; i < SPI_CLK_MASK; i++) { | |
d76ea24a | 129 | if (hz >= bcm63xx_spi_freq_table[i][0]) { |
b42dfed8 FF |
130 | clk_cfg = bcm63xx_spi_freq_table[i][1]; |
131 | break; | |
132 | } | |
133 | } | |
134 | ||
135 | /* No matching configuration found, default to lowest */ | |
136 | if (i == SPI_CLK_MASK) | |
137 | clk_cfg = SPI_CLK_0_391MHZ; | |
138 | ||
139 | /* clear existing clock configuration bits of the register */ | |
140 | reg = bcm_spi_readb(bs, SPI_CLK_CFG); | |
141 | reg &= ~SPI_CLK_MASK; | |
142 | reg |= clk_cfg; | |
143 | ||
144 | bcm_spi_writeb(bs, reg, SPI_CLK_CFG); | |
145 | dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", | |
146 | clk_cfg, hz); | |
b42dfed8 FF |
147 | } |
148 | ||
149 | /* the spi->mode bits understood by this driver: */ | |
150 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | |
151 | ||
152 | static int bcm63xx_spi_setup(struct spi_device *spi) | |
153 | { | |
154 | struct bcm63xx_spi *bs; | |
155 | int ret; | |
156 | ||
157 | bs = spi_master_get_devdata(spi->master); | |
158 | ||
b42dfed8 FF |
159 | if (!spi->bits_per_word) |
160 | spi->bits_per_word = 8; | |
161 | ||
162 | if (spi->mode & ~MODEBITS) { | |
163 | dev_err(&spi->dev, "%s, unsupported mode bits %x\n", | |
164 | __func__, spi->mode & ~MODEBITS); | |
165 | return -EINVAL; | |
166 | } | |
167 | ||
b42dfed8 FF |
168 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", |
169 | __func__, spi->mode & MODEBITS, spi->bits_per_word, 0); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
b17de076 JG |
174 | static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, |
175 | unsigned int num_transfers) | |
b42dfed8 FF |
176 | { |
177 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); | |
178 | u16 msg_ctl; | |
179 | u16 cmd; | |
c0fde3ba | 180 | u8 rx_tail; |
b17de076 JG |
181 | unsigned int i, timeout = 0, prepend_len = 0, len = 0; |
182 | struct spi_transfer *t = first; | |
183 | bool do_rx = false; | |
184 | bool do_tx = false; | |
b42dfed8 | 185 | |
cde4384e FF |
186 | /* Disable the CMD_DONE interrupt */ |
187 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | |
188 | ||
b42dfed8 FF |
189 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", |
190 | t->tx_buf, t->rx_buf, t->len); | |
191 | ||
b17de076 JG |
192 | if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) |
193 | prepend_len = t->len; | |
194 | ||
195 | /* prepare the buffer */ | |
196 | for (i = 0; i < num_transfers; i++) { | |
197 | if (t->tx_buf) { | |
198 | do_tx = true; | |
199 | memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); | |
200 | ||
201 | /* don't prepend more than one tx */ | |
202 | if (t != first) | |
203 | prepend_len = 0; | |
204 | } | |
205 | ||
206 | if (t->rx_buf) { | |
207 | do_rx = true; | |
208 | /* prepend is half-duplex write only */ | |
209 | if (t == first) | |
210 | prepend_len = 0; | |
211 | } | |
212 | ||
213 | len += t->len; | |
214 | ||
215 | t = list_entry(t->transfer_list.next, struct spi_transfer, | |
216 | transfer_list); | |
217 | } | |
218 | ||
219 | len -= prepend_len; | |
b42dfed8 | 220 | |
cde4384e | 221 | init_completion(&bs->done); |
b42dfed8 FF |
222 | |
223 | /* Fill in the Message control register */ | |
b17de076 | 224 | msg_ctl = (len << SPI_BYTE_CNT_SHIFT); |
b42dfed8 | 225 | |
b17de076 | 226 | if (do_rx && do_tx && prepend_len == 0) |
5a670445 | 227 | msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); |
b17de076 | 228 | else if (do_rx) |
5a670445 | 229 | msg_ctl |= (SPI_HD_R << bs->msg_type_shift); |
b17de076 | 230 | else if (do_tx) |
5a670445 FF |
231 | msg_ctl |= (SPI_HD_W << bs->msg_type_shift); |
232 | ||
233 | switch (bs->msg_ctl_width) { | |
234 | case 8: | |
235 | bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); | |
236 | break; | |
237 | case 16: | |
238 | bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); | |
239 | break; | |
240 | } | |
b42dfed8 FF |
241 | |
242 | /* Issue the transfer */ | |
243 | cmd = SPI_CMD_START_IMMEDIATE; | |
b17de076 | 244 | cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); |
b42dfed8 FF |
245 | cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); |
246 | bcm_spi_writew(bs, cmd, SPI_CMD); | |
b42dfed8 | 247 | |
cde4384e FF |
248 | /* Enable the CMD_DONE interrupt */ |
249 | bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); | |
b42dfed8 | 250 | |
c0fde3ba JG |
251 | timeout = wait_for_completion_timeout(&bs->done, HZ); |
252 | if (!timeout) | |
253 | return -ETIMEDOUT; | |
254 | ||
255 | /* read out all data */ | |
256 | rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL); | |
257 | ||
b17de076 JG |
258 | if (do_rx && rx_tail != len) |
259 | return -EIO; | |
260 | ||
261 | if (!rx_tail) | |
262 | return 0; | |
263 | ||
264 | len = 0; | |
265 | t = first; | |
c0fde3ba | 266 | /* Read out all the data */ |
b17de076 JG |
267 | for (i = 0; i < num_transfers; i++) { |
268 | if (t->rx_buf) | |
269 | memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); | |
270 | ||
271 | if (t != first || prepend_len == 0) | |
272 | len += t->len; | |
273 | ||
274 | t = list_entry(t->transfer_list.next, struct spi_transfer, | |
275 | transfer_list); | |
276 | } | |
c0fde3ba JG |
277 | |
278 | return 0; | |
b42dfed8 FF |
279 | } |
280 | ||
cde4384e | 281 | static int bcm63xx_spi_prepare_transfer(struct spi_master *master) |
b42dfed8 | 282 | { |
cde4384e | 283 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
b42dfed8 | 284 | |
cde4384e | 285 | pm_runtime_get_sync(&bs->pdev->dev); |
b42dfed8 | 286 | |
cde4384e FF |
287 | return 0; |
288 | } | |
289 | ||
290 | static int bcm63xx_spi_unprepare_transfer(struct spi_master *master) | |
291 | { | |
292 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | |
293 | ||
294 | pm_runtime_put(&bs->pdev->dev); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | static int bcm63xx_spi_transfer_one(struct spi_master *master, | |
300 | struct spi_message *m) | |
301 | { | |
302 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | |
b17de076 | 303 | struct spi_transfer *t, *first = NULL; |
cde4384e FF |
304 | struct spi_device *spi = m->spi; |
305 | int status = 0; | |
b17de076 JG |
306 | unsigned int n_transfers = 0, total_len = 0; |
307 | bool can_use_prepend = false; | |
308 | ||
309 | /* | |
310 | * This SPI controller does not support keeping CS active after a | |
311 | * transfer. | |
312 | * Work around this by merging as many transfers we can into one big | |
313 | * full-duplex transfers. | |
314 | */ | |
b42dfed8 | 315 | list_for_each_entry(t, &m->transfers, transfer_list) { |
cde4384e FF |
316 | status = bcm63xx_spi_check_transfer(spi, t); |
317 | if (status < 0) | |
318 | goto exit; | |
319 | ||
b17de076 JG |
320 | if (!first) |
321 | first = t; | |
322 | ||
323 | n_transfers++; | |
324 | total_len += t->len; | |
325 | ||
326 | if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && | |
327 | first->len <= BCM63XX_SPI_MAX_PREPEND) | |
328 | can_use_prepend = true; | |
329 | else if (can_use_prepend && t->tx_buf) | |
330 | can_use_prepend = false; | |
331 | ||
c0fde3ba | 332 | /* we can only transfer one fifo worth of data */ |
b17de076 JG |
333 | if ((can_use_prepend && |
334 | total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || | |
335 | (!can_use_prepend && total_len > bs->fifo_size)) { | |
c0fde3ba | 336 | dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", |
b17de076 | 337 | total_len, bs->fifo_size); |
c0fde3ba JG |
338 | status = -EINVAL; |
339 | goto exit; | |
340 | } | |
cde4384e | 341 | |
b17de076 JG |
342 | /* all combined transfers have to have the same speed */ |
343 | if (t->speed_hz != first->speed_hz) { | |
344 | dev_err(&spi->dev, "unable to change speed between transfers\n"); | |
c0fde3ba JG |
345 | status = -EINVAL; |
346 | goto exit; | |
347 | } | |
cde4384e | 348 | |
b17de076 JG |
349 | /* CS will be deasserted directly after transfer */ |
350 | if (t->delay_usecs) { | |
351 | dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); | |
c0fde3ba JG |
352 | status = -EINVAL; |
353 | goto exit; | |
354 | } | |
cde4384e | 355 | |
b17de076 JG |
356 | if (t->cs_change || |
357 | list_is_last(&t->transfer_list, &m->transfers)) { | |
358 | /* configure adapter for a new transfer */ | |
359 | bcm63xx_spi_setup_transfer(spi, first); | |
cde4384e | 360 | |
b17de076 JG |
361 | /* send the data */ |
362 | status = bcm63xx_txrx_bufs(spi, first, n_transfers); | |
363 | if (status) | |
364 | goto exit; | |
365 | ||
366 | m->actual_length += total_len; | |
b42dfed8 | 367 | |
b17de076 JG |
368 | first = NULL; |
369 | n_transfers = 0; | |
370 | total_len = 0; | |
371 | can_use_prepend = false; | |
372 | } | |
cde4384e FF |
373 | } |
374 | exit: | |
375 | m->status = status; | |
376 | spi_finalize_current_message(master); | |
b42dfed8 | 377 | |
cde4384e | 378 | return 0; |
b42dfed8 FF |
379 | } |
380 | ||
381 | /* This driver supports single master mode only. Hence | |
382 | * CMD_DONE is the only interrupt we care about | |
383 | */ | |
384 | static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) | |
385 | { | |
386 | struct spi_master *master = (struct spi_master *)dev_id; | |
387 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | |
388 | u8 intr; | |
b42dfed8 FF |
389 | |
390 | /* Read interupts and clear them immediately */ | |
391 | intr = bcm_spi_readb(bs, SPI_INT_STATUS); | |
392 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); | |
393 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | |
394 | ||
cde4384e FF |
395 | /* A transfer completed */ |
396 | if (intr & SPI_INTR_CMD_DONE) | |
397 | complete(&bs->done); | |
b42dfed8 FF |
398 | |
399 | return IRQ_HANDLED; | |
400 | } | |
401 | ||
402 | ||
fd4a319b | 403 | static int bcm63xx_spi_probe(struct platform_device *pdev) |
b42dfed8 FF |
404 | { |
405 | struct resource *r; | |
406 | struct device *dev = &pdev->dev; | |
407 | struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data; | |
408 | int irq; | |
409 | struct spi_master *master; | |
410 | struct clk *clk; | |
411 | struct bcm63xx_spi *bs; | |
412 | int ret; | |
413 | ||
414 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
415 | if (!r) { | |
416 | dev_err(dev, "no iomem\n"); | |
417 | ret = -ENXIO; | |
418 | goto out; | |
419 | } | |
420 | ||
421 | irq = platform_get_irq(pdev, 0); | |
422 | if (irq < 0) { | |
423 | dev_err(dev, "no irq\n"); | |
424 | ret = -ENXIO; | |
425 | goto out; | |
426 | } | |
427 | ||
428 | clk = clk_get(dev, "spi"); | |
429 | if (IS_ERR(clk)) { | |
430 | dev_err(dev, "no clock for device\n"); | |
431 | ret = PTR_ERR(clk); | |
432 | goto out; | |
433 | } | |
434 | ||
435 | master = spi_alloc_master(dev, sizeof(*bs)); | |
436 | if (!master) { | |
437 | dev_err(dev, "out of memory\n"); | |
438 | ret = -ENOMEM; | |
439 | goto out_clk; | |
440 | } | |
441 | ||
442 | bs = spi_master_get_devdata(master); | |
b42dfed8 FF |
443 | |
444 | platform_set_drvdata(pdev, master); | |
445 | bs->pdev = pdev; | |
446 | ||
447 | if (!devm_request_mem_region(&pdev->dev, r->start, | |
448 | resource_size(r), PFX)) { | |
449 | dev_err(dev, "iomem request failed\n"); | |
450 | ret = -ENXIO; | |
451 | goto out_err; | |
452 | } | |
453 | ||
454 | bs->regs = devm_ioremap_nocache(&pdev->dev, r->start, | |
455 | resource_size(r)); | |
456 | if (!bs->regs) { | |
457 | dev_err(dev, "unable to ioremap regs\n"); | |
458 | ret = -ENOMEM; | |
459 | goto out_err; | |
460 | } | |
461 | ||
462 | bs->irq = irq; | |
463 | bs->clk = clk; | |
464 | bs->fifo_size = pdata->fifo_size; | |
465 | ||
466 | ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, | |
467 | pdev->name, master); | |
468 | if (ret) { | |
469 | dev_err(dev, "unable to request irq\n"); | |
470 | goto out_err; | |
471 | } | |
472 | ||
473 | master->bus_num = pdata->bus_num; | |
474 | master->num_chipselect = pdata->num_chipselect; | |
475 | master->setup = bcm63xx_spi_setup; | |
cde4384e FF |
476 | master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer; |
477 | master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer; | |
478 | master->transfer_one_message = bcm63xx_spi_transfer_one; | |
88a3a255 | 479 | master->mode_bits = MODEBITS; |
b42dfed8 | 480 | bs->speed_hz = pdata->speed_hz; |
5a670445 FF |
481 | bs->msg_type_shift = pdata->msg_type_shift; |
482 | bs->msg_ctl_width = pdata->msg_ctl_width; | |
b42dfed8 FF |
483 | bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); |
484 | bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); | |
b42dfed8 | 485 | |
5a670445 FF |
486 | switch (bs->msg_ctl_width) { |
487 | case 8: | |
488 | case 16: | |
489 | break; | |
490 | default: | |
491 | dev_err(dev, "unsupported MSG_CTL width: %d\n", | |
492 | bs->msg_ctl_width); | |
493 | goto out_clk_disable; | |
494 | } | |
495 | ||
b42dfed8 FF |
496 | /* Initialize hardware */ |
497 | clk_enable(bs->clk); | |
498 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); | |
499 | ||
500 | /* register and we are done */ | |
501 | ret = spi_register_master(master); | |
502 | if (ret) { | |
503 | dev_err(dev, "spi register failed\n"); | |
504 | goto out_clk_disable; | |
505 | } | |
506 | ||
61d15963 FF |
507 | dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", |
508 | r->start, irq, bs->fifo_size); | |
b42dfed8 FF |
509 | |
510 | return 0; | |
511 | ||
512 | out_clk_disable: | |
513 | clk_disable(clk); | |
514 | out_err: | |
515 | platform_set_drvdata(pdev, NULL); | |
516 | spi_master_put(master); | |
517 | out_clk: | |
518 | clk_put(clk); | |
519 | out: | |
520 | return ret; | |
521 | } | |
522 | ||
fd4a319b | 523 | static int bcm63xx_spi_remove(struct platform_device *pdev) |
b42dfed8 | 524 | { |
1f682378 | 525 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
b42dfed8 FF |
526 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
527 | ||
1e41dc0e FF |
528 | spi_unregister_master(master); |
529 | ||
b42dfed8 FF |
530 | /* reset spi block */ |
531 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | |
b42dfed8 FF |
532 | |
533 | /* HW shutdown */ | |
534 | clk_disable(bs->clk); | |
535 | clk_put(bs->clk); | |
536 | ||
b42dfed8 | 537 | platform_set_drvdata(pdev, 0); |
b42dfed8 | 538 | |
1f682378 GR |
539 | spi_master_put(master); |
540 | ||
b42dfed8 FF |
541 | return 0; |
542 | } | |
543 | ||
544 | #ifdef CONFIG_PM | |
545 | static int bcm63xx_spi_suspend(struct device *dev) | |
546 | { | |
547 | struct spi_master *master = | |
548 | platform_get_drvdata(to_platform_device(dev)); | |
549 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | |
550 | ||
96519957 FF |
551 | spi_master_suspend(master); |
552 | ||
b42dfed8 FF |
553 | clk_disable(bs->clk); |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | static int bcm63xx_spi_resume(struct device *dev) | |
559 | { | |
560 | struct spi_master *master = | |
561 | platform_get_drvdata(to_platform_device(dev)); | |
562 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | |
563 | ||
564 | clk_enable(bs->clk); | |
565 | ||
96519957 FF |
566 | spi_master_resume(master); |
567 | ||
b42dfed8 FF |
568 | return 0; |
569 | } | |
570 | ||
571 | static const struct dev_pm_ops bcm63xx_spi_pm_ops = { | |
572 | .suspend = bcm63xx_spi_suspend, | |
573 | .resume = bcm63xx_spi_resume, | |
574 | }; | |
575 | ||
576 | #define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops) | |
577 | #else | |
578 | #define BCM63XX_SPI_PM_OPS NULL | |
579 | #endif | |
580 | ||
581 | static struct platform_driver bcm63xx_spi_driver = { | |
582 | .driver = { | |
583 | .name = "bcm63xx-spi", | |
584 | .owner = THIS_MODULE, | |
585 | .pm = BCM63XX_SPI_PM_OPS, | |
586 | }, | |
587 | .probe = bcm63xx_spi_probe, | |
fd4a319b | 588 | .remove = bcm63xx_spi_remove, |
b42dfed8 FF |
589 | }; |
590 | ||
591 | module_platform_driver(bcm63xx_spi_driver); | |
592 | ||
593 | MODULE_ALIAS("platform:bcm63xx_spi"); | |
594 | MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); | |
595 | MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); | |
596 | MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); | |
597 | MODULE_LICENSE("GPL"); |