[deliverable/linux.git] / drivers / spi / spi-bcm63xx.c

/*
 * Broadcom BCM63xx SPI controller support
 *
 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the
 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/workqueue.h>
#include <linux/pm_runtime.h>

#include <bcm63xx_dev_spi.h>

#define PFX		KBUILD_MODNAME

#define BCM63XX_SPI_MAX_PREPEND		15

struct bcm63xx_spi {
	struct completion	done;

	void __iomem		*regs;
	int			irq;

	/* Platform data */
	u32			speed_hz;
	unsigned		fifo_size;
	unsigned int		msg_type_shift;
	unsigned int		msg_ctl_width;

	/* data iomem */
	u8 __iomem		*tx_io;
	const u8 __iomem	*rx_io;

	struct clk		*clk;
	struct platform_device	*pdev;
};

static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
}

static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
				  u8 value, unsigned int offset)
{
	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
				  u16 value, unsigned int offset)
{
	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
}

static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	{ 20000000, SPI_CLK_20MHZ },
	{ 12500000, SPI_CLK_12_50MHZ },
	{  6250000, SPI_CLK_6_250MHZ },
	{  3125000, SPI_CLK_3_125MHZ },
	{  1563000, SPI_CLK_1_563MHZ },
	{   781000, SPI_CLK_0_781MHZ },
	{   391000, SPI_CLK_0_391MHZ }
};

static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
				      struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u8 clk_cfg, reg;
	int i;

	/* Find the closest clock configuration */
	for (i = 0; i < SPI_CLK_MASK; i++) {
		if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
			clk_cfg = bcm63xx_spi_freq_table[i][1];
			break;
		}
	}

	/* No matching configuration found, default to lowest */
	if (i == SPI_CLK_MASK)
		clk_cfg = SPI_CLK_0_391MHZ;

	/* clear existing clock configuration bits of the register */
	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	reg &= ~SPI_CLK_MASK;
	reg |= clk_cfg;

	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
		clk_cfg, t->speed_hz);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)

static int bcm63xx_spi_setup(struct spi_device *spi)
{
	if (spi->bits_per_word != 8) {
		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
			__func__, spi->bits_per_word);
		return -EINVAL;
	}

	return 0;
}

static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
				unsigned int num_transfers)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u16 msg_ctl;
	u16 cmd;
	u8 rx_tail;
	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	struct spi_transfer *t = first;
	bool do_rx = false;
	bool do_tx = false;

	/* Disable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
		prepend_len = t->len;

	/* prepare the buffer */
	for (i = 0; i < num_transfers; i++) {
		if (t->tx_buf) {
			do_tx = true;
			memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);

			/* don't prepend more than one tx */
			if (t != first)
				prepend_len = 0;
		}

		if (t->rx_buf) {
			do_rx = true;
			/* prepend is half-duplex write only */
			if (t == first)
				prepend_len = 0;
		}

		len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	len -= prepend_len;

	init_completion(&bs->done);

	/* Fill in the Message control register */
	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);

	if (do_rx && do_tx && prepend_len == 0)
		msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
	else if (do_rx)
		msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
	else if (do_tx)
		msg_ctl |= (SPI_HD_W << bs->msg_type_shift);

	switch (bs->msg_ctl_width) {
	case 8:
		bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
		break;
	case 16:
		bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
		break;
	}

	/* Issue the transfer */
	cmd = SPI_CMD_START_IMMEDIATE;
	cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	bcm_spi_writew(bs, cmd, SPI_CMD);

	/* Enable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);

	timeout = wait_for_completion_timeout(&bs->done, HZ);
	if (!timeout)
		return -ETIMEDOUT;

	/* read out all data */
	rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);

	if (do_rx && rx_tail != len)
		return -EIO;

	if (!rx_tail)
		return 0;

	len = 0;
	t = first;
	/* Read out all the data */
	for (i = 0; i < num_transfers; i++) {
		if (t->rx_buf)
			memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);

		if (t != first || prepend_len == 0)
			len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	return 0;
}

static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	pm_runtime_get_sync(&bs->pdev->dev);

	return 0;
}

static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	pm_runtime_put(&bs->pdev->dev);

	return 0;
}

static int bcm63xx_spi_transfer_one(struct spi_master *master,
					struct spi_message *m)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t, *first = NULL;
	struct spi_device *spi = m->spi;
	int status = 0;
	unsigned int n_transfers = 0, total_len = 0;
	bool can_use_prepend = false;

	/*
	 * This SPI controller does not support keeping CS active after a
	 * transfer.
	 * Work around this by merging as many transfers we can into one big
	 * full-duplex transfers.
	 */
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->bits_per_word != 8) {
			dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
				__func__, t->bits_per_word);
			status = -EINVAL;
			goto exit;
		}

		if (!first)
			first = t;

		n_transfers++;
		total_len += t->len;

		if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
		    first->len <= BCM63XX_SPI_MAX_PREPEND)
			can_use_prepend = true;
		else if (can_use_prepend && t->tx_buf)
			can_use_prepend = false;

		/* we can only transfer one fifo worth of data */
		if ((can_use_prepend &&
		     total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
		    (!can_use_prepend && total_len > bs->fifo_size)) {
			dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
				total_len, bs->fifo_size);
			status = -EINVAL;
			goto exit;
		}

		/* all combined transfers have to have the same speed */
		if (t->speed_hz != first->speed_hz) {
			dev_err(&spi->dev, "unable to change speed between transfers\n");
			status = -EINVAL;
			goto exit;
		}

		/* CS will be deasserted directly after transfer */
		if (t->delay_usecs) {
			dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
			status = -EINVAL;
			goto exit;
		}

		if (t->cs_change ||
		    list_is_last(&t->transfer_list, &m->transfers)) {
			/* configure adapter for a new transfer */
			bcm63xx_spi_setup_transfer(spi, first);

			/* send the data */
			status = bcm63xx_txrx_bufs(spi, first, n_transfers);
			if (status)
				goto exit;

			m->actual_length += total_len;

			first = NULL;
			n_transfers = 0;
			total_len = 0;
			can_use_prepend = false;
		}
	}
exit:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

/* This driver supports single master mode only. Hence
 * CMD_DONE is the only interrupt we care about
 */
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = (struct spi_master *)dev_id;
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	u8 intr;

	/* Read interupts and clear them immediately */
	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* A transfer completed */
	if (intr & SPI_INTR_CMD_DONE)
		complete(&bs->done);

	return IRQ_HANDLED;
}


static int bcm63xx_spi_probe(struct platform_device *pdev)
{
	struct resource *r;
	struct device *dev = &pdev->dev;
	struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
	int irq;
	struct spi_master *master;
	struct clk *clk;
	struct bcm63xx_spi *bs;
	int ret;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(dev, "no iomem\n");
		ret = -ENXIO;
		goto out;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq\n");
		ret = -ENXIO;
		goto out;
	}

	clk = clk_get(dev, "spi");
	if (IS_ERR(clk)) {
		dev_err(dev, "no clock for device\n");
		ret = PTR_ERR(clk);
		goto out;
	}

	master = spi_alloc_master(dev, sizeof(*bs));
	if (!master) {
		dev_err(dev, "out of memory\n");
		ret = -ENOMEM;
		goto out_clk;
	}

	bs = spi_master_get_devdata(master);

	platform_set_drvdata(pdev, master);
	bs->pdev = pdev;

	if (!devm_request_mem_region(&pdev->dev, r->start,
					resource_size(r), PFX)) {
		dev_err(dev, "iomem request failed\n");
		ret = -ENXIO;
		goto out_err;
	}

	bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
							resource_size(r));
	if (!bs->regs) {
		dev_err(dev, "unable to ioremap regs\n");
		ret = -ENOMEM;
		goto out_err;
	}

	bs->irq = irq;
	bs->clk = clk;
	bs->fifo_size = pdata->fifo_size;

	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
							pdev->name, master);
	if (ret) {
		dev_err(dev, "unable to request irq\n");
		goto out_err;
	}

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;
	master->setup = bcm63xx_spi_setup;
	master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
	master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
	master->transfer_one_message = bcm63xx_spi_transfer_one;
	master->mode_bits = MODEBITS;
	bs->speed_hz = pdata->speed_hz;
	bs->msg_type_shift = pdata->msg_type_shift;
	bs->msg_ctl_width = pdata->msg_ctl_width;
	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));

	switch (bs->msg_ctl_width) {
	case 8:
	case 16:
		break;
	default:
		dev_err(dev, "unsupported MSG_CTL width: %d\n",
			 bs->msg_ctl_width);
		goto out_err;
	}

	/* Initialize hardware */
	clk_prepare_enable(bs->clk);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);

	/* register and we are done */
	ret = spi_register_master(master);
	if (ret) {
		dev_err(dev, "spi register failed\n");
		goto out_clk_disable;
	}

	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
		 r->start, irq, bs->fifo_size);

	return 0;

out_clk_disable:
	clk_disable_unprepare(clk);
out_err:
	platform_set_drvdata(pdev, NULL);
	spi_master_put(master);
out_clk:
	clk_put(clk);
out:
	return ret;
}

static int bcm63xx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_unregister_master(master);

	/* reset spi block */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* HW shutdown */
	clk_disable_unprepare(bs->clk);
	clk_put(bs->clk);

	platform_set_drvdata(pdev, 0);

	spi_master_put(master);

	return 0;
}

#ifdef CONFIG_PM
static int bcm63xx_spi_suspend(struct device *dev)
{
	struct spi_master *master =
			platform_get_drvdata(to_platform_device(dev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);

	clk_disable_unprepare(bs->clk);

	return 0;
}

static int bcm63xx_spi_resume(struct device *dev)
{
	struct spi_master *master =
			platform_get_drvdata(to_platform_device(dev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	clk_prepare_enable(bs->clk);

	spi_master_resume(master);

	return 0;
}

static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	.suspend	= bcm63xx_spi_suspend,
	.resume		= bcm63xx_spi_resume,
};

#define BCM63XX_SPI_PM_OPS	(&bcm63xx_spi_pm_ops)
#else
#define BCM63XX_SPI_PM_OPS	NULL
#endif

static struct platform_driver bcm63xx_spi_driver = {
	.driver = {
		.name	= "bcm63xx-spi",
		.owner	= THIS_MODULE,
		.pm	= BCM63XX_SPI_PM_OPS,
	},
	.probe		= bcm63xx_spi_probe,
	.remove		= bcm63xx_spi_remove,
};

module_platform_driver(bcm63xx_spi_driver);

MODULE_ALIAS("platform:bcm63xx_spi");
MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b42dfed8 FF	1	/*
	2	* Broadcom BCM63xx SPI controller support
	3	*
cde4384e	4	* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
b42dfed8 FF	5	* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version 2
	10	* of the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the
	19	* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
	24	#include <linux/clk.h>
	25	#include <linux/io.h>
	26	#include <linux/module.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/delay.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/spi/spi.h>
	31	#include <linux/completion.h>
	32	#include <linux/err.h>
cde4384e FF	33	#include <linux/workqueue.h>
cde4384e FF	34	#include <linux/pm_runtime.h>
b42dfed8 FF	35
	36	#include <bcm63xx_dev_spi.h>
	37
	38	#define PFX KBUILD_MODNAME
b42dfed8	39
b17de076 JG	40	#define BCM63XX_SPI_MAX_PREPEND 15
b17de076 JG	41
b42dfed8	42	struct bcm63xx_spi {
b42dfed8 FF	43	struct completion done;
	44
	45	void __iomem *regs;
	46	int irq;
	47
	48	/* Platform data */
	49	u32 speed_hz;
	50	unsigned fifo_size;
5a670445 FF	51	unsigned int msg_type_shift;
5a670445 FF	52	unsigned int msg_ctl_width;
b42dfed8	53
b42dfed8 FF	54	/* data iomem */
	55	u8 __iomem *tx_io;
	56	const u8 __iomem *rx_io;
	57
b42dfed8 FF	58	struct clk *clk;
	59	struct platform_device *pdev;
	60	};
	61
	62	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
	63	unsigned int offset)
	64	{
	65	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
	66	}
	67
	68	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
	69	unsigned int offset)
	70	{
	71	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
	72	}
	73
	74	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
	75	u8 value, unsigned int offset)
	76	{
	77	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
	78	}
	79
	80	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
	81	u16 value, unsigned int offset)
	82	{
	83	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
	84	}
	85
	86	static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	87	{ 20000000, SPI_CLK_20MHZ },
	88	{ 12500000, SPI_CLK_12_50MHZ },
	89	{ 6250000, SPI_CLK_6_250MHZ },
	90	{ 3125000, SPI_CLK_3_125MHZ },
	91	{ 1563000, SPI_CLK_1_563MHZ },
	92	{ 781000, SPI_CLK_0_781MHZ },
	93	{ 391000, SPI_CLK_0_391MHZ }
	94	};
	95
cde4384e FF	96	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
	97	struct spi_transfer *t)
	98	{
	99	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
cde4384e FF	100	u8 clk_cfg, reg;
	101	int i;
	102
b42dfed8 FF	103	/* Find the closest clock configuration */
b42dfed8 FF	104	for (i = 0; i < SPI_CLK_MASK; i++) {
68792e2a	105	if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
b42dfed8 FF	106	clk_cfg = bcm63xx_spi_freq_table[i][1];
	107	break;
	108	}
	109	}
	110
	111	/* No matching configuration found, default to lowest */
	112	if (i == SPI_CLK_MASK)
	113	clk_cfg = SPI_CLK_0_391MHZ;
	114
	115	/* clear existing clock configuration bits of the register */
	116	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	117	reg &= ~SPI_CLK_MASK;
	118	reg \|= clk_cfg;
	119
	120	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	121	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
68792e2a	122	clk_cfg, t->speed_hz);
b42dfed8 FF	123	}
	124
	125	/* the spi->mode bits understood by this driver: */
	126	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
	127
	128	static int bcm63xx_spi_setup(struct spi_device *spi)
	129	{
e2bdae06 JG	130	if (spi->bits_per_word != 8) {
	131	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
	132	__func__, spi->bits_per_word);
	133	return -EINVAL;
	134	}
b42dfed8	135
b42dfed8 FF	136	return 0;
	137	}
	138
b17de076 JG	139	static int bcm63xx_txrx_bufs(struct spi_device spi, struct spi_transfer first,
b17de076 JG	140	unsigned int num_transfers)
b42dfed8 FF	141	{
	142	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	143	u16 msg_ctl;
	144	u16 cmd;
c0fde3ba	145	u8 rx_tail;
b17de076 JG	146	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	147	struct spi_transfer *t = first;
	148	bool do_rx = false;
	149	bool do_tx = false;
b42dfed8	150
cde4384e FF	151	/* Disable the CMD_DONE interrupt */
	152	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	153
b42dfed8 FF	154	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	155	t->tx_buf, t->rx_buf, t->len);
	156
b17de076 JG	157	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
	158	prepend_len = t->len;
	159
	160	/* prepare the buffer */
	161	for (i = 0; i < num_transfers; i++) {
	162	if (t->tx_buf) {
	163	do_tx = true;
	164	memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
	165
	166	/* don't prepend more than one tx */
	167	if (t != first)
	168	prepend_len = 0;
	169	}
	170
	171	if (t->rx_buf) {
	172	do_rx = true;
	173	/* prepend is half-duplex write only */
	174	if (t == first)
	175	prepend_len = 0;
	176	}
	177
	178	len += t->len;
	179
	180	t = list_entry(t->transfer_list.next, struct spi_transfer,
	181	transfer_list);
	182	}
	183
	184	len -= prepend_len;
b42dfed8	185
cde4384e	186	init_completion(&bs->done);
b42dfed8 FF	187
b42dfed8 FF	188	/* Fill in the Message control register */
b17de076	189	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
b42dfed8	190
b17de076	191	if (do_rx && do_tx && prepend_len == 0)
5a670445	192	msg_ctl \|= (SPI_FD_RW << bs->msg_type_shift);
b17de076	193	else if (do_rx)
5a670445	194	msg_ctl \|= (SPI_HD_R << bs->msg_type_shift);
b17de076	195	else if (do_tx)
5a670445 FF	196	msg_ctl \|= (SPI_HD_W << bs->msg_type_shift);
	197
	198	switch (bs->msg_ctl_width) {
	199	case 8:
	200	bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
	201	break;
	202	case 16:
	203	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
	204	break;
	205	}
b42dfed8 FF	206
	207	/* Issue the transfer */
	208	cmd = SPI_CMD_START_IMMEDIATE;
b17de076	209	cmd \|= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
b42dfed8 FF	210	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
b42dfed8 FF	211	bcm_spi_writew(bs, cmd, SPI_CMD);
b42dfed8	212
cde4384e FF	213	/* Enable the CMD_DONE interrupt */
cde4384e FF	214	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
b42dfed8	215
c0fde3ba JG	216	timeout = wait_for_completion_timeout(&bs->done, HZ);
	217	if (!timeout)
	218	return -ETIMEDOUT;
	219
	220	/* read out all data */
	221	rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
	222
b17de076 JG	223	if (do_rx && rx_tail != len)
	224	return -EIO;
	225
	226	if (!rx_tail)
	227	return 0;
	228
	229	len = 0;
	230	t = first;
c0fde3ba	231	/* Read out all the data */
b17de076 JG	232	for (i = 0; i < num_transfers; i++) {
	233	if (t->rx_buf)
	234	memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
	235
	236	if (t != first \|\| prepend_len == 0)
	237	len += t->len;
	238
	239	t = list_entry(t->transfer_list.next, struct spi_transfer,
	240	transfer_list);
	241	}
c0fde3ba JG	242
c0fde3ba JG	243	return 0;
b42dfed8 FF	244	}
b42dfed8 FF	245
cde4384e	246	static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
b42dfed8	247	{
cde4384e	248	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8	249
cde4384e	250	pm_runtime_get_sync(&bs->pdev->dev);
b42dfed8	251
cde4384e FF	252	return 0;
	253	}
	254
	255	static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
	256	{
	257	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	258
	259	pm_runtime_put(&bs->pdev->dev);
	260
	261	return 0;
	262	}
	263
	264	static int bcm63xx_spi_transfer_one(struct spi_master *master,
	265	struct spi_message *m)
	266	{
	267	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b17de076	268	struct spi_transfer t, first = NULL;
cde4384e FF	269	struct spi_device *spi = m->spi;
cde4384e FF	270	int status = 0;
b17de076 JG	271	unsigned int n_transfers = 0, total_len = 0;
	272	bool can_use_prepend = false;
	273
	274	/*
	275	* This SPI controller does not support keeping CS active after a
	276	* transfer.
	277	* Work around this by merging as many transfers we can into one big
	278	* full-duplex transfers.
	279	*/
b42dfed8	280	list_for_each_entry(t, &m->transfers, transfer_list) {
c94df495 JG	281	if (t->bits_per_word != 8) {
	282	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
	283	__func__, t->bits_per_word);
	284	status = -EINVAL;
cde4384e	285	goto exit;
c94df495	286	}
cde4384e	287
b17de076 JG	288	if (!first)
	289	first = t;
	290
	291	n_transfers++;
	292	total_len += t->len;
	293
	294	if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
	295	first->len <= BCM63XX_SPI_MAX_PREPEND)
	296	can_use_prepend = true;
	297	else if (can_use_prepend && t->tx_buf)
	298	can_use_prepend = false;
	299
c0fde3ba	300	/* we can only transfer one fifo worth of data */
b17de076 JG	301	if ((can_use_prepend &&
	302	total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) \|\|
	303	(!can_use_prepend && total_len > bs->fifo_size)) {
c0fde3ba	304	dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
b17de076	305	total_len, bs->fifo_size);
c0fde3ba JG	306	status = -EINVAL;
	307	goto exit;
	308	}
cde4384e	309
b17de076 JG	310	/* all combined transfers have to have the same speed */
	311	if (t->speed_hz != first->speed_hz) {
	312	dev_err(&spi->dev, "unable to change speed between transfers\n");
c0fde3ba JG	313	status = -EINVAL;
	314	goto exit;
	315	}
cde4384e	316
b17de076 JG	317	/* CS will be deasserted directly after transfer */
	318	if (t->delay_usecs) {
	319	dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
c0fde3ba JG	320	status = -EINVAL;
	321	goto exit;
	322	}
cde4384e	323
b17de076 JG	324	if (t->cs_change \|\|
	325	list_is_last(&t->transfer_list, &m->transfers)) {
	326	/* configure adapter for a new transfer */
	327	bcm63xx_spi_setup_transfer(spi, first);
cde4384e	328
b17de076 JG	329	/* send the data */
	330	status = bcm63xx_txrx_bufs(spi, first, n_transfers);
	331	if (status)
	332	goto exit;
	333
	334	m->actual_length += total_len;
b42dfed8	335
b17de076 JG	336	first = NULL;
	337	n_transfers = 0;
	338	total_len = 0;
	339	can_use_prepend = false;
	340	}
cde4384e FF	341	}
	342	exit:
	343	m->status = status;
	344	spi_finalize_current_message(master);
b42dfed8	345
cde4384e	346	return 0;
b42dfed8 FF	347	}
	348
	349	/* This driver supports single master mode only. Hence
	350	* CMD_DONE is the only interrupt we care about
	351	*/
	352	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
	353	{
	354	struct spi_master master = (struct spi_master )dev_id;
	355	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	356	u8 intr;
b42dfed8 FF	357
	358	/* Read interupts and clear them immediately */
	359	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	360	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	361	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	362
cde4384e FF	363	/* A transfer completed */
	364	if (intr & SPI_INTR_CMD_DONE)
	365	complete(&bs->done);
b42dfed8 FF	366
	367	return IRQ_HANDLED;
	368	}
	369
	370
fd4a319b	371	static int bcm63xx_spi_probe(struct platform_device *pdev)
b42dfed8 FF	372	{
	373	struct resource *r;
	374	struct device *dev = &pdev->dev;
	375	struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
	376	int irq;
	377	struct spi_master *master;
	378	struct clk *clk;
	379	struct bcm63xx_spi *bs;
	380	int ret;
	381
	382	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	383	if (!r) {
	384	dev_err(dev, "no iomem\n");
	385	ret = -ENXIO;
	386	goto out;
	387	}
	388
	389	irq = platform_get_irq(pdev, 0);
	390	if (irq < 0) {
	391	dev_err(dev, "no irq\n");
	392	ret = -ENXIO;
	393	goto out;
	394	}
	395
	396	clk = clk_get(dev, "spi");
	397	if (IS_ERR(clk)) {
	398	dev_err(dev, "no clock for device\n");
	399	ret = PTR_ERR(clk);
	400	goto out;
	401	}
	402
	403	master = spi_alloc_master(dev, sizeof(*bs));
	404	if (!master) {
	405	dev_err(dev, "out of memory\n");
	406	ret = -ENOMEM;
	407	goto out_clk;
	408	}
	409
	410	bs = spi_master_get_devdata(master);
b42dfed8 FF	411
	412	platform_set_drvdata(pdev, master);
	413	bs->pdev = pdev;
	414
	415	if (!devm_request_mem_region(&pdev->dev, r->start,
	416	resource_size(r), PFX)) {
	417	dev_err(dev, "iomem request failed\n");
	418	ret = -ENXIO;
	419	goto out_err;
	420	}
	421
	422	bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
	423	resource_size(r));
	424	if (!bs->regs) {
	425	dev_err(dev, "unable to ioremap regs\n");
	426	ret = -ENOMEM;
	427	goto out_err;
	428	}
	429
	430	bs->irq = irq;
	431	bs->clk = clk;
	432	bs->fifo_size = pdata->fifo_size;
	433
	434	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
	435	pdev->name, master);
	436	if (ret) {
	437	dev_err(dev, "unable to request irq\n");
	438	goto out_err;
	439	}
	440
	441	master->bus_num = pdata->bus_num;
	442	master->num_chipselect = pdata->num_chipselect;
	443	master->setup = bcm63xx_spi_setup;
cde4384e FF	444	master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
	445	master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
	446	master->transfer_one_message = bcm63xx_spi_transfer_one;
88a3a255	447	master->mode_bits = MODEBITS;
b42dfed8	448	bs->speed_hz = pdata->speed_hz;
5a670445 FF	449	bs->msg_type_shift = pdata->msg_type_shift;
5a670445 FF	450	bs->msg_ctl_width = pdata->msg_ctl_width;
b42dfed8 FF	451	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
b42dfed8 FF	452	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
b42dfed8	453
5a670445 FF	454	switch (bs->msg_ctl_width) {
	455	case 8:
	456	case 16:
	457	break;
	458	default:
	459	dev_err(dev, "unsupported MSG_CTL width: %d\n",
	460	bs->msg_ctl_width);
b435ff21	461	goto out_err;
5a670445 FF	462	}
5a670445 FF	463
b42dfed8	464	/* Initialize hardware */
4fbb82a7	465	clk_prepare_enable(bs->clk);
b42dfed8 FF	466	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	467
	468	/* register and we are done */
	469	ret = spi_register_master(master);
	470	if (ret) {
	471	dev_err(dev, "spi register failed\n");
	472	goto out_clk_disable;
	473	}
	474
61d15963 FF	475	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
61d15963 FF	476	r->start, irq, bs->fifo_size);
b42dfed8 FF	477
	478	return 0;
	479
	480	out_clk_disable:
4fbb82a7	481	clk_disable_unprepare(clk);
b42dfed8 FF	482	out_err:
	483	platform_set_drvdata(pdev, NULL);
	484	spi_master_put(master);
	485	out_clk:
	486	clk_put(clk);
	487	out:
	488	return ret;
	489	}
	490
fd4a319b	491	static int bcm63xx_spi_remove(struct platform_device *pdev)
b42dfed8	492	{
1f682378	493	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
b42dfed8 FF	494	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8 FF	495
1e41dc0e FF	496	spi_unregister_master(master);
1e41dc0e FF	497
b42dfed8 FF	498	/* reset spi block */
b42dfed8 FF	499	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
b42dfed8 FF	500
b42dfed8 FF	501	/* HW shutdown */
4fbb82a7	502	clk_disable_unprepare(bs->clk);
b42dfed8 FF	503	clk_put(bs->clk);
b42dfed8 FF	504
b42dfed8	505	platform_set_drvdata(pdev, 0);
b42dfed8	506
1f682378 GR	507	spi_master_put(master);
1f682378 GR	508
b42dfed8 FF	509	return 0;
	510	}
	511
	512	#ifdef CONFIG_PM
	513	static int bcm63xx_spi_suspend(struct device *dev)
	514	{
	515	struct spi_master *master =
	516	platform_get_drvdata(to_platform_device(dev));
	517	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	518
96519957 FF	519	spi_master_suspend(master);
96519957 FF	520
4fbb82a7	521	clk_disable_unprepare(bs->clk);
b42dfed8 FF	522
	523	return 0;
	524	}
	525
	526	static int bcm63xx_spi_resume(struct device *dev)
	527	{
	528	struct spi_master *master =
	529	platform_get_drvdata(to_platform_device(dev));
	530	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	531
4fbb82a7	532	clk_prepare_enable(bs->clk);
b42dfed8	533
96519957 FF	534	spi_master_resume(master);
96519957 FF	535
b42dfed8 FF	536	return 0;
	537	}
	538
	539	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	540	.suspend = bcm63xx_spi_suspend,
	541	.resume = bcm63xx_spi_resume,
	542	};
	543
	544	#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
	545	#else
	546	#define BCM63XX_SPI_PM_OPS NULL
	547	#endif
	548
	549	static struct platform_driver bcm63xx_spi_driver = {
	550	.driver = {
	551	.name = "bcm63xx-spi",
	552	.owner = THIS_MODULE,
	553	.pm = BCM63XX_SPI_PM_OPS,
	554	},
	555	.probe = bcm63xx_spi_probe,
fd4a319b	556	.remove = bcm63xx_spi_remove,
b42dfed8 FF	557	};
	558
	559	module_platform_driver(bcm63xx_spi_driver);
	560
	561	MODULE_ALIAS("platform:bcm63xx_spi");
	562	MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
	563	MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
	564	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
	565	MODULE_LICENSE("GPL");