[deliverable/linux.git] / drivers / spi / spi-bcm63xx.c

/*
 * Broadcom BCM63xx SPI controller support
 *
 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the
 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/workqueue.h>
#include <linux/pm_runtime.h>

#include <bcm63xx_dev_spi.h>

#define PFX		KBUILD_MODNAME

#define BCM63XX_SPI_MAX_PREPEND		15

struct bcm63xx_spi {
	struct completion	done;

	void __iomem		*regs;
	int			irq;

	/* Platform data */
	unsigned		fifo_size;
	unsigned int		msg_type_shift;
	unsigned int		msg_ctl_width;

	/* data iomem */
	u8 __iomem		*tx_io;
	const u8 __iomem	*rx_io;

	struct clk		*clk;
	struct platform_device	*pdev;
};

static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
}

static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
				  u8 value, unsigned int offset)
{
	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
				  u16 value, unsigned int offset)
{
	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
}

static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	{ 20000000, SPI_CLK_20MHZ },
	{ 12500000, SPI_CLK_12_50MHZ },
	{  6250000, SPI_CLK_6_250MHZ },
	{  3125000, SPI_CLK_3_125MHZ },
	{  1563000, SPI_CLK_1_563MHZ },
	{   781000, SPI_CLK_0_781MHZ },
	{   391000, SPI_CLK_0_391MHZ }
};

static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
				      struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u8 clk_cfg, reg;
	int i;

	/* Find the closest clock configuration */
	for (i = 0; i < SPI_CLK_MASK; i++) {
		if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
			clk_cfg = bcm63xx_spi_freq_table[i][1];
			break;
		}
	}

	/* No matching configuration found, default to lowest */
	if (i == SPI_CLK_MASK)
		clk_cfg = SPI_CLK_0_391MHZ;

	/* clear existing clock configuration bits of the register */
	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	reg &= ~SPI_CLK_MASK;
	reg |= clk_cfg;

	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
		clk_cfg, t->speed_hz);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)

static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
				unsigned int num_transfers)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u16 msg_ctl;
	u16 cmd;
	u8 rx_tail;
	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	struct spi_transfer *t = first;
	bool do_rx = false;
	bool do_tx = false;

	/* Disable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
		prepend_len = t->len;

	/* prepare the buffer */
	for (i = 0; i < num_transfers; i++) {
		if (t->tx_buf) {
			do_tx = true;
			memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);

			/* don't prepend more than one tx */
			if (t != first)
				prepend_len = 0;
		}

		if (t->rx_buf) {
			do_rx = true;
			/* prepend is half-duplex write only */
			if (t == first)
				prepend_len = 0;
		}

		len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	len -= prepend_len;

	init_completion(&bs->done);

	/* Fill in the Message control register */
	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);

	if (do_rx && do_tx && prepend_len == 0)
		msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
	else if (do_rx)
		msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
	else if (do_tx)
		msg_ctl |= (SPI_HD_W << bs->msg_type_shift);

	switch (bs->msg_ctl_width) {
	case 8:
		bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
		break;
	case 16:
		bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
		break;
	}

	/* Issue the transfer */
	cmd = SPI_CMD_START_IMMEDIATE;
	cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	bcm_spi_writew(bs, cmd, SPI_CMD);

	/* Enable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);

	timeout = wait_for_completion_timeout(&bs->done, HZ);
	if (!timeout)
		return -ETIMEDOUT;

	if (!do_rx)
		return 0;

	len = 0;
	t = first;
	/* Read out all the data */
	for (i = 0; i < num_transfers; i++) {
		if (t->rx_buf)
			memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);

		if (t != first || prepend_len == 0)
			len += t->len;

		t = list_entry(t->transfer_list.next, struct spi_transfer,
			       transfer_list);
	}

	return 0;
}

static int bcm63xx_spi_transfer_one(struct spi_master *master,
					struct spi_message *m)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t, *first = NULL;
	struct spi_device *spi = m->spi;
	int status = 0;
	unsigned int n_transfers = 0, total_len = 0;
	bool can_use_prepend = false;

	/*
	 * This SPI controller does not support keeping CS active after a
	 * transfer.
	 * Work around this by merging as many transfers we can into one big
	 * full-duplex transfers.
	 */
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (!first)
			first = t;

		n_transfers++;
		total_len += t->len;

		if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
		    first->len <= BCM63XX_SPI_MAX_PREPEND)
			can_use_prepend = true;
		else if (can_use_prepend && t->tx_buf)
			can_use_prepend = false;

		/* we can only transfer one fifo worth of data */
		if ((can_use_prepend &&
		     total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
		    (!can_use_prepend && total_len > bs->fifo_size)) {
			dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
				total_len, bs->fifo_size);
			status = -EINVAL;
			goto exit;
		}

		/* all combined transfers have to have the same speed */
		if (t->speed_hz != first->speed_hz) {
			dev_err(&spi->dev, "unable to change speed between transfers\n");
			status = -EINVAL;
			goto exit;
		}

		/* CS will be deasserted directly after transfer */
		if (t->delay_usecs) {
			dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
			status = -EINVAL;
			goto exit;
		}

		if (t->cs_change ||
		    list_is_last(&t->transfer_list, &m->transfers)) {
			/* configure adapter for a new transfer */
			bcm63xx_spi_setup_transfer(spi, first);

			/* send the data */
			status = bcm63xx_txrx_bufs(spi, first, n_transfers);
			if (status)
				goto exit;

			m->actual_length += total_len;

			first = NULL;
			n_transfers = 0;
			total_len = 0;
			can_use_prepend = false;
		}
	}
exit:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

/* This driver supports single master mode only. Hence
 * CMD_DONE is the only interrupt we care about
 */
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = (struct spi_master *)dev_id;
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	u8 intr;

	/* Read interupts and clear them immediately */
	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* A transfer completed */
	if (intr & SPI_INTR_CMD_DONE)
		complete(&bs->done);

	return IRQ_HANDLED;
}


static int bcm63xx_spi_probe(struct platform_device *pdev)
{
	struct resource *r;
	struct device *dev = &pdev->dev;
	struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
	int irq;
	struct spi_master *master;
	struct clk *clk;
	struct bcm63xx_spi *bs;
	int ret;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq\n");
		return -ENXIO;
	}

	clk = devm_clk_get(dev, "spi");
	if (IS_ERR(clk)) {
		dev_err(dev, "no clock for device\n");
		return PTR_ERR(clk);
	}

	master = spi_alloc_master(dev, sizeof(*bs));
	if (!master) {
		dev_err(dev, "out of memory\n");
		return -ENOMEM;
	}

	bs = spi_master_get_devdata(master);

	platform_set_drvdata(pdev, master);
	bs->pdev = pdev;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(bs->regs)) {
		ret = PTR_ERR(bs->regs);
		goto out_err;
	}

	bs->irq = irq;
	bs->clk = clk;
	bs->fifo_size = pdata->fifo_size;

	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
							pdev->name, master);
	if (ret) {
		dev_err(dev, "unable to request irq\n");
		goto out_err;
	}

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;
	master->transfer_one_message = bcm63xx_spi_transfer_one;
	master->mode_bits = MODEBITS;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->auto_runtime_pm = true;
	bs->msg_type_shift = pdata->msg_type_shift;
	bs->msg_ctl_width = pdata->msg_ctl_width;
	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));

	switch (bs->msg_ctl_width) {
	case 8:
	case 16:
		break;
	default:
		dev_err(dev, "unsupported MSG_CTL width: %d\n",
			 bs->msg_ctl_width);
		goto out_err;
	}

	/* Initialize hardware */
	ret = clk_prepare_enable(bs->clk);
	if (ret)
		goto out_err;

	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);

	/* register and we are done */
	ret = devm_spi_register_master(dev, master);
	if (ret) {
		dev_err(dev, "spi register failed\n");
		goto out_clk_disable;
	}

	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
		 r->start, irq, bs->fifo_size);

	return 0;

out_clk_disable:
	clk_disable_unprepare(clk);
out_err:
	spi_master_put(master);
	return ret;
}

static int bcm63xx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	/* reset spi block */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* HW shutdown */
	clk_disable_unprepare(bs->clk);

	return 0;
}

#ifdef CONFIG_PM
static int bcm63xx_spi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);

	clk_disable_unprepare(bs->clk);

	return 0;
}

static int bcm63xx_spi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(bs->clk);
	if (ret)
		return ret;

	spi_master_resume(master);

	return 0;
}

static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	.suspend	= bcm63xx_spi_suspend,
	.resume		= bcm63xx_spi_resume,
};

#define BCM63XX_SPI_PM_OPS	(&bcm63xx_spi_pm_ops)
#else
#define BCM63XX_SPI_PM_OPS	NULL
#endif

static struct platform_driver bcm63xx_spi_driver = {
	.driver = {
		.name	= "bcm63xx-spi",
		.owner	= THIS_MODULE,
		.pm	= BCM63XX_SPI_PM_OPS,
	},
	.probe		= bcm63xx_spi_probe,
	.remove		= bcm63xx_spi_remove,
};

module_platform_driver(bcm63xx_spi_driver);

MODULE_ALIAS("platform:bcm63xx_spi");
MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b42dfed8 FF	1	/*
	2	* Broadcom BCM63xx SPI controller support
	3	*
cde4384e	4	* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
b42dfed8 FF	5	* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version 2
	10	* of the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the
	19	* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
	24	#include <linux/clk.h>
	25	#include <linux/io.h>
	26	#include <linux/module.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/delay.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/spi/spi.h>
	31	#include <linux/completion.h>
	32	#include <linux/err.h>
cde4384e FF	33	#include <linux/workqueue.h>
cde4384e FF	34	#include <linux/pm_runtime.h>
b42dfed8 FF	35
	36	#include <bcm63xx_dev_spi.h>
	37
	38	#define PFX KBUILD_MODNAME
b42dfed8	39
b17de076 JG	40	#define BCM63XX_SPI_MAX_PREPEND 15
b17de076 JG	41
b42dfed8	42	struct bcm63xx_spi {
b42dfed8 FF	43	struct completion done;
	44
	45	void __iomem *regs;
	46	int irq;
	47
	48	/* Platform data */
b42dfed8	49	unsigned fifo_size;
5a670445 FF	50	unsigned int msg_type_shift;
5a670445 FF	51	unsigned int msg_ctl_width;
b42dfed8	52
b42dfed8 FF	53	/* data iomem */
	54	u8 __iomem *tx_io;
	55	const u8 __iomem *rx_io;
	56
b42dfed8 FF	57	struct clk *clk;
	58	struct platform_device *pdev;
	59	};
	60
	61	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
	62	unsigned int offset)
	63	{
	64	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
	65	}
	66
	67	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
	68	unsigned int offset)
	69	{
	70	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
	71	}
	72
	73	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
	74	u8 value, unsigned int offset)
	75	{
	76	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
	77	}
	78
	79	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
	80	u16 value, unsigned int offset)
	81	{
	82	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
	83	}
	84
	85	static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	86	{ 20000000, SPI_CLK_20MHZ },
	87	{ 12500000, SPI_CLK_12_50MHZ },
	88	{ 6250000, SPI_CLK_6_250MHZ },
	89	{ 3125000, SPI_CLK_3_125MHZ },
	90	{ 1563000, SPI_CLK_1_563MHZ },
	91	{ 781000, SPI_CLK_0_781MHZ },
	92	{ 391000, SPI_CLK_0_391MHZ }
	93	};
	94
cde4384e FF	95	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
	96	struct spi_transfer *t)
	97	{
	98	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
cde4384e FF	99	u8 clk_cfg, reg;
	100	int i;
	101
b42dfed8 FF	102	/* Find the closest clock configuration */
b42dfed8 FF	103	for (i = 0; i < SPI_CLK_MASK; i++) {
68792e2a	104	if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
b42dfed8 FF	105	clk_cfg = bcm63xx_spi_freq_table[i][1];
	106	break;
	107	}
	108	}
	109
	110	/* No matching configuration found, default to lowest */
	111	if (i == SPI_CLK_MASK)
	112	clk_cfg = SPI_CLK_0_391MHZ;
	113
	114	/* clear existing clock configuration bits of the register */
	115	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	116	reg &= ~SPI_CLK_MASK;
	117	reg \|= clk_cfg;
	118
	119	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	120	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
68792e2a	121	clk_cfg, t->speed_hz);
b42dfed8 FF	122	}
	123
	124	/* the spi->mode bits understood by this driver: */
	125	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
	126
b17de076 JG	127	static int bcm63xx_txrx_bufs(struct spi_device spi, struct spi_transfer first,
b17de076 JG	128	unsigned int num_transfers)
b42dfed8 FF	129	{
	130	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	131	u16 msg_ctl;
	132	u16 cmd;
c0fde3ba	133	u8 rx_tail;
b17de076 JG	134	unsigned int i, timeout = 0, prepend_len = 0, len = 0;
	135	struct spi_transfer *t = first;
	136	bool do_rx = false;
	137	bool do_tx = false;
b42dfed8	138
cde4384e FF	139	/* Disable the CMD_DONE interrupt */
	140	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	141
b42dfed8 FF	142	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	143	t->tx_buf, t->rx_buf, t->len);
	144
b17de076 JG	145	if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
	146	prepend_len = t->len;
	147
	148	/* prepare the buffer */
	149	for (i = 0; i < num_transfers; i++) {
	150	if (t->tx_buf) {
	151	do_tx = true;
	152	memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
	153
	154	/* don't prepend more than one tx */
	155	if (t != first)
	156	prepend_len = 0;
	157	}
	158
	159	if (t->rx_buf) {
	160	do_rx = true;
	161	/* prepend is half-duplex write only */
	162	if (t == first)
	163	prepend_len = 0;
	164	}
	165
	166	len += t->len;
	167
	168	t = list_entry(t->transfer_list.next, struct spi_transfer,
	169	transfer_list);
	170	}
	171
	172	len -= prepend_len;
b42dfed8	173
cde4384e	174	init_completion(&bs->done);
b42dfed8 FF	175
b42dfed8 FF	176	/* Fill in the Message control register */
b17de076	177	msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
b42dfed8	178
b17de076	179	if (do_rx && do_tx && prepend_len == 0)
5a670445	180	msg_ctl \|= (SPI_FD_RW << bs->msg_type_shift);
b17de076	181	else if (do_rx)
5a670445	182	msg_ctl \|= (SPI_HD_R << bs->msg_type_shift);
b17de076	183	else if (do_tx)
5a670445 FF	184	msg_ctl \|= (SPI_HD_W << bs->msg_type_shift);
	185
	186	switch (bs->msg_ctl_width) {
	187	case 8:
	188	bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
	189	break;
	190	case 16:
	191	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
	192	break;
	193	}
b42dfed8 FF	194
	195	/* Issue the transfer */
	196	cmd = SPI_CMD_START_IMMEDIATE;
b17de076	197	cmd \|= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
b42dfed8 FF	198	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
b42dfed8 FF	199	bcm_spi_writew(bs, cmd, SPI_CMD);
b42dfed8	200
cde4384e FF	201	/* Enable the CMD_DONE interrupt */
cde4384e FF	202	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
b42dfed8	203
c0fde3ba JG	204	timeout = wait_for_completion_timeout(&bs->done, HZ);
	205	if (!timeout)
	206	return -ETIMEDOUT;
	207
20e9e78f	208	if (!do_rx)
b17de076 JG	209	return 0;
	210
	211	len = 0;
	212	t = first;
c0fde3ba	213	/* Read out all the data */
b17de076 JG	214	for (i = 0; i < num_transfers; i++) {
	215	if (t->rx_buf)
	216	memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
	217
	218	if (t != first \|\| prepend_len == 0)
	219	len += t->len;
	220
	221	t = list_entry(t->transfer_list.next, struct spi_transfer,
	222	transfer_list);
	223	}
c0fde3ba JG	224
c0fde3ba JG	225	return 0;
b42dfed8 FF	226	}
b42dfed8 FF	227
cde4384e FF	228	static int bcm63xx_spi_transfer_one(struct spi_master *master,
	229	struct spi_message *m)
	230	{
	231	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b17de076	232	struct spi_transfer t, first = NULL;
cde4384e FF	233	struct spi_device *spi = m->spi;
cde4384e FF	234	int status = 0;
b17de076 JG	235	unsigned int n_transfers = 0, total_len = 0;
	236	bool can_use_prepend = false;
	237
	238	/*
	239	* This SPI controller does not support keeping CS active after a
	240	* transfer.
	241	* Work around this by merging as many transfers we can into one big
	242	* full-duplex transfers.
	243	*/
b42dfed8	244	list_for_each_entry(t, &m->transfers, transfer_list) {
b17de076 JG	245	if (!first)
	246	first = t;
	247
	248	n_transfers++;
	249	total_len += t->len;
	250
	251	if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
	252	first->len <= BCM63XX_SPI_MAX_PREPEND)
	253	can_use_prepend = true;
	254	else if (can_use_prepend && t->tx_buf)
	255	can_use_prepend = false;
	256
c0fde3ba	257	/* we can only transfer one fifo worth of data */
b17de076 JG	258	if ((can_use_prepend &&
	259	total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) \|\|
	260	(!can_use_prepend && total_len > bs->fifo_size)) {
c0fde3ba	261	dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
b17de076	262	total_len, bs->fifo_size);
c0fde3ba JG	263	status = -EINVAL;
	264	goto exit;
	265	}
cde4384e	266
b17de076 JG	267	/* all combined transfers have to have the same speed */
	268	if (t->speed_hz != first->speed_hz) {
	269	dev_err(&spi->dev, "unable to change speed between transfers\n");
c0fde3ba JG	270	status = -EINVAL;
	271	goto exit;
	272	}
cde4384e	273
b17de076 JG	274	/* CS will be deasserted directly after transfer */
	275	if (t->delay_usecs) {
	276	dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
c0fde3ba JG	277	status = -EINVAL;
	278	goto exit;
	279	}
cde4384e	280
b17de076 JG	281	if (t->cs_change \|\|
	282	list_is_last(&t->transfer_list, &m->transfers)) {
	283	/* configure adapter for a new transfer */
	284	bcm63xx_spi_setup_transfer(spi, first);
cde4384e	285
b17de076 JG	286	/* send the data */
	287	status = bcm63xx_txrx_bufs(spi, first, n_transfers);
	288	if (status)
	289	goto exit;
	290
	291	m->actual_length += total_len;
b42dfed8	292
b17de076 JG	293	first = NULL;
	294	n_transfers = 0;
	295	total_len = 0;
	296	can_use_prepend = false;
	297	}
cde4384e FF	298	}
	299	exit:
	300	m->status = status;
	301	spi_finalize_current_message(master);
b42dfed8	302
cde4384e	303	return 0;
b42dfed8 FF	304	}
	305
	306	/* This driver supports single master mode only. Hence
	307	* CMD_DONE is the only interrupt we care about
	308	*/
	309	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
	310	{
	311	struct spi_master master = (struct spi_master )dev_id;
	312	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	313	u8 intr;
b42dfed8 FF	314
	315	/* Read interupts and clear them immediately */
	316	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	317	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	318	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	319
cde4384e FF	320	/* A transfer completed */
	321	if (intr & SPI_INTR_CMD_DONE)
	322	complete(&bs->done);
b42dfed8 FF	323
	324	return IRQ_HANDLED;
	325	}
	326
	327
fd4a319b	328	static int bcm63xx_spi_probe(struct platform_device *pdev)
b42dfed8 FF	329	{
	330	struct resource *r;
	331	struct device *dev = &pdev->dev;
8074cf06	332	struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
b42dfed8 FF	333	int irq;
	334	struct spi_master *master;
	335	struct clk *clk;
	336	struct bcm63xx_spi *bs;
	337	int ret;
	338
b42dfed8 FF	339	irq = platform_get_irq(pdev, 0);
	340	if (irq < 0) {
	341	dev_err(dev, "no irq\n");
acf4fc6f	342	return -ENXIO;
b42dfed8 FF	343	}
b42dfed8 FF	344
acf4fc6f	345	clk = devm_clk_get(dev, "spi");
b42dfed8 FF	346	if (IS_ERR(clk)) {
b42dfed8 FF	347	dev_err(dev, "no clock for device\n");
acf4fc6f	348	return PTR_ERR(clk);
b42dfed8 FF	349	}
	350
	351	master = spi_alloc_master(dev, sizeof(*bs));
	352	if (!master) {
	353	dev_err(dev, "out of memory\n");
acf4fc6f	354	return -ENOMEM;
b42dfed8 FF	355	}
	356
	357	bs = spi_master_get_devdata(master);
b42dfed8 FF	358
	359	platform_set_drvdata(pdev, master);
	360	bs->pdev = pdev;
	361
de0fa83c	362	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b66c7730 JG	363	bs->regs = devm_ioremap_resource(&pdev->dev, r);
	364	if (IS_ERR(bs->regs)) {
	365	ret = PTR_ERR(bs->regs);
b42dfed8 FF	366	goto out_err;
	367	}
	368
	369	bs->irq = irq;
	370	bs->clk = clk;
	371	bs->fifo_size = pdata->fifo_size;
	372
	373	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
	374	pdev->name, master);
	375	if (ret) {
	376	dev_err(dev, "unable to request irq\n");
	377	goto out_err;
	378	}
	379
	380	master->bus_num = pdata->bus_num;
	381	master->num_chipselect = pdata->num_chipselect;
cde4384e	382	master->transfer_one_message = bcm63xx_spi_transfer_one;
88a3a255	383	master->mode_bits = MODEBITS;
24778be2	384	master->bits_per_word_mask = SPI_BPW_MASK(8);
5355d96d	385	master->auto_runtime_pm = true;
5a670445 FF	386	bs->msg_type_shift = pdata->msg_type_shift;
5a670445 FF	387	bs->msg_ctl_width = pdata->msg_ctl_width;
b42dfed8 FF	388	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
b42dfed8 FF	389	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
b42dfed8	390
5a670445 FF	391	switch (bs->msg_ctl_width) {
	392	case 8:
	393	case 16:
	394	break;
	395	default:
	396	dev_err(dev, "unsupported MSG_CTL width: %d\n",
	397	bs->msg_ctl_width);
b435ff21	398	goto out_err;
5a670445 FF	399	}
5a670445 FF	400
b42dfed8	401	/* Initialize hardware */
ea01e8a4 JG	402	ret = clk_prepare_enable(bs->clk);
	403	if (ret)
	404	goto out_err;
	405
b42dfed8 FF	406	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	407
	408	/* register and we are done */
bca76931	409	ret = devm_spi_register_master(dev, master);
b42dfed8 FF	410	if (ret) {
	411	dev_err(dev, "spi register failed\n");
	412	goto out_clk_disable;
	413	}
	414
61d15963 FF	415	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
61d15963 FF	416	r->start, irq, bs->fifo_size);
b42dfed8 FF	417
	418	return 0;
	419
	420	out_clk_disable:
4fbb82a7	421	clk_disable_unprepare(clk);
b42dfed8	422	out_err:
b42dfed8	423	spi_master_put(master);
b42dfed8 FF	424	return ret;
	425	}
	426
fd4a319b	427	static int bcm63xx_spi_remove(struct platform_device *pdev)
b42dfed8	428	{
1f682378	429	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
b42dfed8 FF	430	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	431
	432	/* reset spi block */
	433	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
b42dfed8 FF	434
b42dfed8 FF	435	/* HW shutdown */
4fbb82a7	436	clk_disable_unprepare(bs->clk);
b42dfed8	437
b42dfed8 FF	438	return 0;
	439	}
	440
	441	#ifdef CONFIG_PM
	442	static int bcm63xx_spi_suspend(struct device *dev)
	443	{
a1216394	444	struct spi_master *master = dev_get_drvdata(dev);
b42dfed8 FF	445	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8 FF	446
96519957 FF	447	spi_master_suspend(master);
96519957 FF	448
4fbb82a7	449	clk_disable_unprepare(bs->clk);
b42dfed8 FF	450
	451	return 0;
	452	}
	453
	454	static int bcm63xx_spi_resume(struct device *dev)
	455	{
a1216394	456	struct spi_master *master = dev_get_drvdata(dev);
b42dfed8	457	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
ea01e8a4	458	int ret;
b42dfed8	459
ea01e8a4 JG	460	ret = clk_prepare_enable(bs->clk);
	461	if (ret)
	462	return ret;
b42dfed8	463
96519957 FF	464	spi_master_resume(master);
96519957 FF	465
b42dfed8 FF	466	return 0;
	467	}
	468
	469	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	470	.suspend = bcm63xx_spi_suspend,
	471	.resume = bcm63xx_spi_resume,
	472	};
	473
	474	#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
	475	#else
	476	#define BCM63XX_SPI_PM_OPS NULL
	477	#endif
	478
	479	static struct platform_driver bcm63xx_spi_driver = {
	480	.driver = {
	481	.name = "bcm63xx-spi",
	482	.owner = THIS_MODULE,
	483	.pm = BCM63XX_SPI_PM_OPS,
	484	},
	485	.probe = bcm63xx_spi_probe,
fd4a319b	486	.remove = bcm63xx_spi_remove,
b42dfed8 FF	487	};
	488
	489	module_platform_driver(bcm63xx_spi_driver);
	490
	491	MODULE_ALIAS("platform:bcm63xx_spi");
	492	MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
	493	MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
	494	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
	495	MODULE_LICENSE("GPL");