Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
9c0a788b | 4 | * Copyright 2004-2010 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
131b17d4 | 16 | #include <linux/io.h> |
a5f6abd4 | 17 | #include <linux/ioport.h> |
131b17d4 | 18 | #include <linux/irq.h> |
a5f6abd4 WB |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/workqueue.h> | |
a5f6abd4 | 25 | |
a5f6abd4 | 26 | #include <asm/dma.h> |
131b17d4 | 27 | #include <asm/portmux.h> |
a5f6abd4 | 28 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
29 | #include <asm/cacheflush.h> |
30 | ||
a32c691d BW |
31 | #define DRV_NAME "bfin-spi" |
32 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 33 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
34 | #define DRV_VERSION "1.0" |
35 | ||
36 | MODULE_AUTHOR(DRV_AUTHOR); | |
37 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
38 | MODULE_LICENSE("GPL"); |
39 | ||
bb90eb00 BW |
40 | #define START_STATE ((void *)0) |
41 | #define RUNNING_STATE ((void *)1) | |
42 | #define DONE_STATE ((void *)2) | |
43 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 44 | |
9c0a788b | 45 | struct bfin_spi_master_data; |
9c4542c7 | 46 | |
9c0a788b MF |
47 | struct bfin_spi_transfer_ops { |
48 | void (*write) (struct bfin_spi_master_data *); | |
49 | void (*read) (struct bfin_spi_master_data *); | |
50 | void (*duplex) (struct bfin_spi_master_data *); | |
9c4542c7 MF |
51 | }; |
52 | ||
9c0a788b | 53 | struct bfin_spi_master_data { |
a5f6abd4 WB |
54 | /* Driver model hookup */ |
55 | struct platform_device *pdev; | |
56 | ||
57 | /* SPI framework hookup */ | |
58 | struct spi_master *master; | |
59 | ||
bb90eb00 | 60 | /* Regs base of SPI controller */ |
47885ce8 | 61 | struct bfin_spi_regs __iomem *regs; |
bb90eb00 | 62 | |
003d9226 BW |
63 | /* Pin request list */ |
64 | u16 *pin_req; | |
65 | ||
a5f6abd4 WB |
66 | /* BFIN hookup */ |
67 | struct bfin5xx_spi_master *master_info; | |
68 | ||
69 | /* Driver message queue */ | |
70 | struct workqueue_struct *workqueue; | |
71 | struct work_struct pump_messages; | |
72 | spinlock_t lock; | |
73 | struct list_head queue; | |
74 | int busy; | |
f4f50c3f | 75 | bool running; |
a5f6abd4 WB |
76 | |
77 | /* Message Transfer pump */ | |
78 | struct tasklet_struct pump_transfers; | |
79 | ||
80 | /* Current message transfer state info */ | |
81 | struct spi_message *cur_msg; | |
82 | struct spi_transfer *cur_transfer; | |
9c0a788b | 83 | struct bfin_spi_slave_data *cur_chip; |
a5f6abd4 WB |
84 | size_t len_in_bytes; |
85 | size_t len; | |
86 | void *tx; | |
87 | void *tx_end; | |
88 | void *rx; | |
89 | void *rx_end; | |
bb90eb00 BW |
90 | |
91 | /* DMA stuffs */ | |
92 | int dma_channel; | |
a5f6abd4 | 93 | int dma_mapped; |
bb90eb00 | 94 | int dma_requested; |
a5f6abd4 WB |
95 | dma_addr_t rx_dma; |
96 | dma_addr_t tx_dma; | |
bb90eb00 | 97 | |
f6a6d966 YL |
98 | int irq_requested; |
99 | int spi_irq; | |
100 | ||
a5f6abd4 WB |
101 | size_t rx_map_len; |
102 | size_t tx_map_len; | |
103 | u8 n_bytes; | |
b052fd0a BS |
104 | u16 ctrl_reg; |
105 | u16 flag_reg; | |
106 | ||
fad91c89 | 107 | int cs_change; |
9c0a788b | 108 | const struct bfin_spi_transfer_ops *ops; |
a5f6abd4 WB |
109 | }; |
110 | ||
9c0a788b | 111 | struct bfin_spi_slave_data { |
a5f6abd4 WB |
112 | u16 ctl_reg; |
113 | u16 baud; | |
114 | u16 flag; | |
115 | ||
116 | u8 chip_select_num; | |
a5f6abd4 | 117 | u8 enable_dma; |
62310e51 | 118 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 119 | u32 cs_gpio; |
93b61bdd | 120 | u16 idle_tx_val; |
f6a6d966 | 121 | u8 pio_interrupt; /* use spi data irq */ |
9c0a788b | 122 | const struct bfin_spi_transfer_ops *ops; |
a5f6abd4 WB |
123 | }; |
124 | ||
9c0a788b | 125 | static void bfin_spi_enable(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 126 | { |
47885ce8 | 127 | bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE); |
a5f6abd4 WB |
128 | } |
129 | ||
9c0a788b | 130 | static void bfin_spi_disable(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 131 | { |
47885ce8 | 132 | bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE); |
a5f6abd4 WB |
133 | } |
134 | ||
135 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
136 | static u16 hz_to_spi_baud(u32 speed_hz) | |
137 | { | |
138 | u_long sclk = get_sclk(); | |
139 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
140 | ||
141 | if ((sclk % (2 * speed_hz)) > 0) | |
142 | spi_baud++; | |
143 | ||
7513e006 MH |
144 | if (spi_baud < MIN_SPI_BAUD_VAL) |
145 | spi_baud = MIN_SPI_BAUD_VAL; | |
146 | ||
a5f6abd4 WB |
147 | return spi_baud; |
148 | } | |
149 | ||
9c0a788b | 150 | static int bfin_spi_flush(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
151 | { |
152 | unsigned long limit = loops_per_jiffy << 1; | |
153 | ||
154 | /* wait for stop and clear stat */ | |
47885ce8 | 155 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 156 | cpu_relax(); |
a5f6abd4 | 157 | |
47885ce8 | 158 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
a5f6abd4 WB |
159 | |
160 | return limit; | |
161 | } | |
162 | ||
fad91c89 | 163 | /* Chip select operation functions for cs_change flag */ |
9c0a788b | 164 | static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip) |
fad91c89 | 165 | { |
47885ce8 MF |
166 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) |
167 | bfin_write_and(&drv_data->regs->flg, ~chip->flag); | |
168 | else | |
42c78b2b | 169 | gpio_set_value(chip->cs_gpio, 0); |
fad91c89 BW |
170 | } |
171 | ||
9c0a788b MF |
172 | static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data, |
173 | struct bfin_spi_slave_data *chip) | |
fad91c89 | 174 | { |
47885ce8 MF |
175 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) |
176 | bfin_write_or(&drv_data->regs->flg, chip->flag); | |
177 | else | |
42c78b2b | 178 | gpio_set_value(chip->cs_gpio, 1); |
62310e51 BW |
179 | |
180 | /* Move delay here for consistency */ | |
181 | if (chip->cs_chg_udelay) | |
182 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
183 | } |
184 | ||
8221610e | 185 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
9c0a788b MF |
186 | static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data, |
187 | struct bfin_spi_slave_data *chip) | |
8221610e | 188 | { |
47885ce8 MF |
189 | if (chip->chip_select_num < MAX_CTRL_CS) |
190 | bfin_write_or(&drv_data->regs->flg, chip->flag >> 8); | |
8221610e BS |
191 | } |
192 | ||
9c0a788b MF |
193 | static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data, |
194 | struct bfin_spi_slave_data *chip) | |
8221610e | 195 | { |
47885ce8 MF |
196 | if (chip->chip_select_num < MAX_CTRL_CS) |
197 | bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8)); | |
8221610e BS |
198 | } |
199 | ||
a5f6abd4 | 200 | /* stop controller and re-config current chip*/ |
9c0a788b | 201 | static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 202 | { |
9c0a788b | 203 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
12e17c42 | 204 | |
a5f6abd4 | 205 | /* Clear status and disable clock */ |
47885ce8 | 206 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
a5f6abd4 | 207 | bfin_spi_disable(drv_data); |
88b40369 | 208 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 209 | |
9677b0de BS |
210 | SSYNC(); |
211 | ||
5fec5b5a | 212 | /* Load the registers */ |
47885ce8 MF |
213 | bfin_write(&drv_data->regs->ctl, chip->ctl_reg); |
214 | bfin_write(&drv_data->regs->baud, chip->baud); | |
cc487e73 SZ |
215 | |
216 | bfin_spi_enable(drv_data); | |
138f97cd | 217 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
218 | } |
219 | ||
93b61bdd | 220 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
9c0a788b | 221 | static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 222 | { |
47885ce8 | 223 | (void) bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
224 | } |
225 | ||
9c0a788b | 226 | static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 227 | { |
93b61bdd WM |
228 | /* clear RXS (we check for RXS inside the loop) */ |
229 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 230 | |
a5f6abd4 | 231 | while (drv_data->tx < drv_data->tx_end) { |
47885ce8 | 232 | bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++))); |
93b61bdd WM |
233 | /* wait until transfer finished. |
234 | checking SPIF or TXS may not guarantee transfer completion */ | |
47885ce8 | 235 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
d8c05008 | 236 | cpu_relax(); |
93b61bdd WM |
237 | /* discard RX data and clear RXS */ |
238 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 239 | } |
a5f6abd4 WB |
240 | } |
241 | ||
9c0a788b | 242 | static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 243 | { |
93b61bdd | 244 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 245 | |
93b61bdd | 246 | /* discard old RX data and clear RXS */ |
138f97cd | 247 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 248 | |
93b61bdd | 249 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
250 | bfin_write(&drv_data->regs->tdbr, tx_val); |
251 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 252 | cpu_relax(); |
47885ce8 | 253 | *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 | 254 | } |
a5f6abd4 WB |
255 | } |
256 | ||
9c0a788b | 257 | static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 258 | { |
93b61bdd WM |
259 | /* discard old RX data and clear RXS */ |
260 | bfin_spi_dummy_read(drv_data); | |
261 | ||
a5f6abd4 | 262 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
263 | bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++))); |
264 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 265 | cpu_relax(); |
47885ce8 | 266 | *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
267 | } |
268 | } | |
269 | ||
9c0a788b | 270 | static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = { |
9c4542c7 MF |
271 | .write = bfin_spi_u8_writer, |
272 | .read = bfin_spi_u8_reader, | |
273 | .duplex = bfin_spi_u8_duplex, | |
274 | }; | |
275 | ||
9c0a788b | 276 | static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 277 | { |
93b61bdd WM |
278 | /* clear RXS (we check for RXS inside the loop) */ |
279 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 280 | |
a5f6abd4 | 281 | while (drv_data->tx < drv_data->tx_end) { |
47885ce8 | 282 | bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 283 | drv_data->tx += 2; |
93b61bdd WM |
284 | /* wait until transfer finished. |
285 | checking SPIF or TXS may not guarantee transfer completion */ | |
47885ce8 | 286 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
93b61bdd WM |
287 | cpu_relax(); |
288 | /* discard RX data and clear RXS */ | |
289 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 290 | } |
a5f6abd4 WB |
291 | } |
292 | ||
9c0a788b | 293 | static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 294 | { |
93b61bdd | 295 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 296 | |
93b61bdd | 297 | /* discard old RX data and clear RXS */ |
138f97cd | 298 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 299 | |
93b61bdd | 300 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
301 | bfin_write(&drv_data->regs->tdbr, tx_val); |
302 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 303 | cpu_relax(); |
47885ce8 | 304 | *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
305 | drv_data->rx += 2; |
306 | } | |
a5f6abd4 WB |
307 | } |
308 | ||
9c0a788b | 309 | static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 310 | { |
93b61bdd WM |
311 | /* discard old RX data and clear RXS */ |
312 | bfin_spi_dummy_read(drv_data); | |
313 | ||
314 | while (drv_data->rx < drv_data->rx_end) { | |
47885ce8 | 315 | bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx))); |
93b61bdd | 316 | drv_data->tx += 2; |
47885ce8 | 317 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
d8c05008 | 318 | cpu_relax(); |
47885ce8 | 319 | *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 | 320 | drv_data->rx += 2; |
a5f6abd4 WB |
321 | } |
322 | } | |
323 | ||
9c0a788b | 324 | static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = { |
9c4542c7 MF |
325 | .write = bfin_spi_u16_writer, |
326 | .read = bfin_spi_u16_reader, | |
327 | .duplex = bfin_spi_u16_duplex, | |
328 | }; | |
329 | ||
e3595405 | 330 | /* test if there is more transfer to be done */ |
9c0a788b | 331 | static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
332 | { |
333 | struct spi_message *msg = drv_data->cur_msg; | |
334 | struct spi_transfer *trans = drv_data->cur_transfer; | |
335 | ||
336 | /* Move to next transfer */ | |
337 | if (trans->transfer_list.next != &msg->transfers) { | |
338 | drv_data->cur_transfer = | |
339 | list_entry(trans->transfer_list.next, | |
340 | struct spi_transfer, transfer_list); | |
341 | return RUNNING_STATE; | |
342 | } else | |
343 | return DONE_STATE; | |
344 | } | |
345 | ||
346 | /* | |
347 | * caller already set message->status; | |
348 | * dma and pio irqs are blocked give finished message back | |
349 | */ | |
9c0a788b | 350 | static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 351 | { |
9c0a788b | 352 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
353 | struct spi_transfer *last_transfer; |
354 | unsigned long flags; | |
355 | struct spi_message *msg; | |
356 | ||
357 | spin_lock_irqsave(&drv_data->lock, flags); | |
358 | msg = drv_data->cur_msg; | |
359 | drv_data->cur_msg = NULL; | |
360 | drv_data->cur_transfer = NULL; | |
361 | drv_data->cur_chip = NULL; | |
362 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
363 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
364 | ||
365 | last_transfer = list_entry(msg->transfers.prev, | |
366 | struct spi_transfer, transfer_list); | |
367 | ||
368 | msg->state = NULL; | |
369 | ||
fad91c89 | 370 | if (!drv_data->cs_change) |
138f97cd | 371 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 372 | |
b9b2a76a YL |
373 | /* Not stop spi in autobuffer mode */ |
374 | if (drv_data->tx_dma != 0xFFFF) | |
375 | bfin_spi_disable(drv_data); | |
376 | ||
a5f6abd4 WB |
377 | if (msg->complete) |
378 | msg->complete(msg->context); | |
379 | } | |
380 | ||
f6a6d966 YL |
381 | /* spi data irq handler */ |
382 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
383 | { | |
9c0a788b MF |
384 | struct bfin_spi_master_data *drv_data = dev_id; |
385 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
386 | struct spi_message *msg = drv_data->cur_msg; |
387 | int n_bytes = drv_data->n_bytes; | |
4d676fc5 | 388 | int loop = 0; |
f6a6d966 YL |
389 | |
390 | /* wait until transfer finished. */ | |
47885ce8 | 391 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
f6a6d966 YL |
392 | cpu_relax(); |
393 | ||
394 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
395 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
396 | /* last read */ | |
397 | if (drv_data->rx) { | |
398 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
128465ca | 399 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
400 | u16 *buf = (u16 *)drv_data->rx; |
401 | for (loop = 0; loop < n_bytes / 2; loop++) | |
47885ce8 | 402 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
4d676fc5 BL |
403 | } else { |
404 | u8 *buf = (u8 *)drv_data->rx; | |
405 | for (loop = 0; loop < n_bytes; loop++) | |
47885ce8 | 406 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
4d676fc5 | 407 | } |
f6a6d966 YL |
408 | drv_data->rx += n_bytes; |
409 | } | |
410 | ||
411 | msg->actual_length += drv_data->len_in_bytes; | |
412 | if (drv_data->cs_change) | |
413 | bfin_spi_cs_deactive(drv_data, chip); | |
414 | /* Move to next transfer */ | |
415 | msg->state = bfin_spi_next_transfer(drv_data); | |
416 | ||
7370ed6b | 417 | disable_irq_nosync(drv_data->spi_irq); |
f6a6d966 YL |
418 | |
419 | /* Schedule transfer tasklet */ | |
420 | tasklet_schedule(&drv_data->pump_transfers); | |
421 | return IRQ_HANDLED; | |
422 | } | |
423 | ||
424 | if (drv_data->rx && drv_data->tx) { | |
425 | /* duplex */ | |
426 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
128465ca | 427 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
428 | u16 *buf = (u16 *)drv_data->rx; |
429 | u16 *buf2 = (u16 *)drv_data->tx; | |
430 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
431 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
432 | bfin_write(&drv_data->regs->tdbr, *buf2++); | |
4d676fc5 BL |
433 | } |
434 | } else { | |
435 | u8 *buf = (u8 *)drv_data->rx; | |
436 | u8 *buf2 = (u8 *)drv_data->tx; | |
437 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
438 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
439 | bfin_write(&drv_data->regs->tdbr, *buf2++); | |
4d676fc5 | 440 | } |
f6a6d966 YL |
441 | } |
442 | } else if (drv_data->rx) { | |
443 | /* read */ | |
444 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
128465ca | 445 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
446 | u16 *buf = (u16 *)drv_data->rx; |
447 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
448 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
449 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); | |
4d676fc5 BL |
450 | } |
451 | } else { | |
452 | u8 *buf = (u8 *)drv_data->rx; | |
453 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
454 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
455 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); | |
4d676fc5 BL |
456 | } |
457 | } | |
f6a6d966 YL |
458 | } else if (drv_data->tx) { |
459 | /* write */ | |
460 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
128465ca | 461 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
462 | u16 *buf = (u16 *)drv_data->tx; |
463 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
464 | bfin_read(&drv_data->regs->rdbr); |
465 | bfin_write(&drv_data->regs->tdbr, *buf++); | |
4d676fc5 BL |
466 | } |
467 | } else { | |
468 | u8 *buf = (u8 *)drv_data->tx; | |
469 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
470 | bfin_read(&drv_data->regs->rdbr); |
471 | bfin_write(&drv_data->regs->tdbr, *buf++); | |
4d676fc5 BL |
472 | } |
473 | } | |
f6a6d966 YL |
474 | } |
475 | ||
476 | if (drv_data->tx) | |
477 | drv_data->tx += n_bytes; | |
478 | if (drv_data->rx) | |
479 | drv_data->rx += n_bytes; | |
480 | ||
481 | return IRQ_HANDLED; | |
482 | } | |
483 | ||
138f97cd | 484 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 485 | { |
9c0a788b MF |
486 | struct bfin_spi_master_data *drv_data = dev_id; |
487 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 488 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 489 | unsigned long timeout; |
d24bd1d0 | 490 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
47885ce8 | 491 | u16 spistat = bfin_read(&drv_data->regs->stat); |
a5f6abd4 | 492 | |
d24bd1d0 MF |
493 | dev_dbg(&drv_data->pdev->dev, |
494 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
495 | dmastat, spistat); | |
496 | ||
782a8956 | 497 | if (drv_data->rx != NULL) { |
47885ce8 | 498 | u16 cr = bfin_read(&drv_data->regs->ctl); |
782a8956 MH |
499 | /* discard old RX data and clear RXS */ |
500 | bfin_spi_dummy_read(drv_data); | |
47885ce8 MF |
501 | bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */ |
502 | bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */ | |
503 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */ | |
782a8956 MH |
504 | } |
505 | ||
bb90eb00 | 506 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
507 | |
508 | /* | |
d6fe89b0 BW |
509 | * wait for the last transaction shifted out. HRM states: |
510 | * at this point there may still be data in the SPI DMA FIFO waiting | |
511 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
512 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
513 | */ |
514 | if (drv_data->tx != NULL) { | |
47885ce8 MF |
515 | while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) || |
516 | (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS)) | |
d8c05008 | 517 | cpu_relax(); |
a5f6abd4 WB |
518 | } |
519 | ||
aaaf939c MF |
520 | dev_dbg(&drv_data->pdev->dev, |
521 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
47885ce8 | 522 | dmastat, bfin_read(&drv_data->regs->stat)); |
aaaf939c MF |
523 | |
524 | timeout = jiffies + HZ; | |
47885ce8 | 525 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF)) |
aaaf939c MF |
526 | if (!time_before(jiffies, timeout)) { |
527 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
528 | break; | |
529 | } else | |
530 | cpu_relax(); | |
a5f6abd4 | 531 | |
90008a64 | 532 | if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) { |
04b95d2f MF |
533 | msg->state = ERROR_STATE; |
534 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
535 | } else { | |
536 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 537 | |
04b95d2f | 538 | if (drv_data->cs_change) |
138f97cd | 539 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 540 | |
04b95d2f | 541 | /* Move to next transfer */ |
138f97cd | 542 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 543 | } |
a5f6abd4 WB |
544 | |
545 | /* Schedule transfer tasklet */ | |
546 | tasklet_schedule(&drv_data->pump_transfers); | |
547 | ||
548 | /* free the irq handler before next transfer */ | |
88b40369 BW |
549 | dev_dbg(&drv_data->pdev->dev, |
550 | "disable dma channel irq%d\n", | |
bb90eb00 | 551 | drv_data->dma_channel); |
a75bd65b | 552 | dma_disable_irq_nosync(drv_data->dma_channel); |
a5f6abd4 WB |
553 | |
554 | return IRQ_HANDLED; | |
555 | } | |
556 | ||
138f97cd | 557 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 558 | { |
9c0a788b | 559 | struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data; |
a5f6abd4 WB |
560 | struct spi_message *message = NULL; |
561 | struct spi_transfer *transfer = NULL; | |
562 | struct spi_transfer *previous = NULL; | |
9c0a788b | 563 | struct bfin_spi_slave_data *chip = NULL; |
033f44bd | 564 | unsigned int bits_per_word; |
5e8592dc | 565 | u16 cr, cr_width, dma_width, dma_config; |
a5f6abd4 | 566 | u32 tranf_success = 1; |
8eeb12e5 | 567 | u8 full_duplex = 0; |
a5f6abd4 WB |
568 | |
569 | /* Get current state information */ | |
570 | message = drv_data->cur_msg; | |
571 | transfer = drv_data->cur_transfer; | |
572 | chip = drv_data->cur_chip; | |
092e1fda | 573 | |
a5f6abd4 WB |
574 | /* |
575 | * if msg is error or done, report it back using complete() callback | |
576 | */ | |
577 | ||
578 | /* Handle for abort */ | |
579 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 580 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 581 | message->status = -EIO; |
138f97cd | 582 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
583 | return; |
584 | } | |
585 | ||
586 | /* Handle end of message */ | |
587 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 588 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 589 | message->status = 0; |
2431a815 | 590 | bfin_spi_flush(drv_data); |
138f97cd | 591 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
592 | return; |
593 | } | |
594 | ||
595 | /* Delay if requested at end of transfer */ | |
596 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 597 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
598 | previous = list_entry(transfer->transfer_list.prev, |
599 | struct spi_transfer, transfer_list); | |
600 | if (previous->delay_usecs) | |
601 | udelay(previous->delay_usecs); | |
602 | } | |
603 | ||
ab09e040 | 604 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 605 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
606 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
607 | message->status = -EIO; | |
138f97cd | 608 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
609 | return; |
610 | } | |
611 | ||
93b61bdd WM |
612 | if (transfer->len == 0) { |
613 | /* Move to next transfer of this msg */ | |
614 | message->state = bfin_spi_next_transfer(drv_data); | |
615 | /* Schedule next transfer tasklet */ | |
616 | tasklet_schedule(&drv_data->pump_transfers); | |
1974eba6 | 617 | return; |
93b61bdd WM |
618 | } |
619 | ||
a5f6abd4 WB |
620 | if (transfer->tx_buf != NULL) { |
621 | drv_data->tx = (void *)transfer->tx_buf; | |
622 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
623 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
624 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
625 | } else { |
626 | drv_data->tx = NULL; | |
627 | } | |
628 | ||
629 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 630 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
631 | drv_data->rx = transfer->rx_buf; |
632 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
633 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
634 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
635 | } else { |
636 | drv_data->rx = NULL; | |
637 | } | |
638 | ||
639 | drv_data->rx_dma = transfer->rx_dma; | |
640 | drv_data->tx_dma = transfer->tx_dma; | |
641 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 642 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 643 | |
092e1fda | 644 | /* Bits per word setup */ |
766ed704 | 645 | bits_per_word = transfer->bits_per_word; |
24778be2 | 646 | if (bits_per_word == 16) { |
4d676fc5 | 647 | drv_data->n_bytes = bits_per_word/8; |
5e8592dc MF |
648 | drv_data->len = (transfer->len) >> 1; |
649 | cr_width = BIT_CTL_WORDSIZE; | |
9c0a788b | 650 | drv_data->ops = &bfin_bfin_spi_transfer_ops_u16; |
24778be2 | 651 | } else if (bits_per_word == 8) { |
4d676fc5 BL |
652 | drv_data->n_bytes = bits_per_word/8; |
653 | drv_data->len = transfer->len; | |
654 | cr_width = 0; | |
655 | drv_data->ops = &bfin_bfin_spi_transfer_ops_u8; | |
092e1fda | 656 | } |
47885ce8 | 657 | cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE); |
5e8592dc | 658 | cr |= cr_width; |
47885ce8 | 659 | bfin_write(&drv_data->regs->ctl, cr); |
092e1fda | 660 | |
4fb98efa | 661 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 | 662 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
9c0a788b | 663 | drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8); |
a5f6abd4 | 664 | |
a5f6abd4 WB |
665 | message->state = RUNNING_STATE; |
666 | dma_config = 0; | |
667 | ||
092e1fda BW |
668 | /* Speed setup (surely valid because already checked) */ |
669 | if (transfer->speed_hz) | |
47885ce8 | 670 | bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz)); |
092e1fda | 671 | else |
47885ce8 | 672 | bfin_write(&drv_data->regs->baud, chip->baud); |
092e1fda | 673 | |
47885ce8 | 674 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
e72dcde7 | 675 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 676 | |
88b40369 BW |
677 | dev_dbg(&drv_data->pdev->dev, |
678 | "now pumping a transfer: width is %d, len is %d\n", | |
5e8592dc | 679 | cr_width, transfer->len); |
a5f6abd4 WB |
680 | |
681 | /* | |
8cf5858c VM |
682 | * Try to map dma buffer and do a dma transfer. If successful use, |
683 | * different way to r/w according to the enable_dma settings and if | |
684 | * we are not doing a full duplex transfer (since the hardware does | |
685 | * not support full duplex DMA transfers). | |
a5f6abd4 | 686 | */ |
8eeb12e5 VM |
687 | if (!full_duplex && drv_data->cur_chip->enable_dma |
688 | && drv_data->len > 6) { | |
a5f6abd4 | 689 | |
11d6f599 | 690 | unsigned long dma_start_addr, flags; |
7aec3566 | 691 | |
bb90eb00 BW |
692 | disable_dma(drv_data->dma_channel); |
693 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
694 | |
695 | /* config dma channel */ | |
88b40369 | 696 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 697 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
5e8592dc | 698 | if (cr_width == BIT_CTL_WORDSIZE) { |
bb90eb00 | 699 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
700 | dma_width = WDSIZE_16; |
701 | } else { | |
bb90eb00 | 702 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
703 | dma_width = WDSIZE_8; |
704 | } | |
705 | ||
3f479a65 | 706 | /* poll for SPI completion before start */ |
47885ce8 | 707 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF)) |
d8c05008 | 708 | cpu_relax(); |
3f479a65 | 709 | |
a5f6abd4 WB |
710 | /* dirty hack for autobuffer DMA mode */ |
711 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
712 | dev_dbg(&drv_data->pdev->dev, |
713 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
714 | |
715 | /* no irq in autobuffer mode */ | |
716 | dma_config = | |
717 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
718 | set_dma_config(drv_data->dma_channel, dma_config); |
719 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 720 | (unsigned long)drv_data->tx); |
bb90eb00 | 721 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 722 | |
07612e5f | 723 | /* start SPI transfer */ |
47885ce8 | 724 | bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
725 | |
726 | /* just return here, there can only be one transfer | |
727 | * in this mode | |
728 | */ | |
a5f6abd4 | 729 | message->status = 0; |
138f97cd | 730 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
731 | return; |
732 | } | |
733 | ||
734 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 735 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
736 | if (drv_data->rx != NULL) { |
737 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
738 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
739 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 740 | |
8cf5858c | 741 | /* invalidate caches, if needed */ |
67834fa9 | 742 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
743 | invalidate_dcache_range((unsigned long) drv_data->rx, |
744 | (unsigned long) (drv_data->rx + | |
ace32865 | 745 | drv_data->len_in_bytes)); |
8cf5858c | 746 | |
7aec3566 MF |
747 | dma_config |= WNR; |
748 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 749 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 750 | |
a5f6abd4 | 751 | } else if (drv_data->tx != NULL) { |
88b40369 | 752 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 753 | |
8cf5858c | 754 | /* flush caches, if needed */ |
67834fa9 | 755 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
756 | flush_dcache_range((unsigned long) drv_data->tx, |
757 | (unsigned long) (drv_data->tx + | |
ace32865 | 758 | drv_data->len_in_bytes)); |
8cf5858c | 759 | |
7aec3566 | 760 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 761 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
762 | |
763 | } else | |
764 | BUG(); | |
765 | ||
11d6f599 MF |
766 | /* oh man, here there be monsters ... and i dont mean the |
767 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
768 | * your data, kick your dog, and love it all. do *not* try | |
769 | * and change these lines unless you (1) heavily test DMA | |
770 | * with SPI flashes on a loaded system (e.g. ping floods), | |
771 | * (2) know just how broken the DMA engine interaction with | |
772 | * the SPI peripheral is, and (3) have someone else to blame | |
773 | * when you screw it all up anyways. | |
774 | */ | |
7aec3566 | 775 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
776 | set_dma_config(drv_data->dma_channel, dma_config); |
777 | local_irq_save(flags); | |
a963ea83 | 778 | SSYNC(); |
47885ce8 | 779 | bfin_write(&drv_data->regs->ctl, cr); |
a963ea83 | 780 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
781 | dma_enable_irq(drv_data->dma_channel); |
782 | local_irq_restore(flags); | |
07612e5f | 783 | |
f6a6d966 YL |
784 | return; |
785 | } | |
a5f6abd4 | 786 | |
5e8592dc MF |
787 | /* |
788 | * We always use SPI_WRITE mode (transfer starts with TDBR write). | |
789 | * SPI_READ mode (transfer starts with RDBR read) seems to have | |
790 | * problems with setting up the output value in TDBR prior to the | |
791 | * start of the transfer. | |
792 | */ | |
47885ce8 | 793 | bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD); |
5e8592dc | 794 | |
f6a6d966 | 795 | if (chip->pio_interrupt) { |
5e8592dc | 796 | /* SPI irq should have been disabled by now */ |
93b61bdd | 797 | |
f6a6d966 YL |
798 | /* discard old RX data and clear RXS */ |
799 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 800 | |
f6a6d966 YL |
801 | /* start transfer */ |
802 | if (drv_data->tx == NULL) | |
47885ce8 | 803 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); |
f6a6d966 | 804 | else { |
4d676fc5 | 805 | int loop; |
24778be2 | 806 | if (bits_per_word == 16) { |
4d676fc5 BL |
807 | u16 *buf = (u16 *)drv_data->tx; |
808 | for (loop = 0; loop < bits_per_word / 16; | |
809 | loop++) { | |
47885ce8 | 810 | bfin_write(&drv_data->regs->tdbr, *buf++); |
4d676fc5 | 811 | } |
24778be2 | 812 | } else if (bits_per_word == 8) { |
4d676fc5 BL |
813 | u8 *buf = (u8 *)drv_data->tx; |
814 | for (loop = 0; loop < bits_per_word / 8; loop++) | |
47885ce8 | 815 | bfin_write(&drv_data->regs->tdbr, *buf++); |
4d676fc5 BL |
816 | } |
817 | ||
f6a6d966 YL |
818 | drv_data->tx += drv_data->n_bytes; |
819 | } | |
a5f6abd4 | 820 | |
f6a6d966 YL |
821 | /* once TDBR is empty, interrupt is triggered */ |
822 | enable_irq(drv_data->spi_irq); | |
823 | return; | |
824 | } | |
a5f6abd4 | 825 | |
f6a6d966 YL |
826 | /* IO mode */ |
827 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
828 | ||
f6a6d966 YL |
829 | if (full_duplex) { |
830 | /* full duplex mode */ | |
831 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
832 | (drv_data->rx_end - drv_data->rx)); | |
833 | dev_dbg(&drv_data->pdev->dev, | |
834 | "IO duplex: cr is 0x%x\n", cr); | |
835 | ||
9c4542c7 | 836 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
837 | |
838 | if (drv_data->tx != drv_data->tx_end) | |
839 | tranf_success = 0; | |
840 | } else if (drv_data->tx != NULL) { | |
841 | /* write only half duplex */ | |
842 | dev_dbg(&drv_data->pdev->dev, | |
843 | "IO write: cr is 0x%x\n", cr); | |
844 | ||
9c4542c7 | 845 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
846 | |
847 | if (drv_data->tx != drv_data->tx_end) | |
848 | tranf_success = 0; | |
849 | } else if (drv_data->rx != NULL) { | |
850 | /* read only half duplex */ | |
851 | dev_dbg(&drv_data->pdev->dev, | |
852 | "IO read: cr is 0x%x\n", cr); | |
853 | ||
9c4542c7 | 854 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
855 | if (drv_data->rx != drv_data->rx_end) |
856 | tranf_success = 0; | |
857 | } | |
a5f6abd4 | 858 | |
f6a6d966 YL |
859 | if (!tranf_success) { |
860 | dev_dbg(&drv_data->pdev->dev, | |
861 | "IO write error!\n"); | |
862 | message->state = ERROR_STATE; | |
863 | } else { | |
25985edc | 864 | /* Update total byte transferred */ |
f6a6d966 YL |
865 | message->actual_length += drv_data->len_in_bytes; |
866 | /* Move to next transfer of this msg */ | |
867 | message->state = bfin_spi_next_transfer(drv_data); | |
2431a815 SJ |
868 | if (drv_data->cs_change && message->state != DONE_STATE) { |
869 | bfin_spi_flush(drv_data); | |
f6a6d966 | 870 | bfin_spi_cs_deactive(drv_data, chip); |
2431a815 | 871 | } |
a5f6abd4 | 872 | } |
f6a6d966 YL |
873 | |
874 | /* Schedule next transfer tasklet */ | |
875 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
876 | } |
877 | ||
878 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 879 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 880 | { |
9c0a788b | 881 | struct bfin_spi_master_data *drv_data; |
a5f6abd4 WB |
882 | unsigned long flags; |
883 | ||
9c0a788b | 884 | drv_data = container_of(work, struct bfin_spi_master_data, pump_messages); |
131b17d4 | 885 | |
a5f6abd4 WB |
886 | /* Lock queue and check for queue work */ |
887 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 888 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
889 | /* pumper kicked off but no work to do */ |
890 | drv_data->busy = 0; | |
891 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
892 | return; | |
893 | } | |
894 | ||
895 | /* Make sure we are not already running a message */ | |
896 | if (drv_data->cur_msg) { | |
897 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
898 | return; | |
899 | } | |
900 | ||
901 | /* Extract head of queue */ | |
902 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
903 | struct spi_message, queue); | |
5fec5b5a BW |
904 | |
905 | /* Setup the SSP using the per chip configuration */ | |
906 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 907 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 908 | |
a5f6abd4 WB |
909 | list_del_init(&drv_data->cur_msg->queue); |
910 | ||
911 | /* Initial message state */ | |
912 | drv_data->cur_msg->state = START_STATE; | |
913 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
914 | struct spi_transfer, transfer_list); | |
915 | ||
5fec5b5a BW |
916 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
917 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
918 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
919 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
920 | |
921 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
922 | "the first transfer len is %d\n", |
923 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
924 | |
925 | /* Mark as busy and launch transfers */ | |
926 | tasklet_schedule(&drv_data->pump_transfers); | |
927 | ||
928 | drv_data->busy = 1; | |
929 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
930 | } | |
931 | ||
932 | /* | |
933 | * got a msg to transfer, queue it in drv_data->queue. | |
934 | * And kick off message pumper | |
935 | */ | |
138f97cd | 936 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 937 | { |
9c0a788b | 938 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
939 | unsigned long flags; |
940 | ||
941 | spin_lock_irqsave(&drv_data->lock, flags); | |
942 | ||
f4f50c3f | 943 | if (!drv_data->running) { |
a5f6abd4 WB |
944 | spin_unlock_irqrestore(&drv_data->lock, flags); |
945 | return -ESHUTDOWN; | |
946 | } | |
947 | ||
948 | msg->actual_length = 0; | |
949 | msg->status = -EINPROGRESS; | |
950 | msg->state = START_STATE; | |
951 | ||
88b40369 | 952 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
953 | list_add_tail(&msg->queue, &drv_data->queue); |
954 | ||
f4f50c3f | 955 | if (drv_data->running && !drv_data->busy) |
a5f6abd4 WB |
956 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
957 | ||
958 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
12e17c42 SZ |
963 | #define MAX_SPI_SSEL 7 |
964 | ||
ddc0bf13 | 965 | static const u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
966 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
967 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
968 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
969 | ||
970 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
971 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
972 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
973 | ||
974 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
975 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
976 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
977 | }; | |
978 | ||
ab09e040 | 979 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 980 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 981 | { |
ac01e97d | 982 | struct bfin5xx_spi_chip *chip_info; |
9c0a788b MF |
983 | struct bfin_spi_slave_data *chip = NULL; |
984 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
5b47bcd4 | 985 | u16 bfin_ctl_reg; |
ac01e97d | 986 | int ret = -EINVAL; |
a5f6abd4 | 987 | |
a5f6abd4 | 988 | /* Only alloc (or use chip_info) on first setup */ |
ac01e97d | 989 | chip_info = NULL; |
a5f6abd4 WB |
990 | chip = spi_get_ctldata(spi); |
991 | if (chip == NULL) { | |
ac01e97d DM |
992 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
993 | if (!chip) { | |
994 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
995 | ret = -ENOMEM; | |
996 | goto error; | |
997 | } | |
a5f6abd4 WB |
998 | |
999 | chip->enable_dma = 0; | |
1000 | chip_info = spi->controller_data; | |
1001 | } | |
1002 | ||
5b47bcd4 MF |
1003 | /* Let people set non-standard bits directly */ |
1004 | bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | | |
1005 | BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ; | |
1006 | ||
a5f6abd4 WB |
1007 | /* chip_info isn't always needed */ |
1008 | if (chip_info) { | |
2ed35516 MF |
1009 | /* Make sure people stop trying to set fields via ctl_reg |
1010 | * when they should actually be using common SPI framework. | |
90008a64 | 1011 | * Currently we let through: WOM EMISO PSSE GM SZ. |
2ed35516 MF |
1012 | * Not sure if a user actually needs/uses any of these, |
1013 | * but let's assume (for now) they do. | |
1014 | */ | |
5b47bcd4 | 1015 | if (chip_info->ctl_reg & ~bfin_ctl_reg) { |
2ed35516 MF |
1016 | dev_err(&spi->dev, "do not set bits in ctl_reg " |
1017 | "that the SPI framework manages\n"); | |
ac01e97d | 1018 | goto error; |
2ed35516 | 1019 | } |
a5f6abd4 WB |
1020 | chip->enable_dma = chip_info->enable_dma != 0 |
1021 | && drv_data->master_info->enable_dma; | |
1022 | chip->ctl_reg = chip_info->ctl_reg; | |
a5f6abd4 | 1023 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
93b61bdd | 1024 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1025 | chip->pio_interrupt = chip_info->pio_interrupt; |
5b47bcd4 MF |
1026 | } else { |
1027 | /* force a default base state */ | |
1028 | chip->ctl_reg &= bfin_ctl_reg; | |
033f44bd MF |
1029 | } |
1030 | ||
a5f6abd4 | 1031 | /* translate common spi framework into our register */ |
7715aad4 MF |
1032 | if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) { |
1033 | dev_err(&spi->dev, "unsupported spi modes detected\n"); | |
1034 | goto error; | |
1035 | } | |
a5f6abd4 | 1036 | if (spi->mode & SPI_CPOL) |
90008a64 | 1037 | chip->ctl_reg |= BIT_CTL_CPOL; |
a5f6abd4 | 1038 | if (spi->mode & SPI_CPHA) |
90008a64 | 1039 | chip->ctl_reg |= BIT_CTL_CPHA; |
a5f6abd4 | 1040 | if (spi->mode & SPI_LSB_FIRST) |
90008a64 | 1041 | chip->ctl_reg |= BIT_CTL_LSBF; |
a5f6abd4 | 1042 | /* we dont support running in slave mode (yet?) */ |
90008a64 | 1043 | chip->ctl_reg |= BIT_CTL_MASTER; |
a5f6abd4 | 1044 | |
a5f6abd4 WB |
1045 | /* |
1046 | * Notice: for blackfin, the speed_hz is the value of register | |
1047 | * SPI_BAUD, not the real baudrate | |
1048 | */ | |
1049 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
a5f6abd4 | 1050 | chip->chip_select_num = spi->chip_select; |
4190f6a5 BS |
1051 | if (chip->chip_select_num < MAX_CTRL_CS) { |
1052 | if (!(spi->mode & SPI_CPHA)) | |
1053 | dev_warn(&spi->dev, "Warning: SPI CPHA not set:" | |
1054 | " Slave Select not under software control!\n" | |
1055 | " See Documentation/blackfin/bfin-spi-notes.txt"); | |
1056 | ||
d3cc71f7 | 1057 | chip->flag = (1 << spi->chip_select) << 8; |
4190f6a5 | 1058 | } else |
d3cc71f7 | 1059 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; |
a5f6abd4 | 1060 | |
f6a6d966 YL |
1061 | if (chip->enable_dma && chip->pio_interrupt) { |
1062 | dev_err(&spi->dev, "enable_dma is set, " | |
1063 | "do not set pio_interrupt\n"); | |
1064 | goto error; | |
1065 | } | |
ac01e97d DM |
1066 | /* |
1067 | * if any one SPI chip is registered and wants DMA, request the | |
1068 | * DMA channel for it | |
1069 | */ | |
1070 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1071 | /* register dma irq handler */ | |
1072 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1073 | if (ret) { | |
1074 | dev_err(&spi->dev, | |
1075 | "Unable to request BlackFin SPI DMA channel\n"); | |
1076 | goto error; | |
1077 | } | |
1078 | drv_data->dma_requested = 1; | |
1079 | ||
1080 | ret = set_dma_callback(drv_data->dma_channel, | |
1081 | bfin_spi_dma_irq_handler, drv_data); | |
1082 | if (ret) { | |
1083 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1084 | goto error; | |
1085 | } | |
1086 | dma_disable_irq(drv_data->dma_channel); | |
1087 | } | |
1088 | ||
f6a6d966 YL |
1089 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1090 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
38ada214 | 1091 | 0, "BFIN_SPI", drv_data); |
f6a6d966 YL |
1092 | if (ret) { |
1093 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1094 | goto error; | |
1095 | } | |
1096 | drv_data->irq_requested = 1; | |
1097 | /* we use write mode, spi irq has to be disabled here */ | |
1098 | disable_irq(drv_data->spi_irq); | |
1099 | } | |
1100 | ||
d3cc71f7 | 1101 | if (chip->chip_select_num >= MAX_CTRL_CS) { |
73e1ac16 MH |
1102 | /* Only request on first setup */ |
1103 | if (spi_get_ctldata(spi) == NULL) { | |
1104 | ret = gpio_request(chip->cs_gpio, spi->modalias); | |
1105 | if (ret) { | |
1106 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1107 | goto pin_error; | |
1108 | } | |
1109 | gpio_direction_output(chip->cs_gpio, 1); | |
ac01e97d | 1110 | } |
a5f6abd4 WB |
1111 | } |
1112 | ||
898eb71c | 1113 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
033f44bd | 1114 | spi->modalias, spi->bits_per_word, chip->enable_dma); |
88b40369 | 1115 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1116 | chip->ctl_reg, chip->flag); |
1117 | ||
1118 | spi_set_ctldata(spi, chip); | |
1119 | ||
12e17c42 | 1120 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
d3cc71f7 | 1121 | if (chip->chip_select_num < MAX_CTRL_CS) { |
ac01e97d DM |
1122 | ret = peripheral_request(ssel[spi->master->bus_num] |
1123 | [chip->chip_select_num-1], spi->modalias); | |
1124 | if (ret) { | |
1125 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1126 | goto pin_error; | |
1127 | } | |
1128 | } | |
12e17c42 | 1129 | |
8221610e | 1130 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1131 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1132 | |
a5f6abd4 | 1133 | return 0; |
ac01e97d DM |
1134 | |
1135 | pin_error: | |
d3cc71f7 | 1136 | if (chip->chip_select_num >= MAX_CTRL_CS) |
ac01e97d DM |
1137 | gpio_free(chip->cs_gpio); |
1138 | else | |
1139 | peripheral_free(ssel[spi->master->bus_num] | |
1140 | [chip->chip_select_num - 1]); | |
1141 | error: | |
1142 | if (chip) { | |
1143 | if (drv_data->dma_requested) | |
1144 | free_dma(drv_data->dma_channel); | |
1145 | drv_data->dma_requested = 0; | |
1146 | ||
1147 | kfree(chip); | |
1148 | /* prevent free 'chip' twice */ | |
1149 | spi_set_ctldata(spi, NULL); | |
1150 | } | |
1151 | ||
1152 | return ret; | |
a5f6abd4 WB |
1153 | } |
1154 | ||
1155 | /* | |
1156 | * callback for spi framework. | |
1157 | * clean driver specific data | |
1158 | */ | |
138f97cd | 1159 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1160 | { |
9c0a788b MF |
1161 | struct bfin_spi_slave_data *chip = spi_get_ctldata(spi); |
1162 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1163 | |
e7d02e3c MF |
1164 | if (!chip) |
1165 | return; | |
1166 | ||
d3cc71f7 | 1167 | if (chip->chip_select_num < MAX_CTRL_CS) { |
12e17c42 SZ |
1168 | peripheral_free(ssel[spi->master->bus_num] |
1169 | [chip->chip_select_num-1]); | |
8221610e | 1170 | bfin_spi_cs_disable(drv_data, chip); |
d3cc71f7 | 1171 | } else |
42c78b2b MH |
1172 | gpio_free(chip->cs_gpio); |
1173 | ||
a5f6abd4 | 1174 | kfree(chip); |
ac01e97d DM |
1175 | /* prevent free 'chip' twice */ |
1176 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1177 | } |
1178 | ||
c52d4e5f | 1179 | static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1180 | { |
1181 | INIT_LIST_HEAD(&drv_data->queue); | |
1182 | spin_lock_init(&drv_data->lock); | |
1183 | ||
f4f50c3f | 1184 | drv_data->running = false; |
a5f6abd4 WB |
1185 | drv_data->busy = 0; |
1186 | ||
1187 | /* init transfer tasklet */ | |
1188 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1189 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1190 | |
1191 | /* init messages workqueue */ | |
138f97cd | 1192 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1193 | drv_data->workqueue = create_singlethread_workqueue( |
1194 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1195 | if (drv_data->workqueue == NULL) |
1196 | return -EBUSY; | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
c52d4e5f | 1201 | static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1202 | { |
1203 | unsigned long flags; | |
1204 | ||
1205 | spin_lock_irqsave(&drv_data->lock, flags); | |
1206 | ||
f4f50c3f | 1207 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1208 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1209 | return -EBUSY; | |
1210 | } | |
1211 | ||
f4f50c3f | 1212 | drv_data->running = true; |
a5f6abd4 WB |
1213 | drv_data->cur_msg = NULL; |
1214 | drv_data->cur_transfer = NULL; | |
1215 | drv_data->cur_chip = NULL; | |
1216 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1217 | ||
1218 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
c52d4e5f | 1223 | static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1224 | { |
1225 | unsigned long flags; | |
1226 | unsigned limit = 500; | |
1227 | int status = 0; | |
1228 | ||
1229 | spin_lock_irqsave(&drv_data->lock, flags); | |
1230 | ||
1231 | /* | |
1232 | * This is a bit lame, but is optimized for the common execution path. | |
1233 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1234 | * execution path (pump_messages) would be required to call wake_up or | |
1235 | * friends on every SPI message. Do this instead | |
1236 | */ | |
f4f50c3f | 1237 | drv_data->running = false; |
850a28ec | 1238 | while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) { |
a5f6abd4 WB |
1239 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1240 | msleep(10); | |
1241 | spin_lock_irqsave(&drv_data->lock, flags); | |
1242 | } | |
1243 | ||
1244 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1245 | status = -EBUSY; | |
1246 | ||
1247 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1248 | ||
1249 | return status; | |
1250 | } | |
1251 | ||
c52d4e5f | 1252 | static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1253 | { |
1254 | int status; | |
1255 | ||
138f97cd | 1256 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1257 | if (status != 0) |
1258 | return status; | |
1259 | ||
1260 | destroy_workqueue(drv_data->workqueue); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
2deff8d6 | 1265 | static int bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1266 | { |
1267 | struct device *dev = &pdev->dev; | |
1268 | struct bfin5xx_spi_master *platform_info; | |
1269 | struct spi_master *master; | |
9c0a788b | 1270 | struct bfin_spi_master_data *drv_data; |
a32c691d | 1271 | struct resource *res; |
a5f6abd4 WB |
1272 | int status = 0; |
1273 | ||
1274 | platform_info = dev->platform_data; | |
1275 | ||
1276 | /* Allocate master with space for drv_data */ | |
2a045131 | 1277 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1278 | if (!master) { |
1279 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1280 | return -ENOMEM; | |
1281 | } | |
131b17d4 | 1282 | |
a5f6abd4 WB |
1283 | drv_data = spi_master_get_devdata(master); |
1284 | drv_data->master = master; | |
1285 | drv_data->master_info = platform_info; | |
1286 | drv_data->pdev = pdev; | |
003d9226 | 1287 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1288 | |
e7db06b5 DB |
1289 | /* the spi->mode bits supported by this driver: */ |
1290 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
24778be2 | 1291 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
a5f6abd4 WB |
1292 | master->bus_num = pdev->id; |
1293 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1294 | master->cleanup = bfin_spi_cleanup; |
1295 | master->setup = bfin_spi_setup; | |
1296 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1297 | |
a32c691d BW |
1298 | /* Find and map our resources */ |
1299 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1300 | if (res == NULL) { | |
1301 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1302 | status = -ENOENT; | |
1303 | goto out_error_get_res; | |
1304 | } | |
1305 | ||
47885ce8 MF |
1306 | drv_data->regs = ioremap(res->start, resource_size(res)); |
1307 | if (drv_data->regs == NULL) { | |
a32c691d BW |
1308 | dev_err(dev, "Cannot map IO\n"); |
1309 | status = -ENXIO; | |
1310 | goto out_error_ioremap; | |
1311 | } | |
1312 | ||
f6a6d966 YL |
1313 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1314 | if (res == NULL) { | |
a32c691d BW |
1315 | dev_err(dev, "No DMA channel specified\n"); |
1316 | status = -ENOENT; | |
f6a6d966 YL |
1317 | goto out_error_free_io; |
1318 | } | |
1319 | drv_data->dma_channel = res->start; | |
1320 | ||
1321 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1322 | if (drv_data->spi_irq < 0) { | |
1323 | dev_err(dev, "No spi pio irq specified\n"); | |
1324 | status = -ENOENT; | |
1325 | goto out_error_free_io; | |
a32c691d BW |
1326 | } |
1327 | ||
a5f6abd4 | 1328 | /* Initial and start queue */ |
138f97cd | 1329 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1330 | if (status != 0) { |
a32c691d | 1331 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1332 | goto out_error_queue_alloc; |
1333 | } | |
a32c691d | 1334 | |
138f97cd | 1335 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1336 | if (status != 0) { |
a32c691d | 1337 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1338 | goto out_error_queue_alloc; |
1339 | } | |
1340 | ||
f9e522ca VM |
1341 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1342 | if (status != 0) { | |
1343 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1344 | goto out_error_queue_alloc; | |
1345 | } | |
1346 | ||
bb8beecd WM |
1347 | /* Reset SPI registers. If these registers were used by the boot loader, |
1348 | * the sky may fall on your head if you enable the dma controller. | |
1349 | */ | |
47885ce8 MF |
1350 | bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); |
1351 | bfin_write(&drv_data->regs->flg, 0xFF00); | |
bb8beecd | 1352 | |
a5f6abd4 WB |
1353 | /* Register with the SPI framework */ |
1354 | platform_set_drvdata(pdev, drv_data); | |
1355 | status = spi_register_master(master); | |
1356 | if (status != 0) { | |
a32c691d | 1357 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1358 | goto out_error_queue_alloc; |
1359 | } | |
a32c691d | 1360 | |
47885ce8 MF |
1361 | dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n", |
1362 | DRV_DESC, DRV_VERSION, drv_data->regs, | |
bb90eb00 | 1363 | drv_data->dma_channel); |
a5f6abd4 WB |
1364 | return status; |
1365 | ||
cc2f81a6 | 1366 | out_error_queue_alloc: |
138f97cd | 1367 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1368 | out_error_free_io: |
47885ce8 | 1369 | iounmap(drv_data->regs); |
a32c691d BW |
1370 | out_error_ioremap: |
1371 | out_error_get_res: | |
a5f6abd4 | 1372 | spi_master_put(master); |
cc2f81a6 | 1373 | |
a5f6abd4 WB |
1374 | return status; |
1375 | } | |
1376 | ||
1377 | /* stop hardware and remove the driver */ | |
fd4a319b | 1378 | static int bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1379 | { |
9c0a788b | 1380 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1381 | int status = 0; |
1382 | ||
1383 | if (!drv_data) | |
1384 | return 0; | |
1385 | ||
1386 | /* Remove the queue */ | |
138f97cd | 1387 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1388 | if (status != 0) |
1389 | return status; | |
1390 | ||
1391 | /* Disable the SSP at the peripheral and SOC level */ | |
1392 | bfin_spi_disable(drv_data); | |
1393 | ||
1394 | /* Release DMA */ | |
1395 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1396 | if (dma_channel_active(drv_data->dma_channel)) |
1397 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1398 | } |
1399 | ||
f6a6d966 YL |
1400 | if (drv_data->irq_requested) { |
1401 | free_irq(drv_data->spi_irq, drv_data); | |
1402 | drv_data->irq_requested = 0; | |
1403 | } | |
1404 | ||
a5f6abd4 WB |
1405 | /* Disconnect from the SPI framework */ |
1406 | spi_unregister_master(drv_data->master); | |
1407 | ||
003d9226 | 1408 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1409 | |
a5f6abd4 WB |
1410 | return 0; |
1411 | } | |
1412 | ||
1413 | #ifdef CONFIG_PM | |
138f97cd | 1414 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 | 1415 | { |
9c0a788b | 1416 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1417 | int status = 0; |
1418 | ||
138f97cd | 1419 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1420 | if (status != 0) |
1421 | return status; | |
1422 | ||
47885ce8 MF |
1423 | drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl); |
1424 | drv_data->flag_reg = bfin_read(&drv_data->regs->flg); | |
b052fd0a BS |
1425 | |
1426 | /* | |
1427 | * reset SPI_CTL and SPI_FLG registers | |
1428 | */ | |
47885ce8 MF |
1429 | bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); |
1430 | bfin_write(&drv_data->regs->flg, 0xFF00); | |
a5f6abd4 WB |
1431 | |
1432 | return 0; | |
1433 | } | |
1434 | ||
138f97cd | 1435 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 | 1436 | { |
9c0a788b | 1437 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1438 | int status = 0; |
1439 | ||
47885ce8 MF |
1440 | bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg); |
1441 | bfin_write(&drv_data->regs->flg, drv_data->flag_reg); | |
a5f6abd4 WB |
1442 | |
1443 | /* Start the queue running */ | |
138f97cd | 1444 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1445 | if (status != 0) { |
1446 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1447 | return status; | |
1448 | } | |
1449 | ||
1450 | return 0; | |
1451 | } | |
1452 | #else | |
138f97cd MF |
1453 | #define bfin_spi_suspend NULL |
1454 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1455 | #endif /* CONFIG_PM */ |
1456 | ||
7e38c3c4 | 1457 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1458 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1459 | .driver = { |
a32c691d | 1460 | .name = DRV_NAME, |
88b40369 BW |
1461 | .owner = THIS_MODULE, |
1462 | }, | |
138f97cd MF |
1463 | .suspend = bfin_spi_suspend, |
1464 | .resume = bfin_spi_resume, | |
fd4a319b | 1465 | .remove = bfin_spi_remove, |
a5f6abd4 WB |
1466 | }; |
1467 | ||
138f97cd | 1468 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1469 | { |
138f97cd | 1470 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1471 | } |
6f7c17f4 | 1472 | subsys_initcall(bfin_spi_init); |
a5f6abd4 | 1473 | |
138f97cd | 1474 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1475 | { |
138f97cd | 1476 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1477 | } |
138f97cd | 1478 | module_exit(bfin_spi_exit); |