[deliverable/linux.git] / drivers / spi / spi-bitbang.c

/*
 * polling/bitbanging SPI master controller driver utilities
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>


/*----------------------------------------------------------------------*/

/*
 * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
 * Use this for GPIO or shift-register level hardware APIs.
 *
 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
 * to glue code.  These bitbang setup() and cleanup() routines are always
 * used, though maybe they're called from controller-aware code.
 *
 * chipselect() and friends may use use spi_device->controller_data and
 * controller registers as appropriate.
 *
 *
 * NOTE:  SPI controller pins can often be used as GPIO pins instead,
 * which means you could use a bitbang driver either to get hardware
 * working quickly, or testing for differences that aren't speed related.
 */

struct spi_bitbang_cs {
	unsigned	nsecs;	/* (clock cycle time)/2 */
	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
					u32 word, u8 bits);
	unsigned	(*txrx_bufs)(struct spi_device *,
					u32 (*txrx_word)(
						struct spi_device *spi,
						unsigned nsecs,
						u32 word, u8 bits),
					unsigned, struct spi_transfer *);
};

static unsigned bitbang_txrx_8(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word ? : spi->bits_per_word;
	unsigned		count = t->len;
	const u8		*tx = t->tx_buf;
	u8			*rx = t->rx_buf;

	while (likely(count > 0)) {
		u8		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 1;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_16(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word ? : spi->bits_per_word;
	unsigned		count = t->len;
	const u16		*tx = t->tx_buf;
	u16			*rx = t->rx_buf;

	while (likely(count > 1)) {
		u16		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 2;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_32(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word ? : spi->bits_per_word;
	unsigned		count = t->len;
	const u32		*tx = t->tx_buf;
	u32			*rx = t->rx_buf;

	while (likely(count > 3)) {
		u32		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 4;
	}
	return t->len - count;
}

int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	u8			bits_per_word;
	u32			hz;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;
	if (bits_per_word <= 8)
		cs->txrx_bufs = bitbang_txrx_8;
	else if (bits_per_word <= 16)
		cs->txrx_bufs = bitbang_txrx_16;
	else if (bits_per_word <= 32)
		cs->txrx_bufs = bitbang_txrx_32;
	else
		return -EINVAL;

	/* nsecs = (clock period)/2 */
	if (!hz)
		hz = spi->max_speed_hz;
	if (hz) {
		cs->nsecs = (1000000000/2) / hz;
		if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
			return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);

/**
 * spi_bitbang_setup - default setup for per-word I/O loops
 */
int spi_bitbang_setup(struct spi_device *spi)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	struct spi_bitbang	*bitbang;
	int			retval;
	unsigned long		flags;

	bitbang = spi_master_get_devdata(spi->master);

	if (!cs) {
		cs = kzalloc(sizeof *cs, GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	/* per-word shift register access, in hardware or bitbanging */
	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
	if (!cs->txrx_word)
		return -EINVAL;

	retval = bitbang->setup_transfer(spi, NULL);
	if (retval < 0)
		return retval;

	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);

	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	 * setup, unless the hardware defaults cooperate to avoid confusion
	 * between normal (active low) and inverted chipselects.
	 */

	/* deselect chip (low or high) */
	spin_lock_irqsave(&bitbang->lock, flags);
	if (!bitbang->busy) {
		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
		ndelay(cs->nsecs);
	}
	spin_unlock_irqrestore(&bitbang->lock, flags);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup);

/**
 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 */
void spi_bitbang_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}
EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);

static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	unsigned		nsecs = cs->nsecs;

	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
}

/*----------------------------------------------------------------------*/

/*
 * SECOND PART ... simple transfer queue runner.
 *
 * This costs a task context per controller, running the queue by
 * performing each transfer in sequence.  Smarter hardware can queue
 * several DMA transfers at once, and process several controller queues
 * in parallel; this driver doesn't match such hardware very well.
 *
 * Drivers can provide word-at-a-time i/o primitives, or provide
 * transfer-at-a-time ones to leverage dma or fifo hardware.
 */
static void bitbang_work(struct work_struct *work)
{
	struct spi_bitbang	*bitbang =
		container_of(work, struct spi_bitbang, work);
	unsigned long		flags;

	spin_lock_irqsave(&bitbang->lock, flags);
	bitbang->busy = 1;
	while (!list_empty(&bitbang->queue)) {
		struct spi_message	*m;
		struct spi_device	*spi;
		unsigned		nsecs;
		struct spi_transfer	*t = NULL;
		unsigned		tmp;
		unsigned		cs_change;
		int			status;
		int			do_setup = -1;

		m = container_of(bitbang->queue.next, struct spi_message,
				queue);
		list_del_init(&m->queue);
		spin_unlock_irqrestore(&bitbang->lock, flags);

		/* FIXME this is made-up ... the correct value is known to
		 * word-at-a-time bitbang code, and presumably chipselect()
		 * should enforce these requirements too?
		 */
		nsecs = 100;

		spi = m->spi;
		tmp = 0;
		cs_change = 1;
		status = 0;

		list_for_each_entry (t, &m->transfers, transfer_list) {

			/* override speed or wordsize? */
			if (t->speed_hz || t->bits_per_word)
				do_setup = 1;

			/* init (-1) or override (1) transfer params */
			if (do_setup != 0) {
				status = bitbang->setup_transfer(spi, t);
				if (status < 0)
					break;
				if (do_setup == -1)
					do_setup = 0;
			}

			/* set up default clock polarity, and activate chip;
			 * this implicitly updates clock and spi modes as
			 * previously recorded for this device via setup().
			 * (and also deselects any other chip that might be
			 * selected ...)
			 */
			if (cs_change) {
				bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
				ndelay(nsecs);
			}
			cs_change = t->cs_change;
			if (!t->tx_buf && !t->rx_buf && t->len) {
				status = -EINVAL;
				break;
			}

			/* transfer data.  the lower level code handles any
			 * new dma mappings it needs. our caller always gave
			 * us dma-safe buffers.
			 */
			if (t->len) {
				/* REVISIT dma API still needs a designated
				 * DMA_ADDR_INVALID; ~0 might be better.
				 */
				if (!m->is_dma_mapped)
					t->rx_dma = t->tx_dma = 0;
				status = bitbang->txrx_bufs(spi, t);
			}
			if (status > 0)
				m->actual_length += status;
			if (status != t->len) {
				/* always report some kind of error */
				if (status >= 0)
					status = -EREMOTEIO;
				break;
			}
			status = 0;

			/* protocol tweaks before next transfer */
			if (t->delay_usecs)
				udelay(t->delay_usecs);

			if (!cs_change)
				continue;
			if (t->transfer_list.next == &m->transfers)
				break;

			/* sometimes a short mid-message deselect of the chip
			 * may be needed to terminate a mode or command
			 */
			ndelay(nsecs);
			bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
			ndelay(nsecs);
		}

		m->status = status;
		m->complete(m->context);

		/* normally deactivate chipselect ... unless no error and
		 * cs_change has hinted that the next message will probably
		 * be for this chip too.
		 */
		if (!(status == 0 && cs_change)) {
			ndelay(nsecs);
			bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
			ndelay(nsecs);
		}

		spin_lock_irqsave(&bitbang->lock, flags);
	}
	bitbang->busy = 0;
	spin_unlock_irqrestore(&bitbang->lock, flags);
}

/**
 * spi_bitbang_transfer - default submit to transfer queue
 */
int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
{
	struct spi_bitbang	*bitbang;
	unsigned long		flags;
	int			status = 0;

	m->actual_length = 0;
	m->status = -EINPROGRESS;

	bitbang = spi_master_get_devdata(spi->master);

	spin_lock_irqsave(&bitbang->lock, flags);
	if (!spi->max_speed_hz)
		status = -ENETDOWN;
	else {
		list_add_tail(&m->queue, &bitbang->queue);
		queue_work(bitbang->workqueue, &bitbang->work);
	}
	spin_unlock_irqrestore(&bitbang->lock, flags);

	return status;
}
EXPORT_SYMBOL_GPL(spi_bitbang_transfer);

/*----------------------------------------------------------------------*/

/**
 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
 * @bitbang: driver handle
 *
 * Caller should have zero-initialized all parts of the structure, and then
 * provided callbacks for chip selection and I/O loops.  If the master has
 * a transfer method, its final step should call spi_bitbang_transfer; or,
 * that's the default if the transfer routine is not initialized.  It should
 * also set up the bus number and number of chipselects.
 *
 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 * hardware that basically exposes a shift register) or per-spi_transfer
 * (which takes better advantage of hardware like fifos or DMA engines).
 *
 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
 * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
 * routine isn't initialized.
 *
 * This routine registers the spi_master, which will process requests in a
 * dedicated task, keeping IRQs unblocked most of the time.  To stop
 * processing those requests, call spi_bitbang_stop().
 */
int spi_bitbang_start(struct spi_bitbang *bitbang)
{
	int	status;

	if (!bitbang->master || !bitbang->chipselect)
		return -EINVAL;

	INIT_WORK(&bitbang->work, bitbang_work);
	spin_lock_init(&bitbang->lock);
	INIT_LIST_HEAD(&bitbang->queue);

	if (!bitbang->master->mode_bits)
		bitbang->master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;

	if (!bitbang->master->transfer)
		bitbang->master->transfer = spi_bitbang_transfer;
	if (!bitbang->txrx_bufs) {
		bitbang->use_dma = 0;
		bitbang->txrx_bufs = spi_bitbang_bufs;
		if (!bitbang->master->setup) {
			if (!bitbang->setup_transfer)
				bitbang->setup_transfer =
					 spi_bitbang_setup_transfer;
			bitbang->master->setup = spi_bitbang_setup;
			bitbang->master->cleanup = spi_bitbang_cleanup;
		}
	} else if (!bitbang->master->setup)
		return -EINVAL;
	if (bitbang->master->transfer == spi_bitbang_transfer &&
			!bitbang->setup_transfer)
		return -EINVAL;

	/* this task is the only thing to touch the SPI bits */
	bitbang->busy = 0;
	bitbang->workqueue = create_singlethread_workqueue(
			dev_name(bitbang->master->dev.parent));
	if (bitbang->workqueue == NULL) {
		status = -EBUSY;
		goto err1;
	}

	/* driver may get busy before register() returns, especially
	 * if someone registered boardinfo for devices
	 */
	status = spi_register_master(bitbang->master);
	if (status < 0)
		goto err2;

	return status;

err2:
	destroy_workqueue(bitbang->workqueue);
err1:
	return status;
}
EXPORT_SYMBOL_GPL(spi_bitbang_start);

/**
 * spi_bitbang_stop - stops the task providing spi communication
 */
int spi_bitbang_stop(struct spi_bitbang *bitbang)
{
	spi_unregister_master(bitbang->master);

	WARN_ON(!list_empty(&bitbang->queue));

	destroy_workqueue(bitbang->workqueue);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_stop);

MODULE_LICENSE("GPL");
Commit	Line	Data
9904f22a	1	/*
ca632f55	2	* polling/bitbanging SPI master controller driver utilities
9904f22a DB	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
9904f22a DB	19	#include <linux/init.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/workqueue.h>
	22	#include <linux/interrupt.h>
d7614de4	23	#include <linux/module.h>
9904f22a DB	24	#include <linux/delay.h>
	25	#include <linux/errno.h>
	26	#include <linux/platform_device.h>
5a0e3ad6	27	#include <linux/slab.h>
9904f22a DB	28
	29	#include <linux/spi/spi.h>
	30	#include <linux/spi/spi_bitbang.h>
	31
	32
	33	/----------------------------------------------------------------------/
	34
	35	/*
	36	* FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
	37	* Use this for GPIO or shift-register level hardware APIs.
	38	*
	39	* spi_bitbang_cs is in spi_device->controller_state, which is unavailable
	40	* to glue code. These bitbang setup() and cleanup() routines are always
	41	* used, though maybe they're called from controller-aware code.
	42	*
	43	* chipselect() and friends may use use spi_device->controller_data and
	44	* controller registers as appropriate.
	45	*
	46	*
	47	* NOTE: SPI controller pins can often be used as GPIO pins instead,
	48	* which means you could use a bitbang driver either to get hardware
	49	* working quickly, or testing for differences that aren't speed related.
	50	*/
	51
	52	struct spi_bitbang_cs {
	53	unsigned nsecs; /* (clock cycle time)/2 */
	54	u32 (txrx_word)(struct spi_device spi, unsigned nsecs,
	55	u32 word, u8 bits);
	56	unsigned (txrx_bufs)(struct spi_device ,
	57	u32 (*txrx_word)(
	58	struct spi_device *spi,
	59	unsigned nsecs,
	60	u32 word, u8 bits),
	61	unsigned, struct spi_transfer *);
	62	};
	63
	64	static unsigned bitbang_txrx_8(
	65	struct spi_device *spi,
	66	u32 (txrx_word)(struct spi_device spi,
	67	unsigned nsecs,
	68	u32 word, u8 bits),
	69	unsigned ns,
	70	struct spi_transfer *t
	71	) {
8c992684	72	unsigned bits = t->bits_per_word ? : spi->bits_per_word;
9904f22a DB	73	unsigned count = t->len;
	74	const u8 *tx = t->tx_buf;
	75	u8 *rx = t->rx_buf;
	76
	77	while (likely(count > 0)) {
	78	u8 word = 0;
	79
	80	if (tx)
	81	word = *tx++;
	82	word = txrx_word(spi, ns, word, bits);
	83	if (rx)
	84	*rx++ = word;
	85	count -= 1;
	86	}
	87	return t->len - count;
	88	}
	89
	90	static unsigned bitbang_txrx_16(
	91	struct spi_device *spi,
	92	u32 (txrx_word)(struct spi_device spi,
	93	unsigned nsecs,
	94	u32 word, u8 bits),
	95	unsigned ns,
	96	struct spi_transfer *t
	97	) {
8c992684	98	unsigned bits = t->bits_per_word ? : spi->bits_per_word;
9904f22a DB	99	unsigned count = t->len;
	100	const u16 *tx = t->tx_buf;
	101	u16 *rx = t->rx_buf;
	102
	103	while (likely(count > 1)) {
	104	u16 word = 0;
	105
	106	if (tx)
	107	word = *tx++;
	108	word = txrx_word(spi, ns, word, bits);
	109	if (rx)
	110	*rx++ = word;
	111	count -= 2;
	112	}
	113	return t->len - count;
	114	}
	115
	116	static unsigned bitbang_txrx_32(
	117	struct spi_device *spi,
	118	u32 (txrx_word)(struct spi_device spi,
	119	unsigned nsecs,
	120	u32 word, u8 bits),
	121	unsigned ns,
	122	struct spi_transfer *t
	123	) {
8c992684	124	unsigned bits = t->bits_per_word ? : spi->bits_per_word;
9904f22a DB	125	unsigned count = t->len;
	126	const u32 *tx = t->tx_buf;
	127	u32 *rx = t->rx_buf;
	128
	129	while (likely(count > 3)) {
	130	u32 word = 0;
	131
	132	if (tx)
	133	word = *tx++;
	134	word = txrx_word(spi, ns, word, bits);
	135	if (rx)
	136	*rx++ = word;
	137	count -= 4;
	138	}
	139	return t->len - count;
	140	}
	141
ff9f4771	142	int spi_bitbang_setup_transfer(struct spi_device spi, struct spi_transfer t)
4cff33f9 ID	143	{
	144	struct spi_bitbang_cs *cs = spi->controller_state;
	145	u8 bits_per_word;
	146	u32 hz;
	147
	148	if (t) {
	149	bits_per_word = t->bits_per_word;
	150	hz = t->speed_hz;
	151	} else {
	152	bits_per_word = 0;
	153	hz = 0;
	154	}
	155
	156	/* spi_transfer level calls that work per-word */
	157	if (!bits_per_word)
	158	bits_per_word = spi->bits_per_word;
	159	if (bits_per_word <= 8)
	160	cs->txrx_bufs = bitbang_txrx_8;
	161	else if (bits_per_word <= 16)
	162	cs->txrx_bufs = bitbang_txrx_16;
	163	else if (bits_per_word <= 32)
	164	cs->txrx_bufs = bitbang_txrx_32;
	165	else
	166	return -EINVAL;
	167
	168	/* nsecs = (clock period)/2 */
	169	if (!hz)
	170	hz = spi->max_speed_hz;
1e316d75 DB	171	if (hz) {
	172	cs->nsecs = (1000000000/2) / hz;
	173	if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
	174	return -EINVAL;
	175	}
4cff33f9 ID	176
	177	return 0;
	178	}
ff9f4771	179	EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
4cff33f9	180
9904f22a DB	181	/**
	182	* spi_bitbang_setup - default setup for per-word I/O loops
	183	*/
	184	int spi_bitbang_setup(struct spi_device *spi)
	185	{
	186	struct spi_bitbang_cs *cs = spi->controller_state;
	187	struct spi_bitbang *bitbang;
4cff33f9	188	int retval;
d52df2e2	189	unsigned long flags;
9904f22a	190
ccf77cc4 DB	191	bitbang = spi_master_get_devdata(spi->master);
ccf77cc4 DB	192
9904f22a	193	if (!cs) {
e94b1766	194	cs = kzalloc(sizeof *cs, GFP_KERNEL);
9904f22a DB	195	if (!cs)
	196	return -ENOMEM;
	197	spi->controller_state = cs;
	198	}
9904f22a	199
9904f22a DB	200	/* per-word shift register access, in hardware or bitbanging */
	201	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL\|SPI_CPHA)];
	202	if (!cs->txrx_word)
	203	return -EINVAL;
	204
7f8c7619	205	retval = bitbang->setup_transfer(spi, NULL);
4cff33f9 ID	206	if (retval < 0)
4cff33f9 ID	207	return retval;
9904f22a	208
7d077197	209	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
9904f22a DB	210
	211	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	212	* setup, unless the hardware defaults cooperate to avoid confusion
	213	* between normal (active low) and inverted chipselects.
	214	*/
	215
	216	/* deselect chip (low or high) */
d52df2e2	217	spin_lock_irqsave(&bitbang->lock, flags);
9904f22a	218	if (!bitbang->busy) {
8275c642	219	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
9904f22a DB	220	ndelay(cs->nsecs);
9904f22a DB	221	}
d52df2e2	222	spin_unlock_irqrestore(&bitbang->lock, flags);
9904f22a DB	223
	224	return 0;
	225	}
	226	EXPORT_SYMBOL_GPL(spi_bitbang_setup);
	227
	228	/**
	229	* spi_bitbang_cleanup - default cleanup for per-word I/O loops
	230	*/
0ffa0285	231	void spi_bitbang_cleanup(struct spi_device *spi)
9904f22a DB	232	{
	233	kfree(spi->controller_state);
	234	}
	235	EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
	236
	237	static int spi_bitbang_bufs(struct spi_device spi, struct spi_transfer t)
	238	{
	239	struct spi_bitbang_cs *cs = spi->controller_state;
	240	unsigned nsecs = cs->nsecs;
	241
	242	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
	243	}
	244
	245	/----------------------------------------------------------------------/
	246
	247	/*
	248	* SECOND PART ... simple transfer queue runner.
	249	*
	250	* This costs a task context per controller, running the queue by
	251	* performing each transfer in sequence. Smarter hardware can queue
	252	* several DMA transfers at once, and process several controller queues
	253	* in parallel; this driver doesn't match such hardware very well.
	254	*
	255	* Drivers can provide word-at-a-time i/o primitives, or provide
	256	* transfer-at-a-time ones to leverage dma or fifo hardware.
	257	*/
c4028958	258	static void bitbang_work(struct work_struct *work)
9904f22a	259	{
c4028958 DH	260	struct spi_bitbang *bitbang =
c4028958 DH	261	container_of(work, struct spi_bitbang, work);
9904f22a DB	262	unsigned long flags;
	263
	264	spin_lock_irqsave(&bitbang->lock, flags);
	265	bitbang->busy = 1;
	266	while (!list_empty(&bitbang->queue)) {
	267	struct spi_message *m;
	268	struct spi_device *spi;
	269	unsigned nsecs;
8275c642	270	struct spi_transfer *t = NULL;
9904f22a	271	unsigned tmp;
8275c642	272	unsigned cs_change;
9904f22a	273	int status;
b8f2e7bb	274	int do_setup = -1;
9904f22a DB	275
	276	m = container_of(bitbang->queue.next, struct spi_message,
	277	queue);
	278	list_del_init(&m->queue);
	279	spin_unlock_irqrestore(&bitbang->lock, flags);
	280
8275c642 VW	281	/* FIXME this is made-up ... the correct value is known to
	282	* word-at-a-time bitbang code, and presumably chipselect()
	283	* should enforce these requirements too?
	284	*/
	285	nsecs = 100;
9904f22a DB	286
9904f22a DB	287	spi = m->spi;
9904f22a	288	tmp = 0;
8275c642	289	cs_change = 1;
9904f22a DB	290	status = 0;
9904f22a DB	291
8275c642	292	list_for_each_entry (t, &m->transfers, transfer_list) {
9904f22a	293
529ba0d9 DB	294	/* override speed or wordsize? */
	295	if (t->speed_hz \|\| t->bits_per_word)
	296	do_setup = 1;
	297
	298	/* init (-1) or override (1) transfer params */
	299	if (do_setup != 0) {
ea3065df	300	status = bitbang->setup_transfer(spi, t);
4cff33f9 ID	301	if (status < 0)
4cff33f9 ID	302	break;
b8f2e7bb BN	303	if (do_setup == -1)
b8f2e7bb BN	304	do_setup = 0;
4cff33f9 ID	305	}
4cff33f9 ID	306
8275c642 VW	307	/* set up default clock polarity, and activate chip;
	308	* this implicitly updates clock and spi modes as
	309	* previously recorded for this device via setup().
	310	* (and also deselects any other chip that might be
	311	* selected ...)
	312	*/
	313	if (cs_change) {
	314	bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
9904f22a DB	315	ndelay(nsecs);
9904f22a DB	316	}
8275c642	317	cs_change = t->cs_change;
9904f22a DB	318	if (!t->tx_buf && !t->rx_buf && t->len) {
	319	status = -EINVAL;
	320	break;
	321	}
	322
8275c642 VW	323	/* transfer data. the lower level code handles any
	324	* new dma mappings it needs. our caller always gave
	325	* us dma-safe buffers.
	326	*/
9904f22a	327	if (t->len) {
8275c642 VW	328	/* REVISIT dma API still needs a designated
8275c642 VW	329	* DMA_ADDR_INVALID; ~0 might be better.
9904f22a	330	*/
8275c642 VW	331	if (!m->is_dma_mapped)
8275c642 VW	332	t->rx_dma = t->tx_dma = 0;
9904f22a DB	333	status = bitbang->txrx_bufs(spi, t);
9904f22a DB	334	}
2cfb8ce8 JN	335	if (status > 0)
2cfb8ce8 JN	336	m->actual_length += status;
9904f22a	337	if (status != t->len) {
2cfb8ce8 JN	338	/* always report some kind of error */
	339	if (status >= 0)
	340	status = -EREMOTEIO;
9904f22a DB	341	break;
9904f22a DB	342	}
9904f22a DB	343	status = 0;
	344
	345	/* protocol tweaks before next transfer */
	346	if (t->delay_usecs)
	347	udelay(t->delay_usecs);
	348
8275c642	349	if (!cs_change)
9904f22a	350	continue;
8275c642 VW	351	if (t->transfer_list.next == &m->transfers)
8275c642 VW	352	break;
9904f22a	353
8275c642 VW	354	/* sometimes a short mid-message deselect of the chip
	355	* may be needed to terminate a mode or command
	356	*/
	357	ndelay(nsecs);
	358	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	359	ndelay(nsecs);
9904f22a DB	360	}
9904f22a DB	361
9904f22a DB	362	m->status = status;
	363	m->complete(m->context);
	364
8275c642 VW	365	/* normally deactivate chipselect ... unless no error and
	366	* cs_change has hinted that the next message will probably
	367	* be for this chip too.
	368	*/
	369	if (!(status == 0 && cs_change)) {
	370	ndelay(nsecs);
	371	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	372	ndelay(nsecs);
	373	}
9904f22a DB	374
	375	spin_lock_irqsave(&bitbang->lock, flags);
	376	}
	377	bitbang->busy = 0;
	378	spin_unlock_irqrestore(&bitbang->lock, flags);
	379	}
	380
	381	/**
	382	* spi_bitbang_transfer - default submit to transfer queue
	383	*/
	384	int spi_bitbang_transfer(struct spi_device spi, struct spi_message m)
	385	{
	386	struct spi_bitbang *bitbang;
	387	unsigned long flags;
1e316d75	388	int status = 0;
9904f22a DB	389
	390	m->actual_length = 0;
	391	m->status = -EINPROGRESS;
	392
	393	bitbang = spi_master_get_devdata(spi->master);
9904f22a DB	394
9904f22a DB	395	spin_lock_irqsave(&bitbang->lock, flags);
1e316d75 DB	396	if (!spi->max_speed_hz)
	397	status = -ENETDOWN;
	398	else {
	399	list_add_tail(&m->queue, &bitbang->queue);
	400	queue_work(bitbang->workqueue, &bitbang->work);
	401	}
9904f22a DB	402	spin_unlock_irqrestore(&bitbang->lock, flags);
9904f22a DB	403
1e316d75	404	return status;
9904f22a DB	405	}
	406	EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
	407
	408	/----------------------------------------------------------------------/
	409
	410	/**
	411	* spi_bitbang_start - start up a polled/bitbanging SPI master driver
	412	* @bitbang: driver handle
	413	*
	414	* Caller should have zero-initialized all parts of the structure, and then
	415	* provided callbacks for chip selection and I/O loops. If the master has
	416	* a transfer method, its final step should call spi_bitbang_transfer; or,
	417	* that's the default if the transfer routine is not initialized. It should
	418	* also set up the bus number and number of chipselects.
	419	*
	420	* For i/o loops, provide callbacks either per-word (for bitbanging, or for
	421	* hardware that basically exposes a shift register) or per-spi_transfer
	422	* (which takes better advantage of hardware like fifos or DMA engines).
	423	*
7f8c7619 HPN	424	* Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
	425	* spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
	426	* master methods. Those methods are the defaults if the bitbang->txrx_bufs
	427	* routine isn't initialized.
9904f22a DB	428	*
	429	* This routine registers the spi_master, which will process requests in a
	430	* dedicated task, keeping IRQs unblocked most of the time. To stop
	431	* processing those requests, call spi_bitbang_stop().
	432	*/
	433	int spi_bitbang_start(struct spi_bitbang *bitbang)
	434	{
	435	int status;
	436
	437	if (!bitbang->master \|\| !bitbang->chipselect)
	438	return -EINVAL;
	439
c4028958	440	INIT_WORK(&bitbang->work, bitbang_work);
9904f22a DB	441	spin_lock_init(&bitbang->lock);
	442	INIT_LIST_HEAD(&bitbang->queue);
	443
e7db06b5 DB	444	if (!bitbang->master->mode_bits)
	445	bitbang->master->mode_bits = SPI_CPOL \| SPI_CPHA \| bitbang->flags;
	446
9904f22a DB	447	if (!bitbang->master->transfer)
	448	bitbang->master->transfer = spi_bitbang_transfer;
	449	if (!bitbang->txrx_bufs) {
	450	bitbang->use_dma = 0;
	451	bitbang->txrx_bufs = spi_bitbang_bufs;
	452	if (!bitbang->master->setup) {
ff9f4771 KG	453	if (!bitbang->setup_transfer)
	454	bitbang->setup_transfer =
	455	spi_bitbang_setup_transfer;
9904f22a DB	456	bitbang->master->setup = spi_bitbang_setup;
	457	bitbang->master->cleanup = spi_bitbang_cleanup;
	458	}
	459	} else if (!bitbang->master->setup)
	460	return -EINVAL;
ea3065df SH	461	if (bitbang->master->transfer == spi_bitbang_transfer &&
	462	!bitbang->setup_transfer)
	463	return -EINVAL;
9904f22a DB	464
	465	/* this task is the only thing to touch the SPI bits */
	466	bitbang->busy = 0;
	467	bitbang->workqueue = create_singlethread_workqueue(
35f74fca	468	dev_name(bitbang->master->dev.parent));
9904f22a DB	469	if (bitbang->workqueue == NULL) {
	470	status = -EBUSY;
	471	goto err1;
	472	}
	473
	474	/* driver may get busy before register() returns, especially
	475	* if someone registered boardinfo for devices
	476	*/
	477	status = spi_register_master(bitbang->master);
	478	if (status < 0)
	479	goto err2;
	480
	481	return status;
	482
	483	err2:
	484	destroy_workqueue(bitbang->workqueue);
	485	err1:
	486	return status;
	487	}
	488	EXPORT_SYMBOL_GPL(spi_bitbang_start);
	489
	490	/**
	491	* spi_bitbang_stop - stops the task providing spi communication
	492	*/
	493	int spi_bitbang_stop(struct spi_bitbang *bitbang)
	494	{
a836f585	495	spi_unregister_master(bitbang->master);
9904f22a	496
a836f585	497	WARN_ON(!list_empty(&bitbang->queue));
9904f22a DB	498
	499	destroy_workqueue(bitbang->workqueue);
	500
9904f22a DB	501	return 0;
	502	}
	503	EXPORT_SYMBOL_GPL(spi_bitbang_stop);
	504
	505	MODULE_LICENSE("GPL");
	506