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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
43abb11b | 3 | * Copyright (C) 2010 EF Johnson Technologies |
358934a6 SP |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/gpio.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/clk.h> | |
048177ce | 28 | #include <linux/dmaengine.h> |
358934a6 | 29 | #include <linux/dma-mapping.h> |
048177ce | 30 | #include <linux/edma.h> |
aae7147d MK |
31 | #include <linux/of.h> |
32 | #include <linux/of_device.h> | |
358934a6 SP |
33 | #include <linux/spi/spi.h> |
34 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
358934a6 | 36 | |
ec2a0833 | 37 | #include <linux/platform_data/spi-davinci.h> |
358934a6 SP |
38 | |
39 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
40 | ||
358934a6 SP |
41 | #define CS_DEFAULT 0xFF |
42 | ||
358934a6 SP |
43 | #define SPIFMT_PHASE_MASK BIT(16) |
44 | #define SPIFMT_POLARITY_MASK BIT(17) | |
45 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
46 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
47 | #define SPIFMT_WAITENA_MASK BIT(21) | |
48 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
49 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
50 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
51 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 52 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 53 | |
358934a6 SP |
54 | /* SPIPC0 */ |
55 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
56 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
57 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
58 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
59 | |
60 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
61 | #define SPIINT_MASKINT 0x0000015F |
62 | #define SPI_INTLVL_1 0x000001FF | |
63 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 64 | |
cfbc5d1d BN |
65 | /* SPIDAT1 (upper 16 bit defines) */ |
66 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
67 | ||
68 | /* SPIGCR1 */ | |
358934a6 SP |
69 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
70 | #define SPIGCR1_MASTER_MASK BIT(0) | |
3f27b57c | 71 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
358934a6 | 72 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
8e206f1c | 73 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
74 | |
75 | /* SPIBUF */ | |
76 | #define SPIBUF_TXFULL_MASK BIT(29) | |
77 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
78 | ||
7abbf23c BN |
79 | /* SPIDELAY */ |
80 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
81 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
82 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
83 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
84 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
85 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
86 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
87 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
88 | ||
358934a6 SP |
89 | /* Error Masks */ |
90 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
91 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
92 | #define SPIFLG_PARERR_MASK BIT(2) | |
93 | #define SPIFLG_DESYNC_MASK BIT(3) | |
94 | #define SPIFLG_BITERR_MASK BIT(4) | |
95 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 96 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
97 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
98 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
99 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
100 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 101 | |
358934a6 | 102 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 103 | |
358934a6 SP |
104 | /* SPI Controller registers */ |
105 | #define SPIGCR0 0x00 | |
106 | #define SPIGCR1 0x04 | |
107 | #define SPIINT 0x08 | |
108 | #define SPILVL 0x0c | |
109 | #define SPIFLG 0x10 | |
110 | #define SPIPC0 0x14 | |
358934a6 SP |
111 | #define SPIDAT1 0x3c |
112 | #define SPIBUF 0x40 | |
358934a6 SP |
113 | #define SPIDELAY 0x48 |
114 | #define SPIDEF 0x4c | |
115 | #define SPIFMT0 0x50 | |
358934a6 | 116 | |
358934a6 SP |
117 | /* SPI Controller driver's private data. */ |
118 | struct davinci_spi { | |
119 | struct spi_bitbang bitbang; | |
120 | struct clk *clk; | |
121 | ||
122 | u8 version; | |
123 | resource_size_t pbase; | |
124 | void __iomem *base; | |
e0d205e9 BN |
125 | u32 irq; |
126 | struct completion done; | |
358934a6 SP |
127 | |
128 | const void *tx; | |
129 | void *rx; | |
e0d205e9 BN |
130 | int rcount; |
131 | int wcount; | |
048177ce MP |
132 | |
133 | struct dma_chan *dma_rx; | |
134 | struct dma_chan *dma_tx; | |
135 | int dma_rx_chnum; | |
136 | int dma_tx_chnum; | |
137 | ||
aae7147d | 138 | struct davinci_spi_platform_data pdata; |
358934a6 SP |
139 | |
140 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
141 | u32 (*get_tx)(struct davinci_spi *); | |
142 | ||
7480e755 | 143 | u8 *bytes_per_word; |
358934a6 SP |
144 | }; |
145 | ||
53a31b07 BN |
146 | static struct davinci_spi_config davinci_spi_default_cfg; |
147 | ||
212d4b69 | 148 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
358934a6 | 149 | { |
212d4b69 SN |
150 | if (dspi->rx) { |
151 | u8 *rx = dspi->rx; | |
53d454a1 | 152 | *rx++ = (u8)data; |
212d4b69 | 153 | dspi->rx = rx; |
53d454a1 | 154 | } |
358934a6 SP |
155 | } |
156 | ||
212d4b69 | 157 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
358934a6 | 158 | { |
212d4b69 SN |
159 | if (dspi->rx) { |
160 | u16 *rx = dspi->rx; | |
53d454a1 | 161 | *rx++ = (u16)data; |
212d4b69 | 162 | dspi->rx = rx; |
53d454a1 | 163 | } |
358934a6 SP |
164 | } |
165 | ||
212d4b69 | 166 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
358934a6 | 167 | { |
53d454a1 | 168 | u32 data = 0; |
212d4b69 SN |
169 | if (dspi->tx) { |
170 | const u8 *tx = dspi->tx; | |
53d454a1 | 171 | data = *tx++; |
212d4b69 | 172 | dspi->tx = tx; |
53d454a1 | 173 | } |
358934a6 SP |
174 | return data; |
175 | } | |
176 | ||
212d4b69 | 177 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
358934a6 | 178 | { |
53d454a1 | 179 | u32 data = 0; |
212d4b69 SN |
180 | if (dspi->tx) { |
181 | const u16 *tx = dspi->tx; | |
53d454a1 | 182 | data = *tx++; |
212d4b69 | 183 | dspi->tx = tx; |
53d454a1 | 184 | } |
358934a6 SP |
185 | return data; |
186 | } | |
187 | ||
188 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
189 | { | |
190 | u32 v = ioread32(addr); | |
191 | ||
192 | v |= bits; | |
193 | iowrite32(v, addr); | |
194 | } | |
195 | ||
196 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
197 | { | |
198 | u32 v = ioread32(addr); | |
199 | ||
200 | v &= ~bits; | |
201 | iowrite32(v, addr); | |
202 | } | |
203 | ||
358934a6 SP |
204 | /* |
205 | * Interface to control the chip select signal | |
206 | */ | |
207 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
208 | { | |
212d4b69 | 209 | struct davinci_spi *dspi; |
358934a6 | 210 | struct davinci_spi_platform_data *pdata; |
7978b8c3 | 211 | u8 chip_sel = spi->chip_select; |
212d4b69 | 212 | u16 spidat1 = CS_DEFAULT; |
23853973 | 213 | bool gpio_chipsel = false; |
358934a6 | 214 | |
212d4b69 | 215 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 216 | pdata = &dspi->pdata; |
358934a6 | 217 | |
23853973 BN |
218 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
219 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | |
220 | gpio_chipsel = true; | |
221 | ||
358934a6 SP |
222 | /* |
223 | * Board specific chip select logic decides the polarity and cs | |
224 | * line for the controller | |
225 | */ | |
23853973 BN |
226 | if (gpio_chipsel) { |
227 | if (value == BITBANG_CS_ACTIVE) | |
228 | gpio_set_value(pdata->chip_sel[chip_sel], 0); | |
229 | else | |
230 | gpio_set_value(pdata->chip_sel[chip_sel], 1); | |
231 | } else { | |
232 | if (value == BITBANG_CS_ACTIVE) { | |
212d4b69 SN |
233 | spidat1 |= SPIDAT1_CSHOLD_MASK; |
234 | spidat1 &= ~(0x1 << chip_sel); | |
23853973 | 235 | } |
7978b8c3 | 236 | |
212d4b69 | 237 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); |
23853973 | 238 | } |
358934a6 SP |
239 | } |
240 | ||
7fe0092b BN |
241 | /** |
242 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
243 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
244 | * | |
245 | * This function calculates the prescale value that generates a clock rate | |
246 | * less than or equal to the specified maximum. | |
247 | * | |
248 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
249 | * or negative error number if valid prescalar cannot be updated. | |
250 | */ | |
212d4b69 | 251 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
7fe0092b BN |
252 | u32 max_speed_hz) |
253 | { | |
254 | int ret; | |
255 | ||
212d4b69 | 256 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); |
7fe0092b BN |
257 | |
258 | if (ret < 3 || ret > 256) | |
259 | return -EINVAL; | |
260 | ||
261 | return ret - 1; | |
262 | } | |
263 | ||
358934a6 SP |
264 | /** |
265 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
266 | * @spi: spi device on which data transfer to be done | |
267 | * @t: spi transfer in which transfer info is filled | |
268 | * | |
269 | * This function determines data transfer method (8/16/32 bit transfer). | |
270 | * It will also set the SPI Clock Control register according to | |
271 | * SPI slave device freq. | |
272 | */ | |
273 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
274 | struct spi_transfer *t) | |
275 | { | |
276 | ||
212d4b69 | 277 | struct davinci_spi *dspi; |
25f33512 | 278 | struct davinci_spi_config *spicfg; |
358934a6 | 279 | u8 bits_per_word = 0; |
32ea3944 SK |
280 | u32 hz = 0, spifmt = 0; |
281 | int prescale; | |
358934a6 | 282 | |
212d4b69 | 283 | dspi = spi_master_get_devdata(spi->master); |
25f33512 BN |
284 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
285 | if (!spicfg) | |
286 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
287 | |
288 | if (t) { | |
289 | bits_per_word = t->bits_per_word; | |
290 | hz = t->speed_hz; | |
291 | } | |
292 | ||
293 | /* if bits_per_word is not set then set it default */ | |
294 | if (!bits_per_word) | |
295 | bits_per_word = spi->bits_per_word; | |
296 | ||
297 | /* | |
298 | * Assign function pointer to appropriate transfer method | |
299 | * 8bit, 16bit or 32bit transfer | |
300 | */ | |
24778be2 | 301 | if (bits_per_word <= 8) { |
212d4b69 SN |
302 | dspi->get_rx = davinci_spi_rx_buf_u8; |
303 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
304 | dspi->bytes_per_word[spi->chip_select] = 1; | |
24778be2 | 305 | } else { |
212d4b69 SN |
306 | dspi->get_rx = davinci_spi_rx_buf_u16; |
307 | dspi->get_tx = davinci_spi_tx_buf_u16; | |
308 | dspi->bytes_per_word[spi->chip_select] = 2; | |
24778be2 | 309 | } |
358934a6 SP |
310 | |
311 | if (!hz) | |
312 | hz = spi->max_speed_hz; | |
313 | ||
25f33512 BN |
314 | /* Set up SPIFMTn register, unique to this chipselect. */ |
315 | ||
212d4b69 | 316 | prescale = davinci_spi_get_prescale(dspi, hz); |
7fe0092b BN |
317 | if (prescale < 0) |
318 | return prescale; | |
319 | ||
25f33512 BN |
320 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
321 | ||
322 | if (spi->mode & SPI_LSB_FIRST) | |
323 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
324 | ||
325 | if (spi->mode & SPI_CPOL) | |
326 | spifmt |= SPIFMT_POLARITY_MASK; | |
327 | ||
328 | if (!(spi->mode & SPI_CPHA)) | |
329 | spifmt |= SPIFMT_PHASE_MASK; | |
330 | ||
331 | /* | |
332 | * Version 1 hardware supports two basic SPI modes: | |
333 | * - Standard SPI mode uses 4 pins, with chipselect | |
334 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
335 | * (distinct from SPI_3WIRE, with just one data wire; | |
336 | * or similar variants without MOSI or without MISO) | |
337 | * | |
338 | * Version 2 hardware supports an optional handshaking signal, | |
339 | * so it can support two more modes: | |
340 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
341 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
342 | */ | |
343 | ||
212d4b69 | 344 | if (dspi->version == SPI_VERSION_2) { |
25f33512 | 345 | |
7abbf23c BN |
346 | u32 delay = 0; |
347 | ||
25f33512 BN |
348 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
349 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 350 | |
25f33512 BN |
351 | if (spicfg->odd_parity) |
352 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
353 | ||
354 | if (spicfg->parity_enable) | |
355 | spifmt |= SPIFMT_PARITYENA_MASK; | |
356 | ||
7abbf23c | 357 | if (spicfg->timer_disable) { |
25f33512 | 358 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
359 | } else { |
360 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
361 | & SPIDELAY_C2TDELAY_MASK; | |
362 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
363 | & SPIDELAY_T2CDELAY_MASK; | |
364 | } | |
25f33512 | 365 | |
7abbf23c | 366 | if (spi->mode & SPI_READY) { |
25f33512 | 367 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
368 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
369 | & SPIDELAY_T2EDELAY_MASK; | |
370 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
371 | & SPIDELAY_C2EDELAY_MASK; | |
372 | } | |
373 | ||
212d4b69 | 374 | iowrite32(delay, dspi->base + SPIDELAY); |
25f33512 BN |
375 | } |
376 | ||
212d4b69 | 377 | iowrite32(spifmt, dspi->base + SPIFMT0); |
358934a6 SP |
378 | |
379 | return 0; | |
380 | } | |
381 | ||
358934a6 SP |
382 | /** |
383 | * davinci_spi_setup - This functions will set default transfer method | |
384 | * @spi: spi device on which data transfer to be done | |
385 | * | |
386 | * This functions sets the default transfer method. | |
387 | */ | |
358934a6 SP |
388 | static int davinci_spi_setup(struct spi_device *spi) |
389 | { | |
b23a5d46 | 390 | int retval = 0; |
212d4b69 | 391 | struct davinci_spi *dspi; |
be88471b | 392 | struct davinci_spi_platform_data *pdata; |
358934a6 | 393 | |
212d4b69 | 394 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 395 | pdata = &dspi->pdata; |
358934a6 | 396 | |
be88471b BN |
397 | if (!(spi->mode & SPI_NO_CS)) { |
398 | if ((pdata->chip_sel == NULL) || | |
399 | (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) | |
212d4b69 | 400 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); |
be88471b BN |
401 | |
402 | } | |
403 | ||
404 | if (spi->mode & SPI_READY) | |
212d4b69 | 405 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
be88471b BN |
406 | |
407 | if (spi->mode & SPI_LOOP) | |
212d4b69 | 408 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 409 | else |
212d4b69 | 410 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 411 | |
358934a6 SP |
412 | return retval; |
413 | } | |
414 | ||
212d4b69 | 415 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
358934a6 | 416 | { |
212d4b69 | 417 | struct device *sdev = dspi->bitbang.master->dev.parent; |
358934a6 SP |
418 | |
419 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
420 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
421 | return -ETIMEDOUT; | |
422 | } | |
423 | if (int_status & SPIFLG_DESYNC_MASK) { | |
424 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
425 | return -EIO; | |
426 | } | |
427 | if (int_status & SPIFLG_BITERR_MASK) { | |
428 | dev_dbg(sdev, "SPI Bit error\n"); | |
429 | return -EIO; | |
430 | } | |
431 | ||
212d4b69 | 432 | if (dspi->version == SPI_VERSION_2) { |
358934a6 SP |
433 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
434 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
435 | return -EIO; | |
436 | } | |
437 | if (int_status & SPIFLG_PARERR_MASK) { | |
438 | dev_dbg(sdev, "SPI Parity Error\n"); | |
439 | return -EIO; | |
440 | } | |
441 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
442 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
443 | return -EIO; | |
444 | } | |
358934a6 SP |
445 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
446 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
447 | return -EBUSY; | |
448 | } | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
e0d205e9 BN |
454 | /** |
455 | * davinci_spi_process_events - check for and handle any SPI controller events | |
212d4b69 | 456 | * @dspi: the controller data |
e0d205e9 BN |
457 | * |
458 | * This function will check the SPIFLG register and handle any events that are | |
459 | * detected there | |
460 | */ | |
212d4b69 | 461 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
e0d205e9 | 462 | { |
212d4b69 | 463 | u32 buf, status, errors = 0, spidat1; |
e0d205e9 | 464 | |
212d4b69 | 465 | buf = ioread32(dspi->base + SPIBUF); |
e0d205e9 | 466 | |
212d4b69 SN |
467 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
468 | dspi->get_rx(buf & 0xFFFF, dspi); | |
469 | dspi->rcount--; | |
e0d205e9 BN |
470 | } |
471 | ||
212d4b69 | 472 | status = ioread32(dspi->base + SPIFLG); |
e0d205e9 BN |
473 | |
474 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
475 | errors = status & SPIFLG_ERROR_MASK; | |
476 | goto out; | |
477 | } | |
478 | ||
212d4b69 SN |
479 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
480 | spidat1 = ioread32(dspi->base + SPIDAT1); | |
481 | dspi->wcount--; | |
482 | spidat1 &= ~0xFFFF; | |
483 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); | |
484 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
e0d205e9 BN |
485 | } |
486 | ||
487 | out: | |
488 | return errors; | |
489 | } | |
490 | ||
048177ce | 491 | static void davinci_spi_dma_rx_callback(void *data) |
87467bd9 | 492 | { |
048177ce | 493 | struct davinci_spi *dspi = (struct davinci_spi *)data; |
87467bd9 | 494 | |
048177ce | 495 | dspi->rcount = 0; |
87467bd9 | 496 | |
048177ce MP |
497 | if (!dspi->wcount && !dspi->rcount) |
498 | complete(&dspi->done); | |
499 | } | |
87467bd9 | 500 | |
048177ce MP |
501 | static void davinci_spi_dma_tx_callback(void *data) |
502 | { | |
503 | struct davinci_spi *dspi = (struct davinci_spi *)data; | |
504 | ||
505 | dspi->wcount = 0; | |
506 | ||
507 | if (!dspi->wcount && !dspi->rcount) | |
212d4b69 | 508 | complete(&dspi->done); |
87467bd9 BN |
509 | } |
510 | ||
358934a6 SP |
511 | /** |
512 | * davinci_spi_bufs - functions which will handle transfer data | |
513 | * @spi: spi device on which data transfer to be done | |
514 | * @t: spi transfer in which transfer info is filled | |
515 | * | |
516 | * This function will put data to be transferred into data register | |
517 | * of SPI controller and then wait until the completion will be marked | |
518 | * by the IRQ Handler. | |
519 | */ | |
87467bd9 | 520 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
358934a6 | 521 | { |
212d4b69 | 522 | struct davinci_spi *dspi; |
048177ce | 523 | int data_type, ret = -ENOMEM; |
212d4b69 | 524 | u32 tx_data, spidat1; |
839c996c | 525 | u32 errors = 0; |
e0d205e9 | 526 | struct davinci_spi_config *spicfg; |
358934a6 | 527 | struct davinci_spi_platform_data *pdata; |
87467bd9 | 528 | unsigned uninitialized_var(rx_buf_count); |
048177ce MP |
529 | void *dummy_buf = NULL; |
530 | struct scatterlist sg_rx, sg_tx; | |
358934a6 | 531 | |
212d4b69 | 532 | dspi = spi_master_get_devdata(spi->master); |
aae7147d | 533 | pdata = &dspi->pdata; |
e0d205e9 BN |
534 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
535 | if (!spicfg) | |
536 | spicfg = &davinci_spi_default_cfg; | |
87467bd9 BN |
537 | |
538 | /* convert len to words based on bits_per_word */ | |
212d4b69 | 539 | data_type = dspi->bytes_per_word[spi->chip_select]; |
358934a6 | 540 | |
212d4b69 SN |
541 | dspi->tx = t->tx_buf; |
542 | dspi->rx = t->rx_buf; | |
543 | dspi->wcount = t->len / data_type; | |
544 | dspi->rcount = dspi->wcount; | |
7978b8c3 | 545 | |
212d4b69 | 546 | spidat1 = ioread32(dspi->base + SPIDAT1); |
839c996c | 547 | |
212d4b69 SN |
548 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
549 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
358934a6 | 550 | |
16735d02 | 551 | reinit_completion(&dspi->done); |
87467bd9 BN |
552 | |
553 | if (spicfg->io_type == SPI_IO_TYPE_INTR) | |
212d4b69 | 554 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
cf90fe73 | 555 | |
87467bd9 BN |
556 | if (spicfg->io_type != SPI_IO_TYPE_DMA) { |
557 | /* start the transfer */ | |
212d4b69 SN |
558 | dspi->wcount--; |
559 | tx_data = dspi->get_tx(dspi); | |
560 | spidat1 &= 0xFFFF0000; | |
561 | spidat1 |= tx_data & 0xFFFF; | |
562 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
87467bd9 | 563 | } else { |
048177ce MP |
564 | struct dma_slave_config dma_rx_conf = { |
565 | .direction = DMA_DEV_TO_MEM, | |
566 | .src_addr = (unsigned long)dspi->pbase + SPIBUF, | |
567 | .src_addr_width = data_type, | |
568 | .src_maxburst = 1, | |
569 | }; | |
570 | struct dma_slave_config dma_tx_conf = { | |
571 | .direction = DMA_MEM_TO_DEV, | |
572 | .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, | |
573 | .dst_addr_width = data_type, | |
574 | .dst_maxburst = 1, | |
575 | }; | |
576 | struct dma_async_tx_descriptor *rxdesc; | |
577 | struct dma_async_tx_descriptor *txdesc; | |
578 | void *buf; | |
579 | ||
580 | dummy_buf = kzalloc(t->len, GFP_KERNEL); | |
581 | if (!dummy_buf) | |
582 | goto err_alloc_dummy_buf; | |
583 | ||
584 | dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); | |
585 | dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); | |
586 | ||
587 | sg_init_table(&sg_rx, 1); | |
588 | if (!t->rx_buf) | |
589 | buf = dummy_buf; | |
b1178b21 | 590 | else |
048177ce MP |
591 | buf = t->rx_buf; |
592 | t->rx_dma = dma_map_single(&spi->dev, buf, | |
593 | t->len, DMA_FROM_DEVICE); | |
594 | if (!t->rx_dma) { | |
595 | ret = -EFAULT; | |
596 | goto err_rx_map; | |
87467bd9 | 597 | } |
048177ce MP |
598 | sg_dma_address(&sg_rx) = t->rx_dma; |
599 | sg_dma_len(&sg_rx) = t->len; | |
87467bd9 | 600 | |
048177ce MP |
601 | sg_init_table(&sg_tx, 1); |
602 | if (!t->tx_buf) | |
603 | buf = dummy_buf; | |
604 | else | |
605 | buf = (void *)t->tx_buf; | |
606 | t->tx_dma = dma_map_single(&spi->dev, buf, | |
89c66ee8 | 607 | t->len, DMA_TO_DEVICE); |
048177ce MP |
608 | if (!t->tx_dma) { |
609 | ret = -EFAULT; | |
610 | goto err_tx_map; | |
87467bd9 | 611 | } |
048177ce MP |
612 | sg_dma_address(&sg_tx) = t->tx_dma; |
613 | sg_dma_len(&sg_tx) = t->len; | |
614 | ||
615 | rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, | |
616 | &sg_rx, 1, DMA_DEV_TO_MEM, | |
617 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
618 | if (!rxdesc) | |
619 | goto err_desc; | |
620 | ||
621 | txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, | |
622 | &sg_tx, 1, DMA_MEM_TO_DEV, | |
623 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
624 | if (!txdesc) | |
625 | goto err_desc; | |
626 | ||
627 | rxdesc->callback = davinci_spi_dma_rx_callback; | |
628 | rxdesc->callback_param = (void *)dspi; | |
629 | txdesc->callback = davinci_spi_dma_tx_callback; | |
630 | txdesc->callback_param = (void *)dspi; | |
87467bd9 BN |
631 | |
632 | if (pdata->cshold_bug) | |
212d4b69 | 633 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
87467bd9 | 634 | |
048177ce MP |
635 | dmaengine_submit(rxdesc); |
636 | dmaengine_submit(txdesc); | |
637 | ||
638 | dma_async_issue_pending(dspi->dma_rx); | |
639 | dma_async_issue_pending(dspi->dma_tx); | |
640 | ||
212d4b69 | 641 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
87467bd9 | 642 | } |
358934a6 | 643 | |
e0d205e9 | 644 | /* Wait for the transfer to complete */ |
87467bd9 | 645 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
212d4b69 | 646 | wait_for_completion_interruptible(&(dspi->done)); |
e0d205e9 | 647 | } else { |
212d4b69 SN |
648 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
649 | errors = davinci_spi_process_events(dspi); | |
e0d205e9 BN |
650 | if (errors) |
651 | break; | |
652 | cpu_relax(); | |
358934a6 SP |
653 | } |
654 | } | |
655 | ||
212d4b69 | 656 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
87467bd9 | 657 | if (spicfg->io_type == SPI_IO_TYPE_DMA) { |
212d4b69 | 658 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
048177ce MP |
659 | |
660 | dma_unmap_single(&spi->dev, t->rx_dma, | |
661 | t->len, DMA_FROM_DEVICE); | |
662 | dma_unmap_single(&spi->dev, t->tx_dma, | |
663 | t->len, DMA_TO_DEVICE); | |
664 | kfree(dummy_buf); | |
87467bd9 | 665 | } |
e0d205e9 | 666 | |
212d4b69 SN |
667 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
668 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
3f27b57c | 669 | |
358934a6 SP |
670 | /* |
671 | * Check for bit error, desync error,parity error,timeout error and | |
672 | * receive overflow errors | |
673 | */ | |
839c996c | 674 | if (errors) { |
212d4b69 | 675 | ret = davinci_spi_check_error(dspi, errors); |
839c996c BN |
676 | WARN(!ret, "%s: error reported but no error found!\n", |
677 | dev_name(&spi->dev)); | |
358934a6 | 678 | return ret; |
839c996c | 679 | } |
358934a6 | 680 | |
212d4b69 | 681 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
048177ce | 682 | dev_err(&spi->dev, "SPI data transfer error\n"); |
87467bd9 BN |
683 | return -EIO; |
684 | } | |
685 | ||
358934a6 | 686 | return t->len; |
048177ce MP |
687 | |
688 | err_desc: | |
689 | dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); | |
690 | err_tx_map: | |
691 | dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); | |
692 | err_rx_map: | |
693 | kfree(dummy_buf); | |
694 | err_alloc_dummy_buf: | |
695 | return ret; | |
358934a6 SP |
696 | } |
697 | ||
32310aaf MK |
698 | /** |
699 | * dummy_thread_fn - dummy thread function | |
700 | * @irq: IRQ number for this SPI Master | |
701 | * @context_data: structure for SPI Master controller davinci_spi | |
702 | * | |
703 | * This is to satisfy the request_threaded_irq() API so that the irq | |
704 | * handler is called in interrupt context. | |
705 | */ | |
706 | static irqreturn_t dummy_thread_fn(s32 irq, void *data) | |
707 | { | |
708 | return IRQ_HANDLED; | |
709 | } | |
710 | ||
e0d205e9 BN |
711 | /** |
712 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
713 | * @irq: IRQ number for this SPI Master | |
714 | * @context_data: structure for SPI Master controller davinci_spi | |
715 | * | |
716 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
717 | * According to command it will do the appropriate action. It will check | |
718 | * transfer length and if it is not zero then dispatch transfer command again. | |
719 | * If transfer length is zero then it will indicate the COMPLETION so that | |
720 | * davinci_spi_bufs function can go ahead. | |
721 | */ | |
212d4b69 | 722 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
e0d205e9 | 723 | { |
212d4b69 | 724 | struct davinci_spi *dspi = data; |
e0d205e9 BN |
725 | int status; |
726 | ||
212d4b69 | 727 | status = davinci_spi_process_events(dspi); |
e0d205e9 | 728 | if (unlikely(status != 0)) |
212d4b69 | 729 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
e0d205e9 | 730 | |
212d4b69 SN |
731 | if ((!dspi->rcount && !dspi->wcount) || status) |
732 | complete(&dspi->done); | |
e0d205e9 BN |
733 | |
734 | return IRQ_HANDLED; | |
735 | } | |
736 | ||
212d4b69 | 737 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
903ca25b | 738 | { |
048177ce MP |
739 | dma_cap_mask_t mask; |
740 | struct device *sdev = dspi->bitbang.master->dev.parent; | |
903ca25b SN |
741 | int r; |
742 | ||
048177ce MP |
743 | dma_cap_zero(mask); |
744 | dma_cap_set(DMA_SLAVE, mask); | |
745 | ||
746 | dspi->dma_rx = dma_request_channel(mask, edma_filter_fn, | |
747 | &dspi->dma_rx_chnum); | |
748 | if (!dspi->dma_rx) { | |
749 | dev_err(sdev, "request RX DMA channel failed\n"); | |
750 | r = -ENODEV; | |
523c37e7 | 751 | goto rx_dma_failed; |
903ca25b SN |
752 | } |
753 | ||
048177ce MP |
754 | dspi->dma_tx = dma_request_channel(mask, edma_filter_fn, |
755 | &dspi->dma_tx_chnum); | |
756 | if (!dspi->dma_tx) { | |
757 | dev_err(sdev, "request TX DMA channel failed\n"); | |
758 | r = -ENODEV; | |
523c37e7 | 759 | goto tx_dma_failed; |
903ca25b SN |
760 | } |
761 | ||
762 | return 0; | |
048177ce | 763 | |
523c37e7 | 764 | tx_dma_failed: |
048177ce | 765 | dma_release_channel(dspi->dma_rx); |
523c37e7 BN |
766 | rx_dma_failed: |
767 | return r; | |
903ca25b SN |
768 | } |
769 | ||
aae7147d MK |
770 | #if defined(CONFIG_OF) |
771 | static const struct of_device_id davinci_spi_of_match[] = { | |
772 | { | |
804413f2 | 773 | .compatible = "ti,dm6441-spi", |
aae7147d MK |
774 | }, |
775 | { | |
804413f2 | 776 | .compatible = "ti,da830-spi", |
aae7147d MK |
777 | .data = (void *)SPI_VERSION_2, |
778 | }, | |
779 | { }, | |
780 | }; | |
0d2d0cc5 | 781 | MODULE_DEVICE_TABLE(of, davinci_spi_of_match); |
aae7147d MK |
782 | |
783 | /** | |
784 | * spi_davinci_get_pdata - Get platform data from DTS binding | |
785 | * @pdev: ptr to platform data | |
786 | * @dspi: ptr to driver data | |
787 | * | |
788 | * Parses and populates pdata in dspi from device tree bindings. | |
789 | * | |
790 | * NOTE: Not all platform data params are supported currently. | |
791 | */ | |
792 | static int spi_davinci_get_pdata(struct platform_device *pdev, | |
793 | struct davinci_spi *dspi) | |
794 | { | |
795 | struct device_node *node = pdev->dev.of_node; | |
796 | struct davinci_spi_platform_data *pdata; | |
797 | unsigned int num_cs, intr_line = 0; | |
798 | const struct of_device_id *match; | |
799 | ||
800 | pdata = &dspi->pdata; | |
801 | ||
802 | pdata->version = SPI_VERSION_1; | |
b53b34f0 | 803 | match = of_match_device(davinci_spi_of_match, &pdev->dev); |
aae7147d MK |
804 | if (!match) |
805 | return -ENODEV; | |
806 | ||
807 | /* match data has the SPI version number for SPI_VERSION_2 */ | |
808 | if (match->data == (void *)SPI_VERSION_2) | |
809 | pdata->version = SPI_VERSION_2; | |
810 | ||
811 | /* | |
812 | * default num_cs is 1 and all chipsel are internal to the chip | |
813 | * indicated by chip_sel being NULL. GPIO based CS is not | |
814 | * supported yet in DT bindings. | |
815 | */ | |
816 | num_cs = 1; | |
817 | of_property_read_u32(node, "num-cs", &num_cs); | |
818 | pdata->num_chipselect = num_cs; | |
819 | of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); | |
820 | pdata->intr_line = intr_line; | |
821 | return 0; | |
822 | } | |
823 | #else | |
aae7147d MK |
824 | static struct davinci_spi_platform_data |
825 | *spi_davinci_get_pdata(struct platform_device *pdev, | |
826 | struct davinci_spi *dspi) | |
827 | { | |
828 | return -ENODEV; | |
829 | } | |
830 | #endif | |
831 | ||
358934a6 SP |
832 | /** |
833 | * davinci_spi_probe - probe function for SPI Master Controller | |
834 | * @pdev: platform_device structure which contains plateform specific data | |
035540f6 BN |
835 | * |
836 | * According to Linux Device Model this function will be invoked by Linux | |
837 | * with platform_device struct which contains the device specific info. | |
838 | * This function will map the SPI controller's memory, register IRQ, | |
839 | * Reset SPI controller and setting its registers to default value. | |
840 | * It will invoke spi_bitbang_start to create work queue so that client driver | |
841 | * can register transfer method to work queue. | |
358934a6 | 842 | */ |
fd4a319b | 843 | static int davinci_spi_probe(struct platform_device *pdev) |
358934a6 SP |
844 | { |
845 | struct spi_master *master; | |
212d4b69 | 846 | struct davinci_spi *dspi; |
358934a6 | 847 | struct davinci_spi_platform_data *pdata; |
5b3bb596 | 848 | struct resource *r; |
358934a6 SP |
849 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; |
850 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
358934a6 | 851 | int i = 0, ret = 0; |
f34bd4cc | 852 | u32 spipc0; |
358934a6 | 853 | |
358934a6 SP |
854 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
855 | if (master == NULL) { | |
856 | ret = -ENOMEM; | |
857 | goto err; | |
858 | } | |
859 | ||
24b5a82c | 860 | platform_set_drvdata(pdev, master); |
358934a6 | 861 | |
212d4b69 | 862 | dspi = spi_master_get_devdata(master); |
358934a6 | 863 | |
8074cf06 JH |
864 | if (dev_get_platdata(&pdev->dev)) { |
865 | pdata = dev_get_platdata(&pdev->dev); | |
aae7147d MK |
866 | dspi->pdata = *pdata; |
867 | } else { | |
868 | /* update dspi pdata with that from the DT */ | |
869 | ret = spi_davinci_get_pdata(pdev, dspi); | |
870 | if (ret < 0) | |
871 | goto free_master; | |
872 | } | |
873 | ||
874 | /* pdata in dspi is now updated and point pdata to that */ | |
875 | pdata = &dspi->pdata; | |
876 | ||
7480e755 MK |
877 | dspi->bytes_per_word = devm_kzalloc(&pdev->dev, |
878 | sizeof(*dspi->bytes_per_word) * | |
879 | pdata->num_chipselect, GFP_KERNEL); | |
880 | if (dspi->bytes_per_word == NULL) { | |
881 | ret = -ENOMEM; | |
882 | goto free_master; | |
883 | } | |
884 | ||
358934a6 SP |
885 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
886 | if (r == NULL) { | |
887 | ret = -ENOENT; | |
888 | goto free_master; | |
889 | } | |
890 | ||
212d4b69 | 891 | dspi->pbase = r->start; |
358934a6 | 892 | |
5b3bb596 JH |
893 | dspi->base = devm_ioremap_resource(&pdev->dev, r); |
894 | if (IS_ERR(dspi->base)) { | |
895 | ret = PTR_ERR(dspi->base); | |
358934a6 SP |
896 | goto free_master; |
897 | } | |
898 | ||
212d4b69 SN |
899 | dspi->irq = platform_get_irq(pdev, 0); |
900 | if (dspi->irq <= 0) { | |
e0d205e9 | 901 | ret = -EINVAL; |
5b3bb596 | 902 | goto free_master; |
e0d205e9 BN |
903 | } |
904 | ||
5b3bb596 JH |
905 | ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, |
906 | dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); | |
e0d205e9 | 907 | if (ret) |
5b3bb596 | 908 | goto free_master; |
e0d205e9 | 909 | |
94c69f76 | 910 | dspi->bitbang.master = master; |
358934a6 | 911 | |
5b3bb596 | 912 | dspi->clk = devm_clk_get(&pdev->dev, NULL); |
212d4b69 | 913 | if (IS_ERR(dspi->clk)) { |
358934a6 | 914 | ret = -ENODEV; |
5b3bb596 | 915 | goto free_master; |
358934a6 | 916 | } |
aae7147d | 917 | clk_prepare_enable(dspi->clk); |
358934a6 | 918 | |
aae7147d | 919 | master->dev.of_node = pdev->dev.of_node; |
358934a6 SP |
920 | master->bus_num = pdev->id; |
921 | master->num_chipselect = pdata->num_chipselect; | |
24778be2 | 922 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); |
358934a6 | 923 | master->setup = davinci_spi_setup; |
358934a6 | 924 | |
212d4b69 SN |
925 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
926 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
358934a6 | 927 | |
212d4b69 | 928 | dspi->version = pdata->version; |
358934a6 | 929 | |
212d4b69 SN |
930 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; |
931 | if (dspi->version == SPI_VERSION_2) | |
932 | dspi->bitbang.flags |= SPI_READY; | |
358934a6 | 933 | |
903ca25b SN |
934 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
935 | if (r) | |
936 | dma_rx_chan = r->start; | |
937 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
938 | if (r) | |
939 | dma_tx_chan = r->start; | |
903ca25b | 940 | |
212d4b69 | 941 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
903ca25b | 942 | if (dma_rx_chan != SPI_NO_RESOURCE && |
2e3e2a5e | 943 | dma_tx_chan != SPI_NO_RESOURCE) { |
048177ce MP |
944 | dspi->dma_rx_chnum = dma_rx_chan; |
945 | dspi->dma_tx_chnum = dma_tx_chan; | |
96fd881f | 946 | |
212d4b69 | 947 | ret = davinci_spi_request_dma(dspi); |
903ca25b SN |
948 | if (ret) |
949 | goto free_clk; | |
950 | ||
87467bd9 | 951 | dev_info(&pdev->dev, "DMA: supported\n"); |
a4ee96e4 SS |
952 | dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, " |
953 | "event queue: %d\n", &dma_rx_chan, &dma_tx_chan, | |
2e3e2a5e | 954 | pdata->dma_event_q); |
358934a6 SP |
955 | } |
956 | ||
212d4b69 SN |
957 | dspi->get_rx = davinci_spi_rx_buf_u8; |
958 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
358934a6 | 959 | |
212d4b69 | 960 | init_completion(&dspi->done); |
e0d205e9 | 961 | |
358934a6 | 962 | /* Reset In/OUT SPI module */ |
212d4b69 | 963 | iowrite32(0, dspi->base + SPIGCR0); |
358934a6 | 964 | udelay(100); |
212d4b69 | 965 | iowrite32(1, dspi->base + SPIGCR0); |
358934a6 | 966 | |
be88471b | 967 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc | 968 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
212d4b69 | 969 | iowrite32(spipc0, dspi->base + SPIPC0); |
f34bd4cc | 970 | |
23853973 BN |
971 | /* initialize chip selects */ |
972 | if (pdata->chip_sel) { | |
973 | for (i = 0; i < pdata->num_chipselect; i++) { | |
974 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
975 | gpio_direction_output(pdata->chip_sel[i], 1); | |
976 | } | |
977 | } | |
978 | ||
e0d205e9 | 979 | if (pdata->intr_line) |
212d4b69 | 980 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
e0d205e9 | 981 | else |
212d4b69 | 982 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
e0d205e9 | 983 | |
212d4b69 | 984 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
843a713b | 985 | |
358934a6 | 986 | /* master mode default */ |
212d4b69 SN |
987 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
988 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
989 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
358934a6 | 990 | |
212d4b69 | 991 | ret = spi_bitbang_start(&dspi->bitbang); |
358934a6 | 992 | if (ret) |
903ca25b | 993 | goto free_dma; |
358934a6 | 994 | |
212d4b69 | 995 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
358934a6 | 996 | |
358934a6 SP |
997 | return ret; |
998 | ||
903ca25b | 999 | free_dma: |
048177ce MP |
1000 | dma_release_channel(dspi->dma_rx); |
1001 | dma_release_channel(dspi->dma_tx); | |
358934a6 | 1002 | free_clk: |
aae7147d | 1003 | clk_disable_unprepare(dspi->clk); |
358934a6 | 1004 | free_master: |
94c69f76 | 1005 | spi_master_put(master); |
358934a6 SP |
1006 | err: |
1007 | return ret; | |
1008 | } | |
1009 | ||
1010 | /** | |
1011 | * davinci_spi_remove - remove function for SPI Master Controller | |
1012 | * @pdev: platform_device structure which contains plateform specific data | |
1013 | * | |
1014 | * This function will do the reverse action of davinci_spi_probe function | |
1015 | * It will free the IRQ and SPI controller's memory region. | |
1016 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1017 | * created by spi_bitbang_start. | |
1018 | */ | |
fd4a319b | 1019 | static int davinci_spi_remove(struct platform_device *pdev) |
358934a6 | 1020 | { |
212d4b69 | 1021 | struct davinci_spi *dspi; |
358934a6 SP |
1022 | struct spi_master *master; |
1023 | ||
24b5a82c | 1024 | master = platform_get_drvdata(pdev); |
212d4b69 | 1025 | dspi = spi_master_get_devdata(master); |
358934a6 | 1026 | |
212d4b69 | 1027 | spi_bitbang_stop(&dspi->bitbang); |
358934a6 | 1028 | |
aae7147d | 1029 | clk_disable_unprepare(dspi->clk); |
94c69f76 | 1030 | spi_master_put(master); |
358934a6 SP |
1031 | |
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | static struct platform_driver davinci_spi_driver = { | |
d8c174cd BN |
1036 | .driver = { |
1037 | .name = "spi_davinci", | |
1038 | .owner = THIS_MODULE, | |
b53b34f0 | 1039 | .of_match_table = of_match_ptr(davinci_spi_of_match), |
d8c174cd | 1040 | }, |
940ab889 | 1041 | .probe = davinci_spi_probe, |
fd4a319b | 1042 | .remove = davinci_spi_remove, |
358934a6 | 1043 | }; |
940ab889 | 1044 | module_platform_driver(davinci_spi_driver); |
358934a6 SP |
1045 | |
1046 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1047 | MODULE_LICENSE("GPL"); |