[deliverable/linux.git] / drivers / spi / spi-dw-mid.c

/*
 * Special handling for DW core on Intel MID platform
 *
 * Copyright (c) 2009, 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/types.h>

#include "spi-dw.h"

#ifdef CONFIG_SPI_DW_MID_DMA
#include <linux/intel_mid_dma.h>
#include <linux/pci.h>

struct mid_dma {
	struct intel_mid_dma_slave	dmas_tx;
	struct intel_mid_dma_slave	dmas_rx;
};

static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
	struct dw_spi *dws = param;

	return dws->dma_dev == chan->device->dev;
}

static int mid_spi_dma_init(struct dw_spi *dws)
{
	struct mid_dma *dw_dma = dws->dma_priv;
	struct pci_dev *dma_dev;
	struct intel_mid_dma_slave *rxs, *txs;
	dma_cap_mask_t mask;

	/*
	 * Get pci device for DMA controller, currently it could only
	 * be the DMA controller of Medfield
	 */
	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	if (!dma_dev)
		return -ENODEV;

	dws->dma_dev = &dma_dev->dev;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/* 1. Init rx channel */
	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->rxchan)
		goto err_exit;
	rxs = &dw_dma->dmas_rx;
	rxs->hs_mode = LNW_DMA_HW_HS;
	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	dws->rxchan->private = rxs;

	/* 2. Init tx channel */
	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->txchan)
		goto free_rxchan;
	txs = &dw_dma->dmas_tx;
	txs->hs_mode = LNW_DMA_HW_HS;
	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	dws->txchan->private = txs;

	dws->dma_inited = 1;
	return 0;

free_rxchan:
	dma_release_channel(dws->rxchan);
err_exit:
	return -EBUSY;
}

static void mid_spi_dma_exit(struct dw_spi *dws)
{
	if (!dws->dma_inited)
		return;
	dma_release_channel(dws->txchan);
	dma_release_channel(dws->rxchan);
}

/*
 * dws->dma_chan_done is cleared before the dma transfer starts,
 * callback for rx/tx channel will each increment it by 1.
 * Reaching 2 means the whole spi transaction is done.
 */
static void dw_spi_dma_done(void *arg)
{
	struct dw_spi *dws = arg;

	if (++dws->dma_chan_done != 2)
		return;
	dw_spi_xfer_done(dws);
}

static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
{
	struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
	struct dma_chan *txchan, *rxchan;
	struct dma_slave_config txconf, rxconf;
	u16 dma_ctrl = 0;

	/* 1. setup DMA related registers */
	if (cs_change) {
		spi_enable_chip(dws, 0);
		dw_writew(dws, DW_SPI_DMARDLR, 0xf);
		dw_writew(dws, DW_SPI_DMATDLR, 0x10);
		if (dws->tx_dma)
			dma_ctrl |= 0x2;
		if (dws->rx_dma)
			dma_ctrl |= 0x1;
		dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
		spi_enable_chip(dws, 1);
	}

	dws->dma_chan_done = 0;
	txchan = dws->txchan;
	rxchan = dws->rxchan;

	/* 2. Prepare the TX dma transfer */
	txconf.direction = DMA_MEM_TO_DEV;
	txconf.dst_addr = dws->dma_addr;
	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	txconf.device_fc = false;

	txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
				       (unsigned long) &txconf);

	memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
	dws->tx_sgl.dma_address = dws->tx_dma;
	dws->tx_sgl.length = dws->len;

	txdesc = dmaengine_prep_slave_sg(txchan,
				&dws->tx_sgl,
				1,
				DMA_MEM_TO_DEV,
				DMA_PREP_INTERRUPT);
	txdesc->callback = dw_spi_dma_done;
	txdesc->callback_param = dws;

	/* 3. Prepare the RX dma transfer */
	rxconf.direction = DMA_DEV_TO_MEM;
	rxconf.src_addr = dws->dma_addr;
	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	rxconf.device_fc = false;

	rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
				       (unsigned long) &rxconf);

	memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
	dws->rx_sgl.dma_address = dws->rx_dma;
	dws->rx_sgl.length = dws->len;

	rxdesc = dmaengine_prep_slave_sg(rxchan,
				&dws->rx_sgl,
				1,
				DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT);
	rxdesc->callback = dw_spi_dma_done;
	rxdesc->callback_param = dws;

	/* rx must be started before tx due to spi instinct */
	rxdesc->tx_submit(rxdesc);
	txdesc->tx_submit(txdesc);
	return 0;
}

static struct dw_spi_dma_ops mid_dma_ops = {
	.dma_init	= mid_spi_dma_init,
	.dma_exit	= mid_spi_dma_exit,
	.dma_transfer	= mid_spi_dma_transfer,
};
#endif

/* Some specific info for SPI0 controller on Intel MID */

/* HW info for MRST CLk Control Unit, one 32b reg */
#define MRST_SPI_CLK_BASE	100000000	/* 100m */
#define MRST_CLK_SPI0_REG	0xff11d86c
#define CLK_SPI_BDIV_OFFSET	0
#define CLK_SPI_BDIV_MASK	0x00000007
#define CLK_SPI_CDIV_OFFSET	9
#define CLK_SPI_CDIV_MASK	0x00000e00
#define CLK_SPI_DISABLE_OFFSET	8

int dw_spi_mid_init(struct dw_spi *dws)
{
	void __iomem *clk_reg;
	u32 clk_cdiv;

	clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
	if (!clk_reg)
		return -ENOMEM;

	/* get SPI controller operating freq info */
	clk_cdiv  = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
	iounmap(clk_reg);

	dws->num_cs = 16;
	dws->fifo_len = 40;	/* FIFO has 40 words buffer */

#ifdef CONFIG_SPI_DW_MID_DMA
	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	if (!dws->dma_priv)
		return -ENOMEM;
	dws->dma_ops = &mid_dma_ops;
#endif
	return 0;
}
Commit	Line	Data
7063c0d9	1	/*
ca632f55	2	* Special handling for DW core on Intel MID platform
7063c0d9	3	*
197e96b4	4	* Copyright (c) 2009, 2014 Intel Corporation.
7063c0d9 FT	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
7063c0d9 FT	14	*/
	15
	16	#include <linux/dma-mapping.h>
	17	#include <linux/dmaengine.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/slab.h>
	20	#include <linux/spi/spi.h>
258aea76	21	#include <linux/types.h>
568a60ed	22
ca632f55	23	#include "spi-dw.h"
7063c0d9 FT	24
	25	#ifdef CONFIG_SPI_DW_MID_DMA
	26	#include <linux/intel_mid_dma.h>
	27	#include <linux/pci.h>
	28
	29	struct mid_dma {
	30	struct intel_mid_dma_slave dmas_tx;
	31	struct intel_mid_dma_slave dmas_rx;
	32	};
	33
	34	static bool mid_spi_dma_chan_filter(struct dma_chan chan, void param)
	35	{
	36	struct dw_spi *dws = param;
	37
b89e9c87	38	return dws->dma_dev == chan->device->dev;
7063c0d9 FT	39	}
	40
	41	static int mid_spi_dma_init(struct dw_spi *dws)
	42	{
	43	struct mid_dma *dw_dma = dws->dma_priv;
b89e9c87	44	struct pci_dev *dma_dev;
7063c0d9 FT	45	struct intel_mid_dma_slave rxs, txs;
	46	dma_cap_mask_t mask;
	47
	48	/*
	49	* Get pci device for DMA controller, currently it could only
ea092455	50	* be the DMA controller of Medfield
7063c0d9	51	*/
b89e9c87 AS	52	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	53	if (!dma_dev)
	54	return -ENODEV;
	55
	56	dws->dma_dev = &dma_dev->dev;
7063c0d9 FT	57
	58	dma_cap_zero(mask);
	59	dma_cap_set(DMA_SLAVE, mask);
	60
	61	/* 1. Init rx channel */
	62	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	63	if (!dws->rxchan)
	64	goto err_exit;
	65	rxs = &dw_dma->dmas_rx;
	66	rxs->hs_mode = LNW_DMA_HW_HS;
	67	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	68	dws->rxchan->private = rxs;
	69
	70	/* 2. Init tx channel */
	71	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	72	if (!dws->txchan)
	73	goto free_rxchan;
	74	txs = &dw_dma->dmas_tx;
	75	txs->hs_mode = LNW_DMA_HW_HS;
	76	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	77	dws->txchan->private = txs;
	78
	79	dws->dma_inited = 1;
	80	return 0;
	81
	82	free_rxchan:
	83	dma_release_channel(dws->rxchan);
	84	err_exit:
b89e9c87	85	return -EBUSY;
7063c0d9 FT	86	}
	87
	88	static void mid_spi_dma_exit(struct dw_spi *dws)
	89	{
fb57862e AS	90	if (!dws->dma_inited)
fb57862e AS	91	return;
7063c0d9 FT	92	dma_release_channel(dws->txchan);
	93	dma_release_channel(dws->rxchan);
	94	}
	95
	96	/*
	97	* dws->dma_chan_done is cleared before the dma transfer starts,
	98	* callback for rx/tx channel will each increment it by 1.
	99	* Reaching 2 means the whole spi transaction is done.
	100	*/
	101	static void dw_spi_dma_done(void *arg)
	102	{
	103	struct dw_spi *dws = arg;
	104
	105	if (++dws->dma_chan_done != 2)
	106	return;
	107	dw_spi_xfer_done(dws);
	108	}
	109
	110	static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
	111	{
	112	struct dma_async_tx_descriptor txdesc = NULL, rxdesc = NULL;
	113	struct dma_chan txchan, rxchan;
	114	struct dma_slave_config txconf, rxconf;
	115	u16 dma_ctrl = 0;
	116
	117	/* 1. setup DMA related registers */
	118	if (cs_change) {
	119	spi_enable_chip(dws, 0);
7eb187b3 HS	120	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
7eb187b3 HS	121	dw_writew(dws, DW_SPI_DMATDLR, 0x10);
7063c0d9 FT	122	if (dws->tx_dma)
	123	dma_ctrl \|= 0x2;
	124	if (dws->rx_dma)
	125	dma_ctrl \|= 0x1;
7eb187b3	126	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
7063c0d9 FT	127	spi_enable_chip(dws, 1);
	128	}
	129
	130	dws->dma_chan_done = 0;
	131	txchan = dws->txchan;
	132	rxchan = dws->rxchan;
	133
	134	/* 2. Prepare the TX dma transfer */
a485df4b	135	txconf.direction = DMA_MEM_TO_DEV;
7063c0d9 FT	136	txconf.dst_addr = dws->dma_addr;
	137	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	138	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	139	txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
258aea76	140	txconf.device_fc = false;
7063c0d9 FT	141
	142	txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
	143	(unsigned long) &txconf);
	144
	145	memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
	146	dws->tx_sgl.dma_address = dws->tx_dma;
	147	dws->tx_sgl.length = dws->len;
	148
16052827	149	txdesc = dmaengine_prep_slave_sg(txchan,
7063c0d9 FT	150	&dws->tx_sgl,
7063c0d9 FT	151	1,
a485df4b	152	DMA_MEM_TO_DEV,
0776ae7b	153	DMA_PREP_INTERRUPT);
7063c0d9 FT	154	txdesc->callback = dw_spi_dma_done;
	155	txdesc->callback_param = dws;
	156
	157	/* 3. Prepare the RX dma transfer */
a485df4b	158	rxconf.direction = DMA_DEV_TO_MEM;
7063c0d9 FT	159	rxconf.src_addr = dws->dma_addr;
	160	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	161	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	162	rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
258aea76	163	rxconf.device_fc = false;
7063c0d9 FT	164
	165	rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
	166	(unsigned long) &rxconf);
	167
	168	memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
	169	dws->rx_sgl.dma_address = dws->rx_dma;
	170	dws->rx_sgl.length = dws->len;
	171
16052827	172	rxdesc = dmaengine_prep_slave_sg(rxchan,
7063c0d9 FT	173	&dws->rx_sgl,
7063c0d9 FT	174	1,
a485df4b	175	DMA_DEV_TO_MEM,
0776ae7b	176	DMA_PREP_INTERRUPT);
7063c0d9 FT	177	rxdesc->callback = dw_spi_dma_done;
	178	rxdesc->callback_param = dws;
	179
	180	/* rx must be started before tx due to spi instinct */
	181	rxdesc->tx_submit(rxdesc);
	182	txdesc->tx_submit(txdesc);
	183	return 0;
	184	}
	185
	186	static struct dw_spi_dma_ops mid_dma_ops = {
	187	.dma_init = mid_spi_dma_init,
	188	.dma_exit = mid_spi_dma_exit,
	189	.dma_transfer = mid_spi_dma_transfer,
	190	};
	191	#endif
	192
ea092455	193	/* Some specific info for SPI0 controller on Intel MID */
7063c0d9 FT	194
	195	/* HW info for MRST CLk Control Unit, one 32b reg */
	196	#define MRST_SPI_CLK_BASE 100000000 /* 100m */
	197	#define MRST_CLK_SPI0_REG 0xff11d86c
	198	#define CLK_SPI_BDIV_OFFSET 0
	199	#define CLK_SPI_BDIV_MASK 0x00000007
	200	#define CLK_SPI_CDIV_OFFSET 9
	201	#define CLK_SPI_CDIV_MASK 0x00000e00
	202	#define CLK_SPI_DISABLE_OFFSET 8
	203
	204	int dw_spi_mid_init(struct dw_spi *dws)
	205	{
7eb187b3 HS	206	void __iomem *clk_reg;
7eb187b3 HS	207	u32 clk_cdiv;
7063c0d9 FT	208
	209	clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
	210	if (!clk_reg)
	211	return -ENOMEM;
	212
	213	/* get SPI controller operating freq info */
	214	clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
	215	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
	216	iounmap(clk_reg);
	217
	218	dws->num_cs = 16;
	219	dws->fifo_len = 40; /* FIFO has 40 words buffer */
	220
	221	#ifdef CONFIG_SPI_DW_MID_DMA
	222	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	223	if (!dws->dma_priv)
	224	return -ENOMEM;
	225	dws->dma_ops = &mid_dma_ops;
	226	#endif
	227	return 0;
	228	}