Commit | Line | Data |
---|---|---|
7063c0d9 | 1 | /* |
ca632f55 | 2 | * Special handling for DW core on Intel MID platform |
7063c0d9 | 3 | * |
197e96b4 | 4 | * Copyright (c) 2009, 2014 Intel Corporation. |
7063c0d9 FT |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
7063c0d9 FT |
14 | */ |
15 | ||
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/dmaengine.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/spi/spi.h> | |
258aea76 | 21 | #include <linux/types.h> |
568a60ed | 22 | |
ca632f55 | 23 | #include "spi-dw.h" |
7063c0d9 FT |
24 | |
25 | #ifdef CONFIG_SPI_DW_MID_DMA | |
26 | #include <linux/intel_mid_dma.h> | |
27 | #include <linux/pci.h> | |
28 | ||
30c8eb52 AS |
29 | #define RX_BUSY 0 |
30 | #define TX_BUSY 1 | |
31 | ||
7063c0d9 FT |
32 | struct mid_dma { |
33 | struct intel_mid_dma_slave dmas_tx; | |
34 | struct intel_mid_dma_slave dmas_rx; | |
35 | }; | |
36 | ||
37 | static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param) | |
38 | { | |
39 | struct dw_spi *dws = param; | |
40 | ||
b89e9c87 | 41 | return dws->dma_dev == chan->device->dev; |
7063c0d9 FT |
42 | } |
43 | ||
44 | static int mid_spi_dma_init(struct dw_spi *dws) | |
45 | { | |
46 | struct mid_dma *dw_dma = dws->dma_priv; | |
b89e9c87 | 47 | struct pci_dev *dma_dev; |
7063c0d9 FT |
48 | struct intel_mid_dma_slave *rxs, *txs; |
49 | dma_cap_mask_t mask; | |
50 | ||
51 | /* | |
52 | * Get pci device for DMA controller, currently it could only | |
ea092455 | 53 | * be the DMA controller of Medfield |
7063c0d9 | 54 | */ |
b89e9c87 AS |
55 | dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL); |
56 | if (!dma_dev) | |
57 | return -ENODEV; | |
58 | ||
59 | dws->dma_dev = &dma_dev->dev; | |
7063c0d9 FT |
60 | |
61 | dma_cap_zero(mask); | |
62 | dma_cap_set(DMA_SLAVE, mask); | |
63 | ||
64 | /* 1. Init rx channel */ | |
65 | dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws); | |
66 | if (!dws->rxchan) | |
67 | goto err_exit; | |
68 | rxs = &dw_dma->dmas_rx; | |
69 | rxs->hs_mode = LNW_DMA_HW_HS; | |
70 | rxs->cfg_mode = LNW_DMA_PER_TO_MEM; | |
71 | dws->rxchan->private = rxs; | |
72 | ||
73 | /* 2. Init tx channel */ | |
74 | dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws); | |
75 | if (!dws->txchan) | |
76 | goto free_rxchan; | |
77 | txs = &dw_dma->dmas_tx; | |
78 | txs->hs_mode = LNW_DMA_HW_HS; | |
79 | txs->cfg_mode = LNW_DMA_MEM_TO_PER; | |
80 | dws->txchan->private = txs; | |
81 | ||
82 | dws->dma_inited = 1; | |
83 | return 0; | |
84 | ||
85 | free_rxchan: | |
86 | dma_release_channel(dws->rxchan); | |
87 | err_exit: | |
b89e9c87 | 88 | return -EBUSY; |
7063c0d9 FT |
89 | } |
90 | ||
91 | static void mid_spi_dma_exit(struct dw_spi *dws) | |
92 | { | |
fb57862e AS |
93 | if (!dws->dma_inited) |
94 | return; | |
8e45ef68 AS |
95 | |
96 | dmaengine_terminate_all(dws->txchan); | |
7063c0d9 | 97 | dma_release_channel(dws->txchan); |
8e45ef68 AS |
98 | |
99 | dmaengine_terminate_all(dws->rxchan); | |
7063c0d9 FT |
100 | dma_release_channel(dws->rxchan); |
101 | } | |
102 | ||
e31abce7 AS |
103 | static enum dma_slave_buswidth convert_dma_width(u32 dma_width) { |
104 | if (dma_width == 1) | |
105 | return DMA_SLAVE_BUSWIDTH_1_BYTE; | |
106 | else if (dma_width == 2) | |
107 | return DMA_SLAVE_BUSWIDTH_2_BYTES; | |
108 | ||
109 | return DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
110 | } | |
111 | ||
7063c0d9 | 112 | /* |
30c8eb52 AS |
113 | * dws->dma_chan_busy is set before the dma transfer starts, callback for tx |
114 | * channel will clear a corresponding bit. | |
7063c0d9 | 115 | */ |
30c8eb52 | 116 | static void dw_spi_dma_tx_done(void *arg) |
7063c0d9 FT |
117 | { |
118 | struct dw_spi *dws = arg; | |
119 | ||
854d2f24 AS |
120 | clear_bit(TX_BUSY, &dws->dma_chan_busy); |
121 | if (test_bit(RX_BUSY, &dws->dma_chan_busy)) | |
7063c0d9 | 122 | return; |
c22c62db | 123 | spi_finalize_current_transfer(dws->master); |
7063c0d9 FT |
124 | } |
125 | ||
a5c2db96 | 126 | static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws) |
7063c0d9 | 127 | { |
a5c2db96 AS |
128 | struct dma_slave_config txconf; |
129 | struct dma_async_tx_descriptor *txdesc; | |
7063c0d9 | 130 | |
30c8eb52 AS |
131 | if (!dws->tx_dma) |
132 | return NULL; | |
133 | ||
a485df4b | 134 | txconf.direction = DMA_MEM_TO_DEV; |
7063c0d9 FT |
135 | txconf.dst_addr = dws->dma_addr; |
136 | txconf.dst_maxburst = LNW_DMA_MSIZE_16; | |
137 | txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
e31abce7 | 138 | txconf.dst_addr_width = convert_dma_width(dws->dma_width); |
258aea76 | 139 | txconf.device_fc = false; |
7063c0d9 | 140 | |
2a285299 | 141 | dmaengine_slave_config(dws->txchan, &txconf); |
7063c0d9 FT |
142 | |
143 | memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl)); | |
144 | dws->tx_sgl.dma_address = dws->tx_dma; | |
145 | dws->tx_sgl.length = dws->len; | |
146 | ||
2a285299 | 147 | txdesc = dmaengine_prep_slave_sg(dws->txchan, |
7063c0d9 FT |
148 | &dws->tx_sgl, |
149 | 1, | |
a485df4b | 150 | DMA_MEM_TO_DEV, |
f7477c2b | 151 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
c9dafb27 AS |
152 | if (!txdesc) |
153 | return NULL; | |
154 | ||
30c8eb52 | 155 | txdesc->callback = dw_spi_dma_tx_done; |
7063c0d9 FT |
156 | txdesc->callback_param = dws; |
157 | ||
a5c2db96 AS |
158 | return txdesc; |
159 | } | |
160 | ||
30c8eb52 AS |
161 | /* |
162 | * dws->dma_chan_busy is set before the dma transfer starts, callback for rx | |
163 | * channel will clear a corresponding bit. | |
164 | */ | |
165 | static void dw_spi_dma_rx_done(void *arg) | |
166 | { | |
167 | struct dw_spi *dws = arg; | |
168 | ||
854d2f24 AS |
169 | clear_bit(RX_BUSY, &dws->dma_chan_busy); |
170 | if (test_bit(TX_BUSY, &dws->dma_chan_busy)) | |
30c8eb52 | 171 | return; |
c22c62db | 172 | spi_finalize_current_transfer(dws->master); |
30c8eb52 AS |
173 | } |
174 | ||
a5c2db96 AS |
175 | static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws) |
176 | { | |
177 | struct dma_slave_config rxconf; | |
178 | struct dma_async_tx_descriptor *rxdesc; | |
179 | ||
30c8eb52 AS |
180 | if (!dws->rx_dma) |
181 | return NULL; | |
182 | ||
a485df4b | 183 | rxconf.direction = DMA_DEV_TO_MEM; |
7063c0d9 FT |
184 | rxconf.src_addr = dws->dma_addr; |
185 | rxconf.src_maxburst = LNW_DMA_MSIZE_16; | |
186 | rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
e31abce7 | 187 | rxconf.src_addr_width = convert_dma_width(dws->dma_width); |
258aea76 | 188 | rxconf.device_fc = false; |
7063c0d9 | 189 | |
2a285299 | 190 | dmaengine_slave_config(dws->rxchan, &rxconf); |
7063c0d9 FT |
191 | |
192 | memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl)); | |
193 | dws->rx_sgl.dma_address = dws->rx_dma; | |
194 | dws->rx_sgl.length = dws->len; | |
195 | ||
2a285299 | 196 | rxdesc = dmaengine_prep_slave_sg(dws->rxchan, |
7063c0d9 FT |
197 | &dws->rx_sgl, |
198 | 1, | |
a485df4b | 199 | DMA_DEV_TO_MEM, |
f7477c2b | 200 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
c9dafb27 AS |
201 | if (!rxdesc) |
202 | return NULL; | |
203 | ||
30c8eb52 | 204 | rxdesc->callback = dw_spi_dma_rx_done; |
7063c0d9 FT |
205 | rxdesc->callback_param = dws; |
206 | ||
a5c2db96 AS |
207 | return rxdesc; |
208 | } | |
209 | ||
9f14538e | 210 | static int mid_spi_dma_setup(struct dw_spi *dws) |
a5c2db96 AS |
211 | { |
212 | u16 dma_ctrl = 0; | |
213 | ||
a5c2db96 AS |
214 | dw_writew(dws, DW_SPI_DMARDLR, 0xf); |
215 | dw_writew(dws, DW_SPI_DMATDLR, 0x10); | |
216 | ||
217 | if (dws->tx_dma) | |
218 | dma_ctrl |= SPI_DMA_TDMAE; | |
219 | if (dws->rx_dma) | |
220 | dma_ctrl |= SPI_DMA_RDMAE; | |
221 | dw_writew(dws, DW_SPI_DMACR, dma_ctrl); | |
222 | ||
9f14538e | 223 | return 0; |
a5c2db96 AS |
224 | } |
225 | ||
9f14538e | 226 | static int mid_spi_dma_transfer(struct dw_spi *dws) |
a5c2db96 AS |
227 | { |
228 | struct dma_async_tx_descriptor *txdesc, *rxdesc; | |
229 | ||
9f14538e | 230 | /* Prepare the TX dma transfer */ |
a5c2db96 AS |
231 | txdesc = dw_spi_dma_prepare_tx(dws); |
232 | ||
9f14538e | 233 | /* Prepare the RX dma transfer */ |
a5c2db96 AS |
234 | rxdesc = dw_spi_dma_prepare_rx(dws); |
235 | ||
7063c0d9 | 236 | /* rx must be started before tx due to spi instinct */ |
30c8eb52 AS |
237 | if (rxdesc) { |
238 | set_bit(RX_BUSY, &dws->dma_chan_busy); | |
239 | dmaengine_submit(rxdesc); | |
240 | dma_async_issue_pending(dws->rxchan); | |
241 | } | |
242 | ||
243 | if (txdesc) { | |
244 | set_bit(TX_BUSY, &dws->dma_chan_busy); | |
245 | dmaengine_submit(txdesc); | |
246 | dma_async_issue_pending(dws->txchan); | |
247 | } | |
f7477c2b | 248 | |
7063c0d9 FT |
249 | return 0; |
250 | } | |
251 | ||
252 | static struct dw_spi_dma_ops mid_dma_ops = { | |
253 | .dma_init = mid_spi_dma_init, | |
254 | .dma_exit = mid_spi_dma_exit, | |
9f14538e | 255 | .dma_setup = mid_spi_dma_setup, |
7063c0d9 FT |
256 | .dma_transfer = mid_spi_dma_transfer, |
257 | }; | |
258 | #endif | |
259 | ||
ea092455 | 260 | /* Some specific info for SPI0 controller on Intel MID */ |
7063c0d9 | 261 | |
d9c14743 | 262 | /* HW info for MRST Clk Control Unit, 32b reg per controller */ |
7063c0d9 | 263 | #define MRST_SPI_CLK_BASE 100000000 /* 100m */ |
d9c14743 | 264 | #define MRST_CLK_SPI_REG 0xff11d86c |
7063c0d9 FT |
265 | #define CLK_SPI_BDIV_OFFSET 0 |
266 | #define CLK_SPI_BDIV_MASK 0x00000007 | |
267 | #define CLK_SPI_CDIV_OFFSET 9 | |
268 | #define CLK_SPI_CDIV_MASK 0x00000e00 | |
269 | #define CLK_SPI_DISABLE_OFFSET 8 | |
270 | ||
271 | int dw_spi_mid_init(struct dw_spi *dws) | |
272 | { | |
7eb187b3 HS |
273 | void __iomem *clk_reg; |
274 | u32 clk_cdiv; | |
7063c0d9 | 275 | |
d9c14743 | 276 | clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16); |
7063c0d9 FT |
277 | if (!clk_reg) |
278 | return -ENOMEM; | |
279 | ||
d9c14743 AS |
280 | /* Get SPI controller operating freq info */ |
281 | clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32)); | |
282 | clk_cdiv &= CLK_SPI_CDIV_MASK; | |
283 | clk_cdiv >>= CLK_SPI_CDIV_OFFSET; | |
7063c0d9 | 284 | dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1); |
d9c14743 | 285 | |
7063c0d9 FT |
286 | iounmap(clk_reg); |
287 | ||
7063c0d9 FT |
288 | #ifdef CONFIG_SPI_DW_MID_DMA |
289 | dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL); | |
290 | if (!dws->dma_priv) | |
291 | return -ENOMEM; | |
292 | dws->dma_ops = &mid_dma_ops; | |
293 | #endif | |
294 | return 0; | |
295 | } |