[deliverable/linux.git] / drivers / spi / spi-dw-mid.c

/*
 * Special handling for DW core on Intel MID platform
 *
 * Copyright (c) 2009, 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/types.h>

#include "spi-dw.h"

#ifdef CONFIG_SPI_DW_MID_DMA
#include <linux/intel_mid_dma.h>
#include <linux/pci.h>

struct mid_dma {
	struct intel_mid_dma_slave	dmas_tx;
	struct intel_mid_dma_slave	dmas_rx;
};

static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
	struct dw_spi *dws = param;

	return dws->dma_dev == chan->device->dev;
}

static int mid_spi_dma_init(struct dw_spi *dws)
{
	struct mid_dma *dw_dma = dws->dma_priv;
	struct pci_dev *dma_dev;
	struct intel_mid_dma_slave *rxs, *txs;
	dma_cap_mask_t mask;

	/*
	 * Get pci device for DMA controller, currently it could only
	 * be the DMA controller of Medfield
	 */
	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	if (!dma_dev)
		return -ENODEV;

	dws->dma_dev = &dma_dev->dev;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/* 1. Init rx channel */
	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->rxchan)
		goto err_exit;
	rxs = &dw_dma->dmas_rx;
	rxs->hs_mode = LNW_DMA_HW_HS;
	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	dws->rxchan->private = rxs;

	/* 2. Init tx channel */
	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->txchan)
		goto free_rxchan;
	txs = &dw_dma->dmas_tx;
	txs->hs_mode = LNW_DMA_HW_HS;
	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	dws->txchan->private = txs;

	dws->dma_inited = 1;
	return 0;

free_rxchan:
	dma_release_channel(dws->rxchan);
err_exit:
	return -EBUSY;
}

static void mid_spi_dma_exit(struct dw_spi *dws)
{
	if (!dws->dma_inited)
		return;

	dmaengine_terminate_all(dws->txchan);
	dma_release_channel(dws->txchan);

	dmaengine_terminate_all(dws->rxchan);
	dma_release_channel(dws->rxchan);
}

/*
 * dws->dma_chan_done is cleared before the dma transfer starts,
 * callback for rx/tx channel will each increment it by 1.
 * Reaching 2 means the whole spi transaction is done.
 */
static void dw_spi_dma_done(void *arg)
{
	struct dw_spi *dws = arg;

	if (++dws->dma_chan_done != 2)
		return;
	dw_spi_xfer_done(dws);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
{
	struct dma_slave_config txconf;
	struct dma_async_tx_descriptor *txdesc;

	txconf.direction = DMA_MEM_TO_DEV;
	txconf.dst_addr = dws->dma_addr;
	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	txconf.dst_addr_width = dws->dma_width;
	txconf.device_fc = false;

	dmaengine_slave_config(dws->txchan, &txconf);

	memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
	dws->tx_sgl.dma_address = dws->tx_dma;
	dws->tx_sgl.length = dws->len;

	txdesc = dmaengine_prep_slave_sg(dws->txchan,
				&dws->tx_sgl,
				1,
				DMA_MEM_TO_DEV,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	txdesc->callback = dw_spi_dma_done;
	txdesc->callback_param = dws;

	return txdesc;
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
{
	struct dma_slave_config rxconf;
	struct dma_async_tx_descriptor *rxdesc;

	rxconf.direction = DMA_DEV_TO_MEM;
	rxconf.src_addr = dws->dma_addr;
	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	rxconf.src_addr_width = dws->dma_width;
	rxconf.device_fc = false;

	dmaengine_slave_config(dws->rxchan, &rxconf);

	memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
	dws->rx_sgl.dma_address = dws->rx_dma;
	dws->rx_sgl.length = dws->len;

	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
				&dws->rx_sgl,
				1,
				DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	rxdesc->callback = dw_spi_dma_done;
	rxdesc->callback_param = dws;

	return rxdesc;
}

static void dw_spi_dma_setup(struct dw_spi *dws)
{
	u16 dma_ctrl = 0;

	spi_enable_chip(dws, 0);

	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
	dw_writew(dws, DW_SPI_DMATDLR, 0x10);

	if (dws->tx_dma)
		dma_ctrl |= SPI_DMA_TDMAE;
	if (dws->rx_dma)
		dma_ctrl |= SPI_DMA_RDMAE;
	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);

	spi_enable_chip(dws, 1);
}

static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
{
	struct dma_async_tx_descriptor *txdesc, *rxdesc;

	/* 1. setup DMA related registers */
	if (cs_change)
		dw_spi_dma_setup(dws);

	dws->dma_chan_done = 0;

	/* 2. Prepare the TX dma transfer */
	txdesc = dw_spi_dma_prepare_tx(dws);

	/* 3. Prepare the RX dma transfer */
	rxdesc = dw_spi_dma_prepare_rx(dws);

	/* rx must be started before tx due to spi instinct */
	dmaengine_submit(rxdesc);
	dma_async_issue_pending(dws->rxchan);

	dmaengine_submit(txdesc);
	dma_async_issue_pending(dws->txchan);

	return 0;
}

static struct dw_spi_dma_ops mid_dma_ops = {
	.dma_init	= mid_spi_dma_init,
	.dma_exit	= mid_spi_dma_exit,
	.dma_transfer	= mid_spi_dma_transfer,
};
#endif

/* Some specific info for SPI0 controller on Intel MID */

/* HW info for MRST CLk Control Unit, one 32b reg */
#define MRST_SPI_CLK_BASE	100000000	/* 100m */
#define MRST_CLK_SPI0_REG	0xff11d86c
#define CLK_SPI_BDIV_OFFSET	0
#define CLK_SPI_BDIV_MASK	0x00000007
#define CLK_SPI_CDIV_OFFSET	9
#define CLK_SPI_CDIV_MASK	0x00000e00
#define CLK_SPI_DISABLE_OFFSET	8

int dw_spi_mid_init(struct dw_spi *dws)
{
	void __iomem *clk_reg;
	u32 clk_cdiv;

	clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
	if (!clk_reg)
		return -ENOMEM;

	/* get SPI controller operating freq info */
	clk_cdiv  = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
	iounmap(clk_reg);

	dws->num_cs = 16;
	dws->fifo_len = 40;	/* FIFO has 40 words buffer */

#ifdef CONFIG_SPI_DW_MID_DMA
	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	if (!dws->dma_priv)
		return -ENOMEM;
	dws->dma_ops = &mid_dma_ops;
#endif
	return 0;
}
Commit	Line	Data
7063c0d9	1	/*
ca632f55	2	* Special handling for DW core on Intel MID platform
7063c0d9	3	*
197e96b4	4	* Copyright (c) 2009, 2014 Intel Corporation.
7063c0d9 FT	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
7063c0d9 FT	14	*/
	15
	16	#include <linux/dma-mapping.h>
	17	#include <linux/dmaengine.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/slab.h>
	20	#include <linux/spi/spi.h>
258aea76	21	#include <linux/types.h>
568a60ed	22
ca632f55	23	#include "spi-dw.h"
7063c0d9 FT	24
	25	#ifdef CONFIG_SPI_DW_MID_DMA
	26	#include <linux/intel_mid_dma.h>
	27	#include <linux/pci.h>
	28
	29	struct mid_dma {
	30	struct intel_mid_dma_slave dmas_tx;
	31	struct intel_mid_dma_slave dmas_rx;
	32	};
	33
	34	static bool mid_spi_dma_chan_filter(struct dma_chan chan, void param)
	35	{
	36	struct dw_spi *dws = param;
	37
b89e9c87	38	return dws->dma_dev == chan->device->dev;
7063c0d9 FT	39	}
	40
	41	static int mid_spi_dma_init(struct dw_spi *dws)
	42	{
	43	struct mid_dma *dw_dma = dws->dma_priv;
b89e9c87	44	struct pci_dev *dma_dev;
7063c0d9 FT	45	struct intel_mid_dma_slave rxs, txs;
	46	dma_cap_mask_t mask;
	47
	48	/*
	49	* Get pci device for DMA controller, currently it could only
ea092455	50	* be the DMA controller of Medfield
7063c0d9	51	*/
b89e9c87 AS	52	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	53	if (!dma_dev)
	54	return -ENODEV;
	55
	56	dws->dma_dev = &dma_dev->dev;
7063c0d9 FT	57
	58	dma_cap_zero(mask);
	59	dma_cap_set(DMA_SLAVE, mask);
	60
	61	/* 1. Init rx channel */
	62	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	63	if (!dws->rxchan)
	64	goto err_exit;
	65	rxs = &dw_dma->dmas_rx;
	66	rxs->hs_mode = LNW_DMA_HW_HS;
	67	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	68	dws->rxchan->private = rxs;
	69
	70	/* 2. Init tx channel */
	71	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	72	if (!dws->txchan)
	73	goto free_rxchan;
	74	txs = &dw_dma->dmas_tx;
	75	txs->hs_mode = LNW_DMA_HW_HS;
	76	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	77	dws->txchan->private = txs;
	78
	79	dws->dma_inited = 1;
	80	return 0;
	81
	82	free_rxchan:
	83	dma_release_channel(dws->rxchan);
	84	err_exit:
b89e9c87	85	return -EBUSY;
7063c0d9 FT	86	}
	87
	88	static void mid_spi_dma_exit(struct dw_spi *dws)
	89	{
fb57862e AS	90	if (!dws->dma_inited)
fb57862e AS	91	return;
8e45ef68 AS	92
8e45ef68 AS	93	dmaengine_terminate_all(dws->txchan);
7063c0d9	94	dma_release_channel(dws->txchan);
8e45ef68 AS	95
8e45ef68 AS	96	dmaengine_terminate_all(dws->rxchan);
7063c0d9 FT	97	dma_release_channel(dws->rxchan);
	98	}
	99
	100	/*
	101	* dws->dma_chan_done is cleared before the dma transfer starts,
	102	* callback for rx/tx channel will each increment it by 1.
	103	* Reaching 2 means the whole spi transaction is done.
	104	*/
	105	static void dw_spi_dma_done(void *arg)
	106	{
	107	struct dw_spi *dws = arg;
	108
	109	if (++dws->dma_chan_done != 2)
	110	return;
	111	dw_spi_xfer_done(dws);
	112	}
	113
a5c2db96	114	static struct dma_async_tx_descriptor dw_spi_dma_prepare_tx(struct dw_spi dws)
7063c0d9	115	{
a5c2db96 AS	116	struct dma_slave_config txconf;
a5c2db96 AS	117	struct dma_async_tx_descriptor *txdesc;
7063c0d9	118
a485df4b	119	txconf.direction = DMA_MEM_TO_DEV;
7063c0d9 FT	120	txconf.dst_addr = dws->dma_addr;
	121	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	122	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
b41583e7	123	txconf.dst_addr_width = dws->dma_width;
258aea76	124	txconf.device_fc = false;
7063c0d9	125
2a285299	126	dmaengine_slave_config(dws->txchan, &txconf);
7063c0d9 FT	127
	128	memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
	129	dws->tx_sgl.dma_address = dws->tx_dma;
	130	dws->tx_sgl.length = dws->len;
	131
2a285299	132	txdesc = dmaengine_prep_slave_sg(dws->txchan,
7063c0d9 FT	133	&dws->tx_sgl,
7063c0d9 FT	134	1,
a485df4b	135	DMA_MEM_TO_DEV,
f7477c2b	136	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
7063c0d9 FT	137	txdesc->callback = dw_spi_dma_done;
	138	txdesc->callback_param = dws;
	139
a5c2db96 AS	140	return txdesc;
	141	}
	142
	143	static struct dma_async_tx_descriptor dw_spi_dma_prepare_rx(struct dw_spi dws)
	144	{
	145	struct dma_slave_config rxconf;
	146	struct dma_async_tx_descriptor *rxdesc;
	147
a485df4b	148	rxconf.direction = DMA_DEV_TO_MEM;
7063c0d9 FT	149	rxconf.src_addr = dws->dma_addr;
	150	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	151	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
b41583e7	152	rxconf.src_addr_width = dws->dma_width;
258aea76	153	rxconf.device_fc = false;
7063c0d9	154
2a285299	155	dmaengine_slave_config(dws->rxchan, &rxconf);
7063c0d9 FT	156
	157	memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
	158	dws->rx_sgl.dma_address = dws->rx_dma;
	159	dws->rx_sgl.length = dws->len;
	160
2a285299	161	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
7063c0d9 FT	162	&dws->rx_sgl,
7063c0d9 FT	163	1,
a485df4b	164	DMA_DEV_TO_MEM,
f7477c2b	165	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
7063c0d9 FT	166	rxdesc->callback = dw_spi_dma_done;
	167	rxdesc->callback_param = dws;
	168
a5c2db96 AS	169	return rxdesc;
	170	}
	171
	172	static void dw_spi_dma_setup(struct dw_spi *dws)
	173	{
	174	u16 dma_ctrl = 0;
	175
	176	spi_enable_chip(dws, 0);
	177
	178	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
	179	dw_writew(dws, DW_SPI_DMATDLR, 0x10);
	180
	181	if (dws->tx_dma)
	182	dma_ctrl \|= SPI_DMA_TDMAE;
	183	if (dws->rx_dma)
	184	dma_ctrl \|= SPI_DMA_RDMAE;
	185	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
	186
	187	spi_enable_chip(dws, 1);
	188	}
	189
	190	static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
	191	{
	192	struct dma_async_tx_descriptor txdesc, rxdesc;
	193
	194	/* 1. setup DMA related registers */
	195	if (cs_change)
	196	dw_spi_dma_setup(dws);
	197
	198	dws->dma_chan_done = 0;
	199
	200	/* 2. Prepare the TX dma transfer */
	201	txdesc = dw_spi_dma_prepare_tx(dws);
	202
	203	/* 3. Prepare the RX dma transfer */
	204	rxdesc = dw_spi_dma_prepare_rx(dws);
	205
7063c0d9	206	/* rx must be started before tx due to spi instinct */
2a285299	207	dmaengine_submit(rxdesc);
f7477c2b AS	208	dma_async_issue_pending(dws->rxchan);
f7477c2b AS	209
2a285299	210	dmaengine_submit(txdesc);
f7477c2b AS	211	dma_async_issue_pending(dws->txchan);
f7477c2b AS	212
7063c0d9 FT	213	return 0;
	214	}
	215
	216	static struct dw_spi_dma_ops mid_dma_ops = {
	217	.dma_init = mid_spi_dma_init,
	218	.dma_exit = mid_spi_dma_exit,
	219	.dma_transfer = mid_spi_dma_transfer,
	220	};
	221	#endif
	222
ea092455	223	/* Some specific info for SPI0 controller on Intel MID */
7063c0d9 FT	224
	225	/* HW info for MRST CLk Control Unit, one 32b reg */
	226	#define MRST_SPI_CLK_BASE 100000000 /* 100m */
	227	#define MRST_CLK_SPI0_REG 0xff11d86c
	228	#define CLK_SPI_BDIV_OFFSET 0
	229	#define CLK_SPI_BDIV_MASK 0x00000007
	230	#define CLK_SPI_CDIV_OFFSET 9
	231	#define CLK_SPI_CDIV_MASK 0x00000e00
	232	#define CLK_SPI_DISABLE_OFFSET 8
	233
	234	int dw_spi_mid_init(struct dw_spi *dws)
	235	{
7eb187b3 HS	236	void __iomem *clk_reg;
7eb187b3 HS	237	u32 clk_cdiv;
7063c0d9 FT	238
	239	clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
	240	if (!clk_reg)
	241	return -ENOMEM;
	242
	243	/* get SPI controller operating freq info */
	244	clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
	245	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
	246	iounmap(clk_reg);
	247
	248	dws->num_cs = 16;
	249	dws->fifo_len = 40; /* FIFO has 40 words buffer */
	250
	251	#ifdef CONFIG_SPI_DW_MID_DMA
	252	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	253	if (!dws->dma_priv)
	254	return -ENOMEM;
	255	dws->dma_ops = &mid_dma_ops;
	256	#endif
	257	return 0;
	258	}