[deliverable/linux.git] / drivers / spi / spi-dw-mid.c

/*
 * Special handling for DW core on Intel MID platform
 *
 * Copyright (c) 2009, 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/types.h>

#include "spi-dw.h"

#ifdef CONFIG_SPI_DW_MID_DMA
#include <linux/intel_mid_dma.h>
#include <linux/pci.h>

#define RX_BUSY		0
#define TX_BUSY		1

struct mid_dma {
	struct intel_mid_dma_slave	dmas_tx;
	struct intel_mid_dma_slave	dmas_rx;
};

static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
	struct dw_spi *dws = param;

	return dws->dma_dev == chan->device->dev;
}

static int mid_spi_dma_init(struct dw_spi *dws)
{
	struct mid_dma *dw_dma = dws->dma_priv;
	struct pci_dev *dma_dev;
	struct intel_mid_dma_slave *rxs, *txs;
	dma_cap_mask_t mask;

	/*
	 * Get pci device for DMA controller, currently it could only
	 * be the DMA controller of Medfield
	 */
	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	if (!dma_dev)
		return -ENODEV;

	dws->dma_dev = &dma_dev->dev;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/* 1. Init rx channel */
	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->rxchan)
		goto err_exit;
	rxs = &dw_dma->dmas_rx;
	rxs->hs_mode = LNW_DMA_HW_HS;
	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	dws->rxchan->private = rxs;
	dws->master->dma_rx = dws->rxchan;

	/* 2. Init tx channel */
	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->txchan)
		goto free_rxchan;
	txs = &dw_dma->dmas_tx;
	txs->hs_mode = LNW_DMA_HW_HS;
	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	dws->txchan->private = txs;
	dws->master->dma_tx = dws->txchan;

	dws->dma_inited = 1;
	return 0;

free_rxchan:
	dma_release_channel(dws->rxchan);
err_exit:
	return -EBUSY;
}

static void mid_spi_dma_exit(struct dw_spi *dws)
{
	if (!dws->dma_inited)
		return;

	dmaengine_terminate_all(dws->txchan);
	dma_release_channel(dws->txchan);

	dmaengine_terminate_all(dws->rxchan);
	dma_release_channel(dws->rxchan);
}

static irqreturn_t dma_transfer(struct dw_spi *dws)
{
	u16 irq_status = dw_readw(dws, DW_SPI_ISR);

	if (!irq_status)
		return IRQ_NONE;

	dw_readw(dws, DW_SPI_ICR);
	spi_reset_chip(dws);

	dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
	dws->master->cur_msg->status = -EIO;
	spi_finalize_current_transfer(dws->master);
	return IRQ_HANDLED;
}

static bool mid_spi_can_dma(struct spi_master *master, struct spi_device *spi,
		struct spi_transfer *xfer)
{
	struct dw_spi *dws = spi_master_get_devdata(master);

	if (!dws->dma_inited)
		return false;

	return xfer->len > dws->fifo_len;
}

static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
	if (dma_width == 1)
		return DMA_SLAVE_BUSWIDTH_1_BYTE;
	else if (dma_width == 2)
		return DMA_SLAVE_BUSWIDTH_2_BYTES;

	return DMA_SLAVE_BUSWIDTH_UNDEFINED;
}

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_tx_done(void *arg)
{
	struct dw_spi *dws = arg;

	clear_bit(TX_BUSY, &dws->dma_chan_busy);
	if (test_bit(RX_BUSY, &dws->dma_chan_busy))
		return;
	spi_finalize_current_transfer(dws->master);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
		struct spi_transfer *xfer)
{
	struct dma_slave_config txconf;
	struct dma_async_tx_descriptor *txdesc;

	if (!xfer->tx_buf)
		return NULL;

	txconf.direction = DMA_MEM_TO_DEV;
	txconf.dst_addr = dws->dma_addr;
	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	txconf.dst_addr_width = convert_dma_width(dws->dma_width);
	txconf.device_fc = false;

	dmaengine_slave_config(dws->txchan, &txconf);

	txdesc = dmaengine_prep_slave_sg(dws->txchan,
				xfer->tx_sg.sgl,
				xfer->tx_sg.nents,
				DMA_MEM_TO_DEV,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!txdesc)
		return NULL;

	txdesc->callback = dw_spi_dma_tx_done;
	txdesc->callback_param = dws;

	return txdesc;
}

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_rx_done(void *arg)
{
	struct dw_spi *dws = arg;

	clear_bit(RX_BUSY, &dws->dma_chan_busy);
	if (test_bit(TX_BUSY, &dws->dma_chan_busy))
		return;
	spi_finalize_current_transfer(dws->master);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
		struct spi_transfer *xfer)
{
	struct dma_slave_config rxconf;
	struct dma_async_tx_descriptor *rxdesc;

	if (!xfer->rx_buf)
		return NULL;

	rxconf.direction = DMA_DEV_TO_MEM;
	rxconf.src_addr = dws->dma_addr;
	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	rxconf.src_addr_width = convert_dma_width(dws->dma_width);
	rxconf.device_fc = false;

	dmaengine_slave_config(dws->rxchan, &rxconf);

	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
				xfer->rx_sg.sgl,
				xfer->rx_sg.nents,
				DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!rxdesc)
		return NULL;

	rxdesc->callback = dw_spi_dma_rx_done;
	rxdesc->callback_param = dws;

	return rxdesc;
}

static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
	u16 dma_ctrl = 0;

	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
	dw_writew(dws, DW_SPI_DMATDLR, 0x10);

	if (xfer->tx_buf)
		dma_ctrl |= SPI_DMA_TDMAE;
	if (xfer->rx_buf)
		dma_ctrl |= SPI_DMA_RDMAE;
	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);

	/* Set the interrupt mask */
	spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);

	dws->transfer_handler = dma_transfer;

	return 0;
}

static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
{
	struct dma_async_tx_descriptor *txdesc, *rxdesc;

	/* Prepare the TX dma transfer */
	txdesc = dw_spi_dma_prepare_tx(dws, xfer);

	/* Prepare the RX dma transfer */
	rxdesc = dw_spi_dma_prepare_rx(dws, xfer);

	/* rx must be started before tx due to spi instinct */
	if (rxdesc) {
		set_bit(RX_BUSY, &dws->dma_chan_busy);
		dmaengine_submit(rxdesc);
		dma_async_issue_pending(dws->rxchan);
	}

	if (txdesc) {
		set_bit(TX_BUSY, &dws->dma_chan_busy);
		dmaengine_submit(txdesc);
		dma_async_issue_pending(dws->txchan);
	}

	return 0;
}

static void mid_spi_dma_stop(struct dw_spi *dws)
{
	if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
		dmaengine_terminate_all(dws->txchan);
		clear_bit(TX_BUSY, &dws->dma_chan_busy);
	}
	if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
		dmaengine_terminate_all(dws->rxchan);
		clear_bit(RX_BUSY, &dws->dma_chan_busy);
	}
}

static struct dw_spi_dma_ops mid_dma_ops = {
	.dma_init	= mid_spi_dma_init,
	.dma_exit	= mid_spi_dma_exit,
	.dma_setup	= mid_spi_dma_setup,
	.can_dma	= mid_spi_can_dma,
	.dma_transfer	= mid_spi_dma_transfer,
	.dma_stop	= mid_spi_dma_stop,
};
#endif

/* Some specific info for SPI0 controller on Intel MID */

/* HW info for MRST Clk Control Unit, 32b reg per controller */
#define MRST_SPI_CLK_BASE	100000000	/* 100m */
#define MRST_CLK_SPI_REG	0xff11d86c
#define CLK_SPI_BDIV_OFFSET	0
#define CLK_SPI_BDIV_MASK	0x00000007
#define CLK_SPI_CDIV_OFFSET	9
#define CLK_SPI_CDIV_MASK	0x00000e00
#define CLK_SPI_DISABLE_OFFSET	8

int dw_spi_mid_init(struct dw_spi *dws)
{
	void __iomem *clk_reg;
	u32 clk_cdiv;

	clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
	if (!clk_reg)
		return -ENOMEM;

	/* Get SPI controller operating freq info */
	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
	clk_cdiv &= CLK_SPI_CDIV_MASK;
	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);

	iounmap(clk_reg);

#ifdef CONFIG_SPI_DW_MID_DMA
	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	if (!dws->dma_priv)
		return -ENOMEM;
	dws->dma_ops = &mid_dma_ops;
#endif
	return 0;
}
Commit	Line	Data
7063c0d9	1	/*
ca632f55	2	* Special handling for DW core on Intel MID platform
7063c0d9	3	*
197e96b4	4	* Copyright (c) 2009, 2014 Intel Corporation.
7063c0d9 FT	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
7063c0d9 FT	14	*/
	15
	16	#include <linux/dma-mapping.h>
	17	#include <linux/dmaengine.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/slab.h>
	20	#include <linux/spi/spi.h>
258aea76	21	#include <linux/types.h>
568a60ed	22
ca632f55	23	#include "spi-dw.h"
7063c0d9 FT	24
	25	#ifdef CONFIG_SPI_DW_MID_DMA
	26	#include <linux/intel_mid_dma.h>
	27	#include <linux/pci.h>
	28
30c8eb52 AS	29	#define RX_BUSY 0
	30	#define TX_BUSY 1
	31
7063c0d9 FT	32	struct mid_dma {
	33	struct intel_mid_dma_slave dmas_tx;
	34	struct intel_mid_dma_slave dmas_rx;
	35	};
	36
	37	static bool mid_spi_dma_chan_filter(struct dma_chan chan, void param)
	38	{
	39	struct dw_spi *dws = param;
	40
b89e9c87	41	return dws->dma_dev == chan->device->dev;
7063c0d9 FT	42	}
	43
	44	static int mid_spi_dma_init(struct dw_spi *dws)
	45	{
	46	struct mid_dma *dw_dma = dws->dma_priv;
b89e9c87	47	struct pci_dev *dma_dev;
7063c0d9 FT	48	struct intel_mid_dma_slave rxs, txs;
	49	dma_cap_mask_t mask;
	50
	51	/*
	52	* Get pci device for DMA controller, currently it could only
ea092455	53	* be the DMA controller of Medfield
7063c0d9	54	*/
b89e9c87 AS	55	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	56	if (!dma_dev)
	57	return -ENODEV;
	58
	59	dws->dma_dev = &dma_dev->dev;
7063c0d9 FT	60
	61	dma_cap_zero(mask);
	62	dma_cap_set(DMA_SLAVE, mask);
	63
	64	/* 1. Init rx channel */
	65	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	66	if (!dws->rxchan)
	67	goto err_exit;
	68	rxs = &dw_dma->dmas_rx;
	69	rxs->hs_mode = LNW_DMA_HW_HS;
	70	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	71	dws->rxchan->private = rxs;
f89a6d8f	72	dws->master->dma_rx = dws->rxchan;
7063c0d9 FT	73
	74	/* 2. Init tx channel */
	75	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	76	if (!dws->txchan)
	77	goto free_rxchan;
	78	txs = &dw_dma->dmas_tx;
	79	txs->hs_mode = LNW_DMA_HW_HS;
	80	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	81	dws->txchan->private = txs;
f89a6d8f	82	dws->master->dma_tx = dws->txchan;
7063c0d9 FT	83
	84	dws->dma_inited = 1;
	85	return 0;
	86
	87	free_rxchan:
	88	dma_release_channel(dws->rxchan);
	89	err_exit:
b89e9c87	90	return -EBUSY;
7063c0d9 FT	91	}
	92
	93	static void mid_spi_dma_exit(struct dw_spi *dws)
	94	{
fb57862e AS	95	if (!dws->dma_inited)
fb57862e AS	96	return;
8e45ef68 AS	97
8e45ef68 AS	98	dmaengine_terminate_all(dws->txchan);
7063c0d9	99	dma_release_channel(dws->txchan);
8e45ef68 AS	100
8e45ef68 AS	101	dmaengine_terminate_all(dws->rxchan);
7063c0d9 FT	102	dma_release_channel(dws->rxchan);
	103	}
	104
f051fc8f AS	105	static irqreturn_t dma_transfer(struct dw_spi *dws)
	106	{
	107	u16 irq_status = dw_readw(dws, DW_SPI_ISR);
	108
	109	if (!irq_status)
	110	return IRQ_NONE;
	111
	112	dw_readw(dws, DW_SPI_ICR);
	113	spi_reset_chip(dws);
	114
	115	dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
	116	dws->master->cur_msg->status = -EIO;
	117	spi_finalize_current_transfer(dws->master);
	118	return IRQ_HANDLED;
	119	}
	120
f89a6d8f AS	121	static bool mid_spi_can_dma(struct spi_master master, struct spi_device spi,
	122	struct spi_transfer *xfer)
	123	{
	124	struct dw_spi *dws = spi_master_get_devdata(master);
	125
	126	if (!dws->dma_inited)
	127	return false;
	128
	129	return xfer->len > dws->fifo_len;
	130	}
	131
e31abce7 AS	132	static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
	133	if (dma_width == 1)
	134	return DMA_SLAVE_BUSWIDTH_1_BYTE;
	135	else if (dma_width == 2)
	136	return DMA_SLAVE_BUSWIDTH_2_BYTES;
	137
	138	return DMA_SLAVE_BUSWIDTH_UNDEFINED;
	139	}
	140
7063c0d9	141	/*
30c8eb52 AS	142	* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
30c8eb52 AS	143	* channel will clear a corresponding bit.
7063c0d9	144	*/
30c8eb52	145	static void dw_spi_dma_tx_done(void *arg)
7063c0d9 FT	146	{
	147	struct dw_spi *dws = arg;
	148
854d2f24 AS	149	clear_bit(TX_BUSY, &dws->dma_chan_busy);
854d2f24 AS	150	if (test_bit(RX_BUSY, &dws->dma_chan_busy))
7063c0d9	151	return;
c22c62db	152	spi_finalize_current_transfer(dws->master);
7063c0d9 FT	153	}
7063c0d9 FT	154
f89a6d8f AS	155	static struct dma_async_tx_descriptor dw_spi_dma_prepare_tx(struct dw_spi dws,
f89a6d8f AS	156	struct spi_transfer *xfer)
7063c0d9	157	{
a5c2db96 AS	158	struct dma_slave_config txconf;
a5c2db96 AS	159	struct dma_async_tx_descriptor *txdesc;
7063c0d9	160
f89a6d8f	161	if (!xfer->tx_buf)
30c8eb52 AS	162	return NULL;
30c8eb52 AS	163
a485df4b	164	txconf.direction = DMA_MEM_TO_DEV;
7063c0d9 FT	165	txconf.dst_addr = dws->dma_addr;
	166	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	167	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
e31abce7	168	txconf.dst_addr_width = convert_dma_width(dws->dma_width);
258aea76	169	txconf.device_fc = false;
7063c0d9	170
2a285299	171	dmaengine_slave_config(dws->txchan, &txconf);
7063c0d9	172
2a285299	173	txdesc = dmaengine_prep_slave_sg(dws->txchan,
f89a6d8f AS	174	xfer->tx_sg.sgl,
f89a6d8f AS	175	xfer->tx_sg.nents,
a485df4b	176	DMA_MEM_TO_DEV,
f7477c2b	177	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
c9dafb27 AS	178	if (!txdesc)
	179	return NULL;
	180
30c8eb52	181	txdesc->callback = dw_spi_dma_tx_done;
7063c0d9 FT	182	txdesc->callback_param = dws;
7063c0d9 FT	183
a5c2db96 AS	184	return txdesc;
	185	}
	186
30c8eb52 AS	187	/*
	188	* dws->dma_chan_busy is set before the dma transfer starts, callback for rx
	189	* channel will clear a corresponding bit.
	190	*/
	191	static void dw_spi_dma_rx_done(void *arg)
	192	{
	193	struct dw_spi *dws = arg;
	194
854d2f24 AS	195	clear_bit(RX_BUSY, &dws->dma_chan_busy);
854d2f24 AS	196	if (test_bit(TX_BUSY, &dws->dma_chan_busy))
30c8eb52	197	return;
c22c62db	198	spi_finalize_current_transfer(dws->master);
30c8eb52 AS	199	}
30c8eb52 AS	200
f89a6d8f AS	201	static struct dma_async_tx_descriptor dw_spi_dma_prepare_rx(struct dw_spi dws,
f89a6d8f AS	202	struct spi_transfer *xfer)
a5c2db96 AS	203	{
	204	struct dma_slave_config rxconf;
	205	struct dma_async_tx_descriptor *rxdesc;
	206
f89a6d8f	207	if (!xfer->rx_buf)
30c8eb52 AS	208	return NULL;
30c8eb52 AS	209
a485df4b	210	rxconf.direction = DMA_DEV_TO_MEM;
7063c0d9 FT	211	rxconf.src_addr = dws->dma_addr;
	212	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	213	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
e31abce7	214	rxconf.src_addr_width = convert_dma_width(dws->dma_width);
258aea76	215	rxconf.device_fc = false;
7063c0d9	216
2a285299	217	dmaengine_slave_config(dws->rxchan, &rxconf);
7063c0d9	218
2a285299	219	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
f89a6d8f AS	220	xfer->rx_sg.sgl,
f89a6d8f AS	221	xfer->rx_sg.nents,
a485df4b	222	DMA_DEV_TO_MEM,
f7477c2b	223	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
c9dafb27 AS	224	if (!rxdesc)
	225	return NULL;
	226
30c8eb52	227	rxdesc->callback = dw_spi_dma_rx_done;
7063c0d9 FT	228	rxdesc->callback_param = dws;
7063c0d9 FT	229
a5c2db96 AS	230	return rxdesc;
	231	}
	232
f89a6d8f	233	static int mid_spi_dma_setup(struct dw_spi dws, struct spi_transfer xfer)
a5c2db96 AS	234	{
	235	u16 dma_ctrl = 0;
	236
a5c2db96 AS	237	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
	238	dw_writew(dws, DW_SPI_DMATDLR, 0x10);
	239
f89a6d8f	240	if (xfer->tx_buf)
a5c2db96	241	dma_ctrl \|= SPI_DMA_TDMAE;
f89a6d8f	242	if (xfer->rx_buf)
a5c2db96 AS	243	dma_ctrl \|= SPI_DMA_RDMAE;
	244	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
	245
f051fc8f AS	246	/* Set the interrupt mask */
	247	spi_umask_intr(dws, SPI_INT_TXOI \| SPI_INT_RXUI \| SPI_INT_RXOI);
	248
	249	dws->transfer_handler = dma_transfer;
	250
9f14538e	251	return 0;
a5c2db96 AS	252	}
a5c2db96 AS	253
f89a6d8f	254	static int mid_spi_dma_transfer(struct dw_spi dws, struct spi_transfer xfer)
a5c2db96 AS	255	{
	256	struct dma_async_tx_descriptor txdesc, rxdesc;
	257
9f14538e	258	/* Prepare the TX dma transfer */
f89a6d8f	259	txdesc = dw_spi_dma_prepare_tx(dws, xfer);
a5c2db96	260
9f14538e	261	/* Prepare the RX dma transfer */
f89a6d8f	262	rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
a5c2db96	263
7063c0d9	264	/* rx must be started before tx due to spi instinct */
30c8eb52 AS	265	if (rxdesc) {
	266	set_bit(RX_BUSY, &dws->dma_chan_busy);
	267	dmaengine_submit(rxdesc);
	268	dma_async_issue_pending(dws->rxchan);
	269	}
	270
	271	if (txdesc) {
	272	set_bit(TX_BUSY, &dws->dma_chan_busy);
	273	dmaengine_submit(txdesc);
	274	dma_async_issue_pending(dws->txchan);
	275	}
f7477c2b	276
7063c0d9 FT	277	return 0;
	278	}
	279
4d5ac1ed AS	280	static void mid_spi_dma_stop(struct dw_spi *dws)
	281	{
	282	if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
	283	dmaengine_terminate_all(dws->txchan);
	284	clear_bit(TX_BUSY, &dws->dma_chan_busy);
	285	}
	286	if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
	287	dmaengine_terminate_all(dws->rxchan);
	288	clear_bit(RX_BUSY, &dws->dma_chan_busy);
	289	}
	290	}
	291
7063c0d9 FT	292	static struct dw_spi_dma_ops mid_dma_ops = {
	293	.dma_init = mid_spi_dma_init,
	294	.dma_exit = mid_spi_dma_exit,
9f14538e	295	.dma_setup = mid_spi_dma_setup,
f89a6d8f	296	.can_dma = mid_spi_can_dma,
7063c0d9	297	.dma_transfer = mid_spi_dma_transfer,
4d5ac1ed	298	.dma_stop = mid_spi_dma_stop,
7063c0d9 FT	299	};
	300	#endif
	301
ea092455	302	/* Some specific info for SPI0 controller on Intel MID */
7063c0d9	303
d9c14743	304	/* HW info for MRST Clk Control Unit, 32b reg per controller */
7063c0d9	305	#define MRST_SPI_CLK_BASE 100000000 /* 100m */
d9c14743	306	#define MRST_CLK_SPI_REG 0xff11d86c
7063c0d9 FT	307	#define CLK_SPI_BDIV_OFFSET 0
	308	#define CLK_SPI_BDIV_MASK 0x00000007
	309	#define CLK_SPI_CDIV_OFFSET 9
	310	#define CLK_SPI_CDIV_MASK 0x00000e00
	311	#define CLK_SPI_DISABLE_OFFSET 8
	312
	313	int dw_spi_mid_init(struct dw_spi *dws)
	314	{
7eb187b3 HS	315	void __iomem *clk_reg;
7eb187b3 HS	316	u32 clk_cdiv;
7063c0d9	317
d9c14743	318	clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
7063c0d9 FT	319	if (!clk_reg)
	320	return -ENOMEM;
	321
d9c14743 AS	322	/* Get SPI controller operating freq info */
	323	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
	324	clk_cdiv &= CLK_SPI_CDIV_MASK;
	325	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
7063c0d9	326	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
d9c14743	327
7063c0d9 FT	328	iounmap(clk_reg);
7063c0d9 FT	329
7063c0d9 FT	330	#ifdef CONFIG_SPI_DW_MID_DMA
	331	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	332	if (!dws->dma_priv)
	333	return -ENOMEM;
	334	dws->dma_ops = &mid_dma_ops;
	335	#endif
	336	return 0;
	337	}