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spi: dw: drop unused struct dw_spi field
[deliverable/linux.git] / drivers / spi / spi-dw.c
CommitLineData
e24c7452 1/*
ca632f55 2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
e24c7452
FT		 3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/interrupt.h>
d7614de4 22#include <linux/module.h>
e24c7452
FT		 23#include <linux/highmem.h>
24#include <linux/delay.h>
5a0e3ad6 25#include <linux/slab.h>
e24c7452
FT		 26#include <linux/spi/spi.h>
27
ca632f55 28#include "spi-dw.h"
568a60ed 29
e24c7452
FT		 30#ifdef CONFIG_DEBUG_FS
31#include <linux/debugfs.h>
32#endif
33
34#define START_STATE ((void *)0)
35#define RUNNING_STATE ((void *)1)
36#define DONE_STATE ((void *)2)
37#define ERROR_STATE ((void *)-1)
38
39#define QUEUE_RUNNING 0
40#define QUEUE_STOPPED 1
41
42#define MRST_SPI_DEASSERT 0
43#define MRST_SPI_ASSERT 1
44
45/* Slave spi_dev related */
46struct chip_data {
47 u16 cr0;
48 u8 cs; /* chip select pin */
49 u8 n_bytes; /* current is a 1/2/4 byte op */
50 u8 tmode; /* TR/TO/RO/EEPROM */
51 u8 type; /* SPI/SSP/MicroWire */
52
53 u8 poll_mode; /* 1 means use poll mode */
54
55 u32 dma_width;
56 u32 rx_threshold;
57 u32 tx_threshold;
58 u8 enable_dma;
59 u8 bits_per_word;
60 u16 clk_div; /* baud rate divider */
61 u32 speed_hz; /* baud rate */
e24c7452
FT		 62 void (*cs_control)(u32 command);
63};
64
65#ifdef CONFIG_DEBUG_FS
e24c7452
FT		 66#define SPI_REGS_BUFSIZE 1024
67static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
68 size_t count, loff_t *ppos)
69{
70 struct dw_spi *dws;
71 char *buf;
72 u32 len = 0;
73 ssize_t ret;
74
75 dws = file->private_data;
76
77 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
78 if (!buf)
79 return 0;
80
81 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
82 "MRST SPI0 registers:\n");
83 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
84 "=================================\n");
85 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 86 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
e24c7452 87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 88 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
e24c7452 89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 90 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
e24c7452 91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 92 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
e24c7452 93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 94 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
e24c7452 95 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 96 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
e24c7452 97 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 98 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
e24c7452 99 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 100 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
e24c7452 101 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 102 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
e24c7452 103 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 104 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
e24c7452 105 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 106 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
e24c7452 107 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 108 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
e24c7452 109 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 110 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
e24c7452 111 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 112 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
e24c7452 113 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
7eb187b3 114 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
e24c7452
FT		 115 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
116 "=================================\n");
117
118 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
119 kfree(buf);
120 return ret;
121}
122
123static const struct file_operations mrst_spi_regs_ops = {
124 .owner = THIS_MODULE,
234e3405 125 .open = simple_open,
e24c7452 126 .read = spi_show_regs,
6038f373 127 .llseek = default_llseek,
e24c7452
FT		 128};
129
130static int mrst_spi_debugfs_init(struct dw_spi *dws)
131{
132 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
133 if (!dws->debugfs)
134 return -ENOMEM;
135
136 debugfs_create_file("registers", S_IFREG | S_IRUGO,
137 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
138 return 0;
139}
140
141static void mrst_spi_debugfs_remove(struct dw_spi *dws)
142{
143 if (dws->debugfs)
144 debugfs_remove_recursive(dws->debugfs);
145}
146
147#else
148static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
149{
20a588fc 150 return 0;
e24c7452
FT		 151}
152
153static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
154{
155}
156#endif /* CONFIG_DEBUG_FS */
157
2ff271bf
AD		 158/* Return the max entries we can fill into tx fifo */
159static inline u32 tx_max(struct dw_spi *dws)
160{
161 u32 tx_left, tx_room, rxtx_gap;
162
163 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
7eb187b3 164 tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
2ff271bf
AD		 165
166 /*
167 * Another concern is about the tx/rx mismatch, we
168 * though to use (dws->fifo_len - rxflr - txflr) as
169 * one maximum value for tx, but it doesn't cover the
170 * data which is out of tx/rx fifo and inside the
171 * shift registers. So a control from sw point of
172 * view is taken.
173 */
174 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
175 / dws->n_bytes;
176
177 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
178}
179
180/* Return the max entries we should read out of rx fifo */
181static inline u32 rx_max(struct dw_spi *dws)
182{
183 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
184
7eb187b3 185 return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
2ff271bf
AD		 186}
187
3b8a4dd3 188static void dw_writer(struct dw_spi *dws)
e24c7452 189{
2ff271bf 190 u32 max = tx_max(dws);
de6efe0a 191 u16 txw = 0;
e24c7452 192
2ff271bf
AD		 193 while (max--) {
194 /* Set the tx word if the transfer's original "tx" is not null */
195 if (dws->tx_end - dws->len) {
196 if (dws->n_bytes == 1)
197 txw = *(u8 *)(dws->tx);
198 else
199 txw = *(u16 *)(dws->tx);
200 }
7eb187b3 201 dw_writew(dws, DW_SPI_DR, txw);
2ff271bf 202 dws->tx += dws->n_bytes;
e24c7452 203 }
e24c7452
FT		 204}
205
3b8a4dd3 206static void dw_reader(struct dw_spi *dws)
e24c7452 207{
2ff271bf 208 u32 max = rx_max(dws);
de6efe0a 209 u16 rxw;
e24c7452 210
2ff271bf 211 while (max--) {
7eb187b3 212 rxw = dw_readw(dws, DW_SPI_DR);
de6efe0a
FT		 213 /* Care rx only if the transfer's original "rx" is not null */
214 if (dws->rx_end - dws->len) {
215 if (dws->n_bytes == 1)
216 *(u8 *)(dws->rx) = rxw;
217 else
218 *(u16 *)(dws->rx) = rxw;
219 }
220 dws->rx += dws->n_bytes;
e24c7452 221 }
e24c7452
FT		 222}
223
224static void *next_transfer(struct dw_spi *dws)
225{
226 struct spi_message *msg = dws->cur_msg;
227 struct spi_transfer *trans = dws->cur_transfer;
228
229 /* Move to next transfer */
230 if (trans->transfer_list.next != &msg->transfers) {
231 dws->cur_transfer =
232 list_entry(trans->transfer_list.next,
233 struct spi_transfer,
234 transfer_list);
235 return RUNNING_STATE;
236 } else
237 return DONE_STATE;
238}
239
240/*
241 * Note: first step is the protocol driver prepares
242 * a dma-capable memory, and this func just need translate
243 * the virt addr to physical
244 */
245static int map_dma_buffers(struct dw_spi *dws)
246{
7063c0d9
FT		 247 if (!dws->cur_msg->is_dma_mapped
248 || !dws->dma_inited
249 || !dws->cur_chip->enable_dma
250 || !dws->dma_ops)
e24c7452
FT		 251 return 0;
252
253 if (dws->cur_transfer->tx_dma)
254 dws->tx_dma = dws->cur_transfer->tx_dma;
255
256 if (dws->cur_transfer->rx_dma)
257 dws->rx_dma = dws->cur_transfer->rx_dma;
258
259 return 1;
260}
261
262/* Caller already set message->status; dma and pio irqs are blocked */
263static void giveback(struct dw_spi *dws)
264{
265 struct spi_transfer *last_transfer;
266 unsigned long flags;
267 struct spi_message *msg;
268
269 spin_lock_irqsave(&dws->lock, flags);
270 msg = dws->cur_msg;
271 dws->cur_msg = NULL;
272 dws->cur_transfer = NULL;
273 dws->prev_chip = dws->cur_chip;
274 dws->cur_chip = NULL;
275 dws->dma_mapped = 0;
276 queue_work(dws->workqueue, &dws->pump_messages);
277 spin_unlock_irqrestore(&dws->lock, flags);
278
279 last_transfer = list_entry(msg->transfers.prev,
280 struct spi_transfer,
281 transfer_list);
282
e3e55ff5 283 if (!last_transfer->cs_change && dws->cs_control)
e24c7452
FT		 284 dws->cs_control(MRST_SPI_DEASSERT);
285
286 msg->state = NULL;
287 if (msg->complete)
288 msg->complete(msg->context);
289}
290
291static void int_error_stop(struct dw_spi *dws, const char *msg)
292{
8a33a373 293 /* Stop the hw */
e24c7452
FT		 294 spi_enable_chip(dws, 0);
295
296 dev_err(&dws->master->dev, "%s\n", msg);
297 dws->cur_msg->state = ERROR_STATE;
298 tasklet_schedule(&dws->pump_transfers);
299}
300
7063c0d9 301void dw_spi_xfer_done(struct dw_spi *dws)
e24c7452 302{
25985edc 303 /* Update total byte transferred return count actual bytes read */
e24c7452
FT		 304 dws->cur_msg->actual_length += dws->len;
305
306 /* Move to next transfer */
307 dws->cur_msg->state = next_transfer(dws);
308
309 /* Handle end of message */
310 if (dws->cur_msg->state == DONE_STATE) {
311 dws->cur_msg->status = 0;
312 giveback(dws);
313 } else
314 tasklet_schedule(&dws->pump_transfers);
315}
7063c0d9 316EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
e24c7452
FT		 317
318static irqreturn_t interrupt_transfer(struct dw_spi *dws)
319{
7eb187b3 320 u16 irq_status = dw_readw(dws, DW_SPI_ISR);
e24c7452 321
e24c7452
FT		 322 /* Error handling */
323 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
7eb187b3
HS		 324 dw_readw(dws, DW_SPI_TXOICR);
325 dw_readw(dws, DW_SPI_RXOICR);
326 dw_readw(dws, DW_SPI_RXUICR);
3b8a4dd3 327 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
e24c7452
FT		 328 return IRQ_HANDLED;
329 }
330
3b8a4dd3
AD		 331 dw_reader(dws);
332 if (dws->rx_end == dws->rx) {
333 spi_mask_intr(dws, SPI_INT_TXEI);
334 dw_spi_xfer_done(dws);
335 return IRQ_HANDLED;
336 }
552e4509
FT		 337 if (irq_status & SPI_INT_TXEI) {
338 spi_mask_intr(dws, SPI_INT_TXEI);
3b8a4dd3
AD		 339 dw_writer(dws);
340 /* Enable TX irq always, it will be disabled when RX finished */
341 spi_umask_intr(dws, SPI_INT_TXEI);
e24c7452
FT		 342 }
343
e24c7452
FT		 344 return IRQ_HANDLED;
345}
346
347static irqreturn_t dw_spi_irq(int irq, void *dev_id)
348{
349 struct dw_spi *dws = dev_id;
7eb187b3 350 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
cbcc062a 351
cbcc062a
YW		 352 if (!irq_status)
353 return IRQ_NONE;
e24c7452
FT		 354
355 if (!dws->cur_msg) {
356 spi_mask_intr(dws, SPI_INT_TXEI);
e24c7452
FT		 357 return IRQ_HANDLED;
358 }
359
360 return dws->transfer_handler(dws);
361}
362
363/* Must be called inside pump_transfers() */
364static void poll_transfer(struct dw_spi *dws)
365{
2ff271bf
AD		 366 do {
367 dw_writer(dws);
de6efe0a 368 dw_reader(dws);
2ff271bf
AD		 369 cpu_relax();
370 } while (dws->rx_end > dws->rx);
e24c7452 371
7063c0d9 372 dw_spi_xfer_done(dws);
e24c7452
FT		 373}
374
375static void pump_transfers(unsigned long data)
376{
377 struct dw_spi *dws = (struct dw_spi *)data;
378 struct spi_message *message = NULL;
379 struct spi_transfer *transfer = NULL;
380 struct spi_transfer *previous = NULL;
381 struct spi_device *spi = NULL;
382 struct chip_data *chip = NULL;
383 u8 bits = 0;
384 u8 imask = 0;
385 u8 cs_change = 0;
552e4509 386 u16 txint_level = 0;
e24c7452
FT		 387 u16 clk_div = 0;
388 u32 speed = 0;
389 u32 cr0 = 0;
390
391 /* Get current state information */
392 message = dws->cur_msg;
393 transfer = dws->cur_transfer;
394 chip = dws->cur_chip;
395 spi = message->spi;
396
552e4509
FT		 397 if (unlikely(!chip->clk_div))
398 chip->clk_div = dws->max_freq / chip->speed_hz;
399
e24c7452
FT		 400 if (message->state == ERROR_STATE) {
401 message->status = -EIO;
402 goto early_exit;
403 }
404
405 /* Handle end of message */
406 if (message->state == DONE_STATE) {
407 message->status = 0;
408 goto early_exit;
409 }
410
411 /* Delay if requested at end of transfer*/
412 if (message->state == RUNNING_STATE) {
413 previous = list_entry(transfer->transfer_list.prev,
414 struct spi_transfer,
415 transfer_list);
416 if (previous->delay_usecs)
417 udelay(previous->delay_usecs);
418 }
419
420 dws->n_bytes = chip->n_bytes;
421 dws->dma_width = chip->dma_width;
422 dws->cs_control = chip->cs_control;
423
424 dws->rx_dma = transfer->rx_dma;
425 dws->tx_dma = transfer->tx_dma;
426 dws->tx = (void *)transfer->tx_buf;
427 dws->tx_end = dws->tx + transfer->len;
428 dws->rx = transfer->rx_buf;
429 dws->rx_end = dws->rx + transfer->len;
e24c7452
FT		 430 dws->len = dws->cur_transfer->len;
431 if (chip != dws->prev_chip)
432 cs_change = 1;
433
434 cr0 = chip->cr0;
435
436 /* Handle per transfer options for bpw and speed */
437 if (transfer->speed_hz) {
438 speed = chip->speed_hz;
439
440 if (transfer->speed_hz != speed) {
441 speed = transfer->speed_hz;
442 if (speed > dws->max_freq) {
443 printk(KERN_ERR "MRST SPI0: unsupported"
444 "freq: %dHz\n", speed);
445 message->status = -EIO;
446 goto early_exit;
447 }
448
449 /* clk_div doesn't support odd number */
450 clk_div = dws->max_freq / speed;
552e4509 451 clk_div = (clk_div + 1) & 0xfffe;
e24c7452
FT		 452
453 chip->speed_hz = speed;
454 chip->clk_div = clk_div;
455 }
456 }
457 if (transfer->bits_per_word) {
458 bits = transfer->bits_per_word;
24778be2 459 dws->n_bytes = dws->dma_width = bits >> 3;
e24c7452
FT		 460 cr0 = (bits - 1)
461 | (chip->type << SPI_FRF_OFFSET)
462 | (spi->mode << SPI_MODE_OFFSET)
463 | (chip->tmode << SPI_TMOD_OFFSET);
464 }
465 message->state = RUNNING_STATE;
466
052dc7c4
GS		 467 /*
468 * Adjust transfer mode if necessary. Requires platform dependent
469 * chipselect mechanism.
470 */
471 if (dws->cs_control) {
472 if (dws->rx && dws->tx)
e3e55ff5 473 chip->tmode = SPI_TMOD_TR;
052dc7c4 474 else if (dws->rx)
e3e55ff5 475 chip->tmode = SPI_TMOD_RO;
052dc7c4 476 else
e3e55ff5 477 chip->tmode = SPI_TMOD_TO;
052dc7c4 478
e3e55ff5 479 cr0 &= ~SPI_TMOD_MASK;
052dc7c4
GS		 480 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
481 }
482
e24c7452
FT		 483 /* Check if current transfer is a DMA transaction */
484 dws->dma_mapped = map_dma_buffers(dws);
485
552e4509
FT		 486 /*
487 * Interrupt mode
488 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
489 */
e24c7452 490 if (!dws->dma_mapped && !chip->poll_mode) {
552e4509
FT		 491 int templen = dws->len / dws->n_bytes;
492 txint_level = dws->fifo_len / 2;
493 txint_level = (templen > txint_level) ? txint_level : templen;
494
3b8a4dd3 495 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
e24c7452
FT		 496 dws->transfer_handler = interrupt_transfer;
497 }
498
499 /*
500 * Reprogram registers only if
501 * 1. chip select changes
502 * 2. clk_div is changed
503 * 3. control value changes
504 */
7eb187b3 505 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
e24c7452
FT		 506 spi_enable_chip(dws, 0);
507
7eb187b3
HS		 508 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
509 dw_writew(dws, DW_SPI_CTRL0, cr0);
e24c7452 510
552e4509
FT		 511 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
512 spi_chip_sel(dws, spi->chip_select);
513
2f263d9d 514 /* Set the interrupt mask, for poll mode just disable all int */
e24c7452 515 spi_mask_intr(dws, 0xff);
552e4509 516 if (imask)
e24c7452 517 spi_umask_intr(dws, imask);
552e4509 518 if (txint_level)
7eb187b3 519 dw_writew(dws, DW_SPI_TXFLTR, txint_level);
e24c7452 520
e24c7452 521 spi_enable_chip(dws, 1);
e24c7452
FT		 522 if (cs_change)
523 dws->prev_chip = chip;
524 }
525
526 if (dws->dma_mapped)
7063c0d9 527 dws->dma_ops->dma_transfer(dws, cs_change);
e24c7452
FT		 528
529 if (chip->poll_mode)
530 poll_transfer(dws);
531
532 return;
533
534early_exit:
535 giveback(dws);
536 return;
537}
538
539static void pump_messages(struct work_struct *work)
540{
541 struct dw_spi *dws =
542 container_of(work, struct dw_spi, pump_messages);
543 unsigned long flags;
544
545 /* Lock queue and check for queue work */
546 spin_lock_irqsave(&dws->lock, flags);
547 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
548 dws->busy = 0;
549 spin_unlock_irqrestore(&dws->lock, flags);
550 return;
551 }
552
553 /* Make sure we are not already running a message */
554 if (dws->cur_msg) {
555 spin_unlock_irqrestore(&dws->lock, flags);
556 return;
557 }
558
559 /* Extract head of queue */
560 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
561 list_del_init(&dws->cur_msg->queue);
562
563 /* Initial message state*/
564 dws->cur_msg->state = START_STATE;
565 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
566 struct spi_transfer,
567 transfer_list);
568 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
569
570 /* Mark as busy and launch transfers */
571 tasklet_schedule(&dws->pump_transfers);
572
573 dws->busy = 1;
574 spin_unlock_irqrestore(&dws->lock, flags);
575}
576
577/* spi_device use this to queue in their spi_msg */
578static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
579{
580 struct dw_spi *dws = spi_master_get_devdata(spi->master);
581 unsigned long flags;
582
583 spin_lock_irqsave(&dws->lock, flags);
584
585 if (dws->run == QUEUE_STOPPED) {
586 spin_unlock_irqrestore(&dws->lock, flags);
587 return -ESHUTDOWN;
588 }
589
590 msg->actual_length = 0;
591 msg->status = -EINPROGRESS;
592 msg->state = START_STATE;
593
594 list_add_tail(&msg->queue, &dws->queue);
595
596 if (dws->run == QUEUE_RUNNING && !dws->busy) {
597
598 if (dws->cur_transfer || dws->cur_msg)
599 queue_work(dws->workqueue,
600 &dws->pump_messages);
601 else {
602 /* If no other data transaction in air, just go */
603 spin_unlock_irqrestore(&dws->lock, flags);
604 pump_messages(&dws->pump_messages);
605 return 0;
606 }
607 }
608
609 spin_unlock_irqrestore(&dws->lock, flags);
610 return 0;
611}
612
613/* This may be called twice for each spi dev */
614static int dw_spi_setup(struct spi_device *spi)
615{
616 struct dw_spi_chip *chip_info = NULL;
617 struct chip_data *chip;
618
e24c7452
FT		 619 /* Only alloc on first setup */
620 chip = spi_get_ctldata(spi);
621 if (!chip) {
622 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
623 if (!chip)
624 return -ENOMEM;
e24c7452
FT		 625 }
626
627 /*
628 * Protocol drivers may change the chip settings, so...
629 * if chip_info exists, use it
630 */
631 chip_info = spi->controller_data;
632
633 /* chip_info doesn't always exist */
634 if (chip_info) {
635 if (chip_info->cs_control)
636 chip->cs_control = chip_info->cs_control;
637
638 chip->poll_mode = chip_info->poll_mode;
639 chip->type = chip_info->type;
640
641 chip->rx_threshold = 0;
642 chip->tx_threshold = 0;
643
644 chip->enable_dma = chip_info->enable_dma;
645 }
646
24778be2 647 if (spi->bits_per_word == 8) {
e24c7452
FT		 648 chip->n_bytes = 1;
649 chip->dma_width = 1;
24778be2 650 } else if (spi->bits_per_word == 16) {
e24c7452
FT		 651 chip->n_bytes = 2;
652 chip->dma_width = 2;
e24c7452
FT		 653 }
654 chip->bits_per_word = spi->bits_per_word;
655
552e4509
FT		 656 if (!spi->max_speed_hz) {
657 dev_err(&spi->dev, "No max speed HZ parameter\n");
658 return -EINVAL;
659 }
e24c7452 660 chip->speed_hz = spi->max_speed_hz;
e24c7452
FT		 661
662 chip->tmode = 0; /* Tx & Rx */
663 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
664 chip->cr0 = (chip->bits_per_word - 1)
665 | (chip->type << SPI_FRF_OFFSET)
666 | (spi->mode << SPI_MODE_OFFSET)
667 | (chip->tmode << SPI_TMOD_OFFSET);
668
669 spi_set_ctldata(spi, chip);
670 return 0;
671}
672
673static void dw_spi_cleanup(struct spi_device *spi)
674{
675 struct chip_data *chip = spi_get_ctldata(spi);
676 kfree(chip);
677}
678
fd4a319b 679static int init_queue(struct dw_spi *dws)
e24c7452
FT		 680{
681 INIT_LIST_HEAD(&dws->queue);
682 spin_lock_init(&dws->lock);
683
684 dws->run = QUEUE_STOPPED;
685 dws->busy = 0;
686
687 tasklet_init(&dws->pump_transfers,
688 pump_transfers, (unsigned long)dws);
689
690 INIT_WORK(&dws->pump_messages, pump_messages);
691 dws->workqueue = create_singlethread_workqueue(
692 dev_name(dws->master->dev.parent));
693 if (dws->workqueue == NULL)
694 return -EBUSY;
695
696 return 0;
697}
698
699static int start_queue(struct dw_spi *dws)
700{
701 unsigned long flags;
702
703 spin_lock_irqsave(&dws->lock, flags);
704
705 if (dws->run == QUEUE_RUNNING || dws->busy) {
706 spin_unlock_irqrestore(&dws->lock, flags);
707 return -EBUSY;
708 }
709
710 dws->run = QUEUE_RUNNING;
711 dws->cur_msg = NULL;
712 dws->cur_transfer = NULL;
713 dws->cur_chip = NULL;
714 dws->prev_chip = NULL;
715 spin_unlock_irqrestore(&dws->lock, flags);
716
717 queue_work(dws->workqueue, &dws->pump_messages);
718
719 return 0;
720}
721
722static int stop_queue(struct dw_spi *dws)
723{
724 unsigned long flags;
725 unsigned limit = 50;
726 int status = 0;
727
728 spin_lock_irqsave(&dws->lock, flags);
729 dws->run = QUEUE_STOPPED;
850a28ec 730 while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
e24c7452
FT		 731 spin_unlock_irqrestore(&dws->lock, flags);
732 msleep(10);
733 spin_lock_irqsave(&dws->lock, flags);
734 }
735
736 if (!list_empty(&dws->queue) || dws->busy)
737 status = -EBUSY;
738 spin_unlock_irqrestore(&dws->lock, flags);
739
740 return status;
741}
742
743static int destroy_queue(struct dw_spi *dws)
744{
745 int status;
746
747 status = stop_queue(dws);
748 if (status != 0)
749 return status;
750 destroy_workqueue(dws->workqueue);
751 return 0;
752}
753
754/* Restart the controller, disable all interrupts, clean rx fifo */
755static void spi_hw_init(struct dw_spi *dws)
756{
757 spi_enable_chip(dws, 0);
758 spi_mask_intr(dws, 0xff);
759 spi_enable_chip(dws, 1);
c587b6fa
FT		 760
761 /*
762 * Try to detect the FIFO depth if not set by interface driver,
763 * the depth could be from 2 to 256 from HW spec
764 */
765 if (!dws->fifo_len) {
766 u32 fifo;
767 for (fifo = 2; fifo <= 257; fifo++) {
7eb187b3
HS		 768 dw_writew(dws, DW_SPI_TXFLTR, fifo);
769 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
c587b6fa
FT		 770 break;
771 }
772
773 dws->fifo_len = (fifo == 257) ? 0 : fifo;
7eb187b3 774 dw_writew(dws, DW_SPI_TXFLTR, 0);
c587b6fa 775 }
e24c7452
FT		 776}
777
fd4a319b 778int dw_spi_add_host(struct dw_spi *dws)
e24c7452
FT		 779{
780 struct spi_master *master;
781 int ret;
782
783 BUG_ON(dws == NULL);
784
785 master = spi_alloc_master(dws->parent_dev, 0);
786 if (!master) {
787 ret = -ENOMEM;
788 goto exit;
789 }
790
791 dws->master = master;
792 dws->type = SSI_MOTO_SPI;
793 dws->prev_chip = NULL;
794 dws->dma_inited = 0;
795 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
40bfff85
LS		 796 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
797 dws->bus_num);
e24c7452 798
cbcc062a 799 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
40bfff85 800 dws->name, dws);
e24c7452
FT		 801 if (ret < 0) {
802 dev_err(&master->dev, "can not get IRQ\n");
803 goto err_free_master;
804 }
805
806 master->mode_bits = SPI_CPOL | SPI_CPHA;
24778be2 807 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
e24c7452
FT		 808 master->bus_num = dws->bus_num;
809 master->num_chipselect = dws->num_cs;
810 master->cleanup = dw_spi_cleanup;
811 master->setup = dw_spi_setup;
812 master->transfer = dw_spi_transfer;
813
e24c7452
FT		 814 /* Basic HW init */
815 spi_hw_init(dws);
816
7063c0d9
FT		 817 if (dws->dma_ops && dws->dma_ops->dma_init) {
818 ret = dws->dma_ops->dma_init(dws);
819 if (ret) {
820 dev_warn(&master->dev, "DMA init failed\n");
821 dws->dma_inited = 0;
822 }
823 }
824
e24c7452
FT		 825 /* Initial and start queue */
826 ret = init_queue(dws);
827 if (ret) {
828 dev_err(&master->dev, "problem initializing queue\n");
829 goto err_diable_hw;
830 }
831 ret = start_queue(dws);
832 if (ret) {
833 dev_err(&master->dev, "problem starting queue\n");
834 goto err_diable_hw;
835 }
836
837 spi_master_set_devdata(master, dws);
838 ret = spi_register_master(master);
839 if (ret) {
840 dev_err(&master->dev, "problem registering spi master\n");
841 goto err_queue_alloc;
842 }
843
844 mrst_spi_debugfs_init(dws);
845 return 0;
846
847err_queue_alloc:
848 destroy_queue(dws);
7063c0d9
FT		 849 if (dws->dma_ops && dws->dma_ops->dma_exit)
850 dws->dma_ops->dma_exit(dws);
e24c7452
FT		 851err_diable_hw:
852 spi_enable_chip(dws, 0);
853 free_irq(dws->irq, dws);
854err_free_master:
855 spi_master_put(master);
856exit:
857 return ret;
858}
79290a2a 859EXPORT_SYMBOL_GPL(dw_spi_add_host);
e24c7452 860
fd4a319b 861void dw_spi_remove_host(struct dw_spi *dws)
e24c7452
FT		 862{
863 int status = 0;
864
865 if (!dws)
866 return;
867 mrst_spi_debugfs_remove(dws);
868
869 /* Remove the queue */
870 status = destroy_queue(dws);
871 if (status != 0)
f6bd03a7
JN		 872 dev_err(&dws->master->dev,
873 "dw_spi_remove: workqueue will not complete, message memory not freed\n");
e24c7452 874
7063c0d9
FT		 875 if (dws->dma_ops && dws->dma_ops->dma_exit)
876 dws->dma_ops->dma_exit(dws);
e24c7452
FT		 877 spi_enable_chip(dws, 0);
878 /* Disable clk */
879 spi_set_clk(dws, 0);
880 free_irq(dws->irq, dws);
881
882 /* Disconnect from the SPI framework */
883 spi_unregister_master(dws->master);
884}
79290a2a 885EXPORT_SYMBOL_GPL(dw_spi_remove_host);
e24c7452
FT		 886
887int dw_spi_suspend_host(struct dw_spi *dws)
888{
889 int ret = 0;
890
891 ret = stop_queue(dws);
892 if (ret)
893 return ret;
894 spi_enable_chip(dws, 0);
895 spi_set_clk(dws, 0);
896 return ret;
897}
79290a2a 898EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
e24c7452
FT		 899
900int dw_spi_resume_host(struct dw_spi *dws)
901{
902 int ret;
903
904 spi_hw_init(dws);
905 ret = start_queue(dws);
906 if (ret)
907 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
908 return ret;
909}
79290a2a 910EXPORT_SYMBOL_GPL(dw_spi_resume_host);
e24c7452
FT		 911
912MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
913MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
914MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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