Commit | Line | Data |
---|---|---|
e24c7452 | 1 | /* |
ca632f55 | 2 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
e24c7452 FT |
3 | * |
4 | * Copyright (c) 2009, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
e24c7452 FT |
14 | */ |
15 | ||
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/interrupt.h> | |
d7614de4 | 18 | #include <linux/module.h> |
e24c7452 FT |
19 | #include <linux/highmem.h> |
20 | #include <linux/delay.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
e24c7452 | 22 | #include <linux/spi/spi.h> |
d9c73bb8 | 23 | #include <linux/gpio.h> |
e24c7452 | 24 | |
ca632f55 | 25 | #include "spi-dw.h" |
568a60ed | 26 | |
e24c7452 FT |
27 | #ifdef CONFIG_DEBUG_FS |
28 | #include <linux/debugfs.h> | |
29 | #endif | |
30 | ||
e24c7452 FT |
31 | /* Slave spi_dev related */ |
32 | struct chip_data { | |
e24c7452 FT |
33 | u8 cs; /* chip select pin */ |
34 | u8 n_bytes; /* current is a 1/2/4 byte op */ | |
35 | u8 tmode; /* TR/TO/RO/EEPROM */ | |
36 | u8 type; /* SPI/SSP/MicroWire */ | |
37 | ||
38 | u8 poll_mode; /* 1 means use poll mode */ | |
39 | ||
40 | u32 dma_width; | |
41 | u32 rx_threshold; | |
42 | u32 tx_threshold; | |
43 | u8 enable_dma; | |
44 | u8 bits_per_word; | |
45 | u16 clk_div; /* baud rate divider */ | |
46 | u32 speed_hz; /* baud rate */ | |
e24c7452 FT |
47 | void (*cs_control)(u32 command); |
48 | }; | |
49 | ||
50 | #ifdef CONFIG_DEBUG_FS | |
e24c7452 | 51 | #define SPI_REGS_BUFSIZE 1024 |
53288fe9 AS |
52 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
53 | size_t count, loff_t *ppos) | |
e24c7452 | 54 | { |
53288fe9 | 55 | struct dw_spi *dws = file->private_data; |
e24c7452 FT |
56 | char *buf; |
57 | u32 len = 0; | |
58 | ssize_t ret; | |
59 | ||
e24c7452 FT |
60 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
61 | if (!buf) | |
62 | return 0; | |
63 | ||
64 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
53288fe9 | 65 | "%s registers:\n", dev_name(&dws->master->dev)); |
e24c7452 FT |
66 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
67 | "=================================\n"); | |
68 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
7eb187b3 | 69 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
e24c7452 | 70 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 71 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
e24c7452 | 72 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 73 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
e24c7452 | 74 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 75 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
e24c7452 | 76 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 77 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
e24c7452 | 78 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 79 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
e24c7452 | 80 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 81 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
e24c7452 | 82 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 83 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
e24c7452 | 84 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 85 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
e24c7452 | 86 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 87 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
e24c7452 | 88 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 89 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
e24c7452 | 90 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 91 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
e24c7452 | 92 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 93 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
e24c7452 | 94 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 95 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
e24c7452 | 96 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 97 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
e24c7452 FT |
98 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
99 | "=================================\n"); | |
100 | ||
53288fe9 | 101 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
e24c7452 FT |
102 | kfree(buf); |
103 | return ret; | |
104 | } | |
105 | ||
53288fe9 | 106 | static const struct file_operations dw_spi_regs_ops = { |
e24c7452 | 107 | .owner = THIS_MODULE, |
234e3405 | 108 | .open = simple_open, |
53288fe9 | 109 | .read = dw_spi_show_regs, |
6038f373 | 110 | .llseek = default_llseek, |
e24c7452 FT |
111 | }; |
112 | ||
53288fe9 | 113 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 114 | { |
53288fe9 | 115 | dws->debugfs = debugfs_create_dir("dw_spi", NULL); |
e24c7452 FT |
116 | if (!dws->debugfs) |
117 | return -ENOMEM; | |
118 | ||
119 | debugfs_create_file("registers", S_IFREG | S_IRUGO, | |
53288fe9 | 120 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
e24c7452 FT |
121 | return 0; |
122 | } | |
123 | ||
53288fe9 | 124 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 | 125 | { |
fadcace7 | 126 | debugfs_remove_recursive(dws->debugfs); |
e24c7452 FT |
127 | } |
128 | ||
129 | #else | |
53288fe9 | 130 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 131 | { |
20a588fc | 132 | return 0; |
e24c7452 FT |
133 | } |
134 | ||
53288fe9 | 135 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 FT |
136 | { |
137 | } | |
138 | #endif /* CONFIG_DEBUG_FS */ | |
139 | ||
c22c62db AS |
140 | static void dw_spi_set_cs(struct spi_device *spi, bool enable) |
141 | { | |
142 | struct dw_spi *dws = spi_master_get_devdata(spi->master); | |
143 | struct chip_data *chip = spi_get_ctldata(spi); | |
144 | ||
145 | /* Chip select logic is inverted from spi_set_cs() */ | |
207cda93 | 146 | if (chip && chip->cs_control) |
c22c62db AS |
147 | chip->cs_control(!enable); |
148 | ||
149 | if (!enable) | |
150 | dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); | |
151 | } | |
152 | ||
2ff271bf AD |
153 | /* Return the max entries we can fill into tx fifo */ |
154 | static inline u32 tx_max(struct dw_spi *dws) | |
155 | { | |
156 | u32 tx_left, tx_room, rxtx_gap; | |
157 | ||
158 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; | |
dd114443 | 159 | tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); |
2ff271bf AD |
160 | |
161 | /* | |
162 | * Another concern is about the tx/rx mismatch, we | |
163 | * though to use (dws->fifo_len - rxflr - txflr) as | |
164 | * one maximum value for tx, but it doesn't cover the | |
165 | * data which is out of tx/rx fifo and inside the | |
166 | * shift registers. So a control from sw point of | |
167 | * view is taken. | |
168 | */ | |
169 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) | |
170 | / dws->n_bytes; | |
171 | ||
172 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); | |
173 | } | |
174 | ||
175 | /* Return the max entries we should read out of rx fifo */ | |
176 | static inline u32 rx_max(struct dw_spi *dws) | |
177 | { | |
178 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; | |
179 | ||
dd114443 | 180 | return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); |
2ff271bf AD |
181 | } |
182 | ||
3b8a4dd3 | 183 | static void dw_writer(struct dw_spi *dws) |
e24c7452 | 184 | { |
2ff271bf | 185 | u32 max = tx_max(dws); |
de6efe0a | 186 | u16 txw = 0; |
e24c7452 | 187 | |
2ff271bf AD |
188 | while (max--) { |
189 | /* Set the tx word if the transfer's original "tx" is not null */ | |
190 | if (dws->tx_end - dws->len) { | |
191 | if (dws->n_bytes == 1) | |
192 | txw = *(u8 *)(dws->tx); | |
193 | else | |
194 | txw = *(u16 *)(dws->tx); | |
195 | } | |
c4fe57f7 | 196 | dw_write_io_reg(dws, DW_SPI_DR, txw); |
2ff271bf | 197 | dws->tx += dws->n_bytes; |
e24c7452 | 198 | } |
e24c7452 FT |
199 | } |
200 | ||
3b8a4dd3 | 201 | static void dw_reader(struct dw_spi *dws) |
e24c7452 | 202 | { |
2ff271bf | 203 | u32 max = rx_max(dws); |
de6efe0a | 204 | u16 rxw; |
e24c7452 | 205 | |
2ff271bf | 206 | while (max--) { |
c4fe57f7 | 207 | rxw = dw_read_io_reg(dws, DW_SPI_DR); |
de6efe0a FT |
208 | /* Care rx only if the transfer's original "rx" is not null */ |
209 | if (dws->rx_end - dws->len) { | |
210 | if (dws->n_bytes == 1) | |
211 | *(u8 *)(dws->rx) = rxw; | |
212 | else | |
213 | *(u16 *)(dws->rx) = rxw; | |
214 | } | |
215 | dws->rx += dws->n_bytes; | |
e24c7452 | 216 | } |
e24c7452 FT |
217 | } |
218 | ||
e24c7452 FT |
219 | static void int_error_stop(struct dw_spi *dws, const char *msg) |
220 | { | |
45746e82 | 221 | spi_reset_chip(dws); |
e24c7452 FT |
222 | |
223 | dev_err(&dws->master->dev, "%s\n", msg); | |
c22c62db AS |
224 | dws->master->cur_msg->status = -EIO; |
225 | spi_finalize_current_transfer(dws->master); | |
e24c7452 FT |
226 | } |
227 | ||
e24c7452 FT |
228 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
229 | { | |
dd114443 | 230 | u16 irq_status = dw_readl(dws, DW_SPI_ISR); |
e24c7452 | 231 | |
e24c7452 FT |
232 | /* Error handling */ |
233 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | |
dd114443 | 234 | dw_readl(dws, DW_SPI_ICR); |
3b8a4dd3 | 235 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
e24c7452 FT |
236 | return IRQ_HANDLED; |
237 | } | |
238 | ||
3b8a4dd3 AD |
239 | dw_reader(dws); |
240 | if (dws->rx_end == dws->rx) { | |
241 | spi_mask_intr(dws, SPI_INT_TXEI); | |
c22c62db | 242 | spi_finalize_current_transfer(dws->master); |
3b8a4dd3 AD |
243 | return IRQ_HANDLED; |
244 | } | |
552e4509 FT |
245 | if (irq_status & SPI_INT_TXEI) { |
246 | spi_mask_intr(dws, SPI_INT_TXEI); | |
3b8a4dd3 AD |
247 | dw_writer(dws); |
248 | /* Enable TX irq always, it will be disabled when RX finished */ | |
249 | spi_umask_intr(dws, SPI_INT_TXEI); | |
e24c7452 FT |
250 | } |
251 | ||
e24c7452 FT |
252 | return IRQ_HANDLED; |
253 | } | |
254 | ||
255 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | |
256 | { | |
c22c62db AS |
257 | struct spi_master *master = dev_id; |
258 | struct dw_spi *dws = spi_master_get_devdata(master); | |
dd114443 | 259 | u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; |
cbcc062a | 260 | |
cbcc062a YW |
261 | if (!irq_status) |
262 | return IRQ_NONE; | |
e24c7452 | 263 | |
c22c62db | 264 | if (!master->cur_msg) { |
e24c7452 | 265 | spi_mask_intr(dws, SPI_INT_TXEI); |
e24c7452 FT |
266 | return IRQ_HANDLED; |
267 | } | |
268 | ||
269 | return dws->transfer_handler(dws); | |
270 | } | |
271 | ||
272 | /* Must be called inside pump_transfers() */ | |
c22c62db | 273 | static int poll_transfer(struct dw_spi *dws) |
e24c7452 | 274 | { |
2ff271bf AD |
275 | do { |
276 | dw_writer(dws); | |
de6efe0a | 277 | dw_reader(dws); |
2ff271bf AD |
278 | cpu_relax(); |
279 | } while (dws->rx_end > dws->rx); | |
e24c7452 | 280 | |
c22c62db | 281 | return 0; |
e24c7452 FT |
282 | } |
283 | ||
c22c62db AS |
284 | static int dw_spi_transfer_one(struct spi_master *master, |
285 | struct spi_device *spi, struct spi_transfer *transfer) | |
e24c7452 | 286 | { |
c22c62db AS |
287 | struct dw_spi *dws = spi_master_get_devdata(master); |
288 | struct chip_data *chip = spi_get_ctldata(spi); | |
e24c7452 | 289 | u8 imask = 0; |
ea11370f | 290 | u16 txlevel = 0; |
e24c7452 FT |
291 | u16 clk_div = 0; |
292 | u32 speed = 0; | |
4adb1f8f | 293 | u32 cr0; |
9f14538e | 294 | int ret; |
e24c7452 | 295 | |
f89a6d8f | 296 | dws->dma_mapped = 0; |
e24c7452 FT |
297 | dws->n_bytes = chip->n_bytes; |
298 | dws->dma_width = chip->dma_width; | |
e24c7452 | 299 | |
e24c7452 FT |
300 | dws->tx = (void *)transfer->tx_buf; |
301 | dws->tx_end = dws->tx + transfer->len; | |
302 | dws->rx = transfer->rx_buf; | |
303 | dws->rx_end = dws->rx + transfer->len; | |
c22c62db | 304 | dws->len = transfer->len; |
e24c7452 | 305 | |
0b2e8915 AS |
306 | spi_enable_chip(dws, 0); |
307 | ||
e24c7452 | 308 | /* Handle per transfer options for bpw and speed */ |
0ed36990 JN |
309 | speed = chip->speed_hz; |
310 | if ((transfer->speed_hz != speed) || !chip->clk_div) { | |
311 | speed = transfer->speed_hz; | |
e24c7452 | 312 | |
0ed36990 JN |
313 | /* clk_div doesn't support odd number */ |
314 | clk_div = (dws->max_freq / speed + 1) & 0xfffe; | |
e24c7452 | 315 | |
0ed36990 JN |
316 | chip->speed_hz = speed; |
317 | chip->clk_div = clk_div; | |
e24c7452 | 318 | |
0ed36990 | 319 | spi_set_clk(dws, chip->clk_div); |
e24c7452 | 320 | } |
0ed36990 JN |
321 | if (transfer->bits_per_word == 8) { |
322 | dws->n_bytes = 1; | |
323 | dws->dma_width = 1; | |
324 | } else if (transfer->bits_per_word == 16) { | |
325 | dws->n_bytes = 2; | |
326 | dws->dma_width = 2; | |
e24c7452 | 327 | } |
4adb1f8f | 328 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ |
0ed36990 JN |
329 | cr0 = (transfer->bits_per_word - 1) |
330 | | (chip->type << SPI_FRF_OFFSET) | |
331 | | (spi->mode << SPI_MODE_OFFSET) | |
332 | | (chip->tmode << SPI_TMOD_OFFSET); | |
e24c7452 | 333 | |
052dc7c4 GS |
334 | /* |
335 | * Adjust transfer mode if necessary. Requires platform dependent | |
336 | * chipselect mechanism. | |
337 | */ | |
c22c62db | 338 | if (chip->cs_control) { |
052dc7c4 | 339 | if (dws->rx && dws->tx) |
e3e55ff5 | 340 | chip->tmode = SPI_TMOD_TR; |
052dc7c4 | 341 | else if (dws->rx) |
e3e55ff5 | 342 | chip->tmode = SPI_TMOD_RO; |
052dc7c4 | 343 | else |
e3e55ff5 | 344 | chip->tmode = SPI_TMOD_TO; |
052dc7c4 | 345 | |
e3e55ff5 | 346 | cr0 &= ~SPI_TMOD_MASK; |
052dc7c4 GS |
347 | cr0 |= (chip->tmode << SPI_TMOD_OFFSET); |
348 | } | |
349 | ||
dd114443 | 350 | dw_writel(dws, DW_SPI_CTRL0, cr0); |
0b2e8915 | 351 | |
e24c7452 | 352 | /* Check if current transfer is a DMA transaction */ |
f89a6d8f AS |
353 | if (master->can_dma && master->can_dma(master, spi, transfer)) |
354 | dws->dma_mapped = master->cur_msg_mapped; | |
e24c7452 | 355 | |
0b2e8915 AS |
356 | /* For poll mode just disable all interrupts */ |
357 | spi_mask_intr(dws, 0xff); | |
358 | ||
552e4509 FT |
359 | /* |
360 | * Interrupt mode | |
361 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely | |
362 | */ | |
9f14538e | 363 | if (dws->dma_mapped) { |
f89a6d8f | 364 | ret = dws->dma_ops->dma_setup(dws, transfer); |
9f14538e AS |
365 | if (ret < 0) { |
366 | spi_enable_chip(dws, 1); | |
367 | return ret; | |
368 | } | |
369 | } else if (!chip->poll_mode) { | |
ea11370f | 370 | txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); |
dd114443 | 371 | dw_writel(dws, DW_SPI_TXFLTR, txlevel); |
552e4509 | 372 | |
0b2e8915 | 373 | /* Set the interrupt mask */ |
fadcace7 JH |
374 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
375 | SPI_INT_RXUI | SPI_INT_RXOI; | |
0b2e8915 AS |
376 | spi_umask_intr(dws, imask); |
377 | ||
e24c7452 FT |
378 | dws->transfer_handler = interrupt_transfer; |
379 | } | |
380 | ||
0b2e8915 | 381 | spi_enable_chip(dws, 1); |
e24c7452 | 382 | |
9f14538e | 383 | if (dws->dma_mapped) { |
f89a6d8f | 384 | ret = dws->dma_ops->dma_transfer(dws, transfer); |
9f14538e AS |
385 | if (ret < 0) |
386 | return ret; | |
387 | } | |
e24c7452 FT |
388 | |
389 | if (chip->poll_mode) | |
c22c62db | 390 | return poll_transfer(dws); |
e24c7452 | 391 | |
c22c62db | 392 | return 1; |
e24c7452 FT |
393 | } |
394 | ||
c22c62db | 395 | static void dw_spi_handle_err(struct spi_master *master, |
ec37e8e1 | 396 | struct spi_message *msg) |
e24c7452 | 397 | { |
ec37e8e1 | 398 | struct dw_spi *dws = spi_master_get_devdata(master); |
e24c7452 | 399 | |
4d5ac1ed AS |
400 | if (dws->dma_mapped) |
401 | dws->dma_ops->dma_stop(dws); | |
402 | ||
c22c62db | 403 | spi_reset_chip(dws); |
e24c7452 FT |
404 | } |
405 | ||
406 | /* This may be called twice for each spi dev */ | |
407 | static int dw_spi_setup(struct spi_device *spi) | |
408 | { | |
409 | struct dw_spi_chip *chip_info = NULL; | |
410 | struct chip_data *chip; | |
d9c73bb8 | 411 | int ret; |
e24c7452 | 412 | |
e24c7452 FT |
413 | /* Only alloc on first setup */ |
414 | chip = spi_get_ctldata(spi); | |
415 | if (!chip) { | |
a97c883a | 416 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
e24c7452 FT |
417 | if (!chip) |
418 | return -ENOMEM; | |
43f627ac | 419 | spi_set_ctldata(spi, chip); |
e24c7452 FT |
420 | } |
421 | ||
422 | /* | |
423 | * Protocol drivers may change the chip settings, so... | |
424 | * if chip_info exists, use it | |
425 | */ | |
426 | chip_info = spi->controller_data; | |
427 | ||
428 | /* chip_info doesn't always exist */ | |
429 | if (chip_info) { | |
430 | if (chip_info->cs_control) | |
431 | chip->cs_control = chip_info->cs_control; | |
432 | ||
433 | chip->poll_mode = chip_info->poll_mode; | |
434 | chip->type = chip_info->type; | |
435 | ||
436 | chip->rx_threshold = 0; | |
437 | chip->tx_threshold = 0; | |
e24c7452 FT |
438 | } |
439 | ||
24778be2 | 440 | if (spi->bits_per_word == 8) { |
e24c7452 FT |
441 | chip->n_bytes = 1; |
442 | chip->dma_width = 1; | |
24778be2 | 443 | } else if (spi->bits_per_word == 16) { |
e24c7452 FT |
444 | chip->n_bytes = 2; |
445 | chip->dma_width = 2; | |
e24c7452 FT |
446 | } |
447 | chip->bits_per_word = spi->bits_per_word; | |
448 | ||
e24c7452 | 449 | chip->tmode = 0; /* Tx & Rx */ |
c3ce15bf | 450 | |
d9c73bb8 BS |
451 | if (gpio_is_valid(spi->cs_gpio)) { |
452 | ret = gpio_direction_output(spi->cs_gpio, | |
453 | !(spi->mode & SPI_CS_HIGH)); | |
454 | if (ret) | |
455 | return ret; | |
456 | } | |
457 | ||
e24c7452 FT |
458 | return 0; |
459 | } | |
460 | ||
a97c883a AL |
461 | static void dw_spi_cleanup(struct spi_device *spi) |
462 | { | |
463 | struct chip_data *chip = spi_get_ctldata(spi); | |
464 | ||
465 | kfree(chip); | |
466 | spi_set_ctldata(spi, NULL); | |
467 | } | |
468 | ||
e24c7452 | 469 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
30b4b703 | 470 | static void spi_hw_init(struct device *dev, struct dw_spi *dws) |
e24c7452 | 471 | { |
45746e82 | 472 | spi_reset_chip(dws); |
c587b6fa FT |
473 | |
474 | /* | |
475 | * Try to detect the FIFO depth if not set by interface driver, | |
476 | * the depth could be from 2 to 256 from HW spec | |
477 | */ | |
478 | if (!dws->fifo_len) { | |
479 | u32 fifo; | |
fadcace7 | 480 | |
9d239d35 | 481 | for (fifo = 1; fifo < 256; fifo++) { |
dd114443 TT |
482 | dw_writel(dws, DW_SPI_TXFLTR, fifo); |
483 | if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) | |
c587b6fa FT |
484 | break; |
485 | } | |
dd114443 | 486 | dw_writel(dws, DW_SPI_TXFLTR, 0); |
c587b6fa | 487 | |
9d239d35 | 488 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
30b4b703 | 489 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
c587b6fa | 490 | } |
e24c7452 FT |
491 | } |
492 | ||
04f421e7 | 493 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
e24c7452 FT |
494 | { |
495 | struct spi_master *master; | |
496 | int ret; | |
497 | ||
498 | BUG_ON(dws == NULL); | |
499 | ||
04f421e7 BS |
500 | master = spi_alloc_master(dev, 0); |
501 | if (!master) | |
502 | return -ENOMEM; | |
e24c7452 FT |
503 | |
504 | dws->master = master; | |
505 | dws->type = SSI_MOTO_SPI; | |
e24c7452 FT |
506 | dws->dma_inited = 0; |
507 | dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); | |
c3c6e231 | 508 | snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); |
e24c7452 | 509 | |
04f421e7 | 510 | ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED, |
c22c62db | 511 | dws->name, master); |
e24c7452 | 512 | if (ret < 0) { |
5f0966e6 | 513 | dev_err(dev, "can not get IRQ\n"); |
e24c7452 FT |
514 | goto err_free_master; |
515 | } | |
516 | ||
c3ce15bf | 517 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
24778be2 | 518 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
e24c7452 FT |
519 | master->bus_num = dws->bus_num; |
520 | master->num_chipselect = dws->num_cs; | |
e24c7452 | 521 | master->setup = dw_spi_setup; |
a97c883a | 522 | master->cleanup = dw_spi_cleanup; |
c22c62db AS |
523 | master->set_cs = dw_spi_set_cs; |
524 | master->transfer_one = dw_spi_transfer_one; | |
525 | master->handle_err = dw_spi_handle_err; | |
765ee709 | 526 | master->max_speed_hz = dws->max_freq; |
9c6de47d | 527 | master->dev.of_node = dev->of_node; |
e24c7452 | 528 | |
e24c7452 | 529 | /* Basic HW init */ |
30b4b703 | 530 | spi_hw_init(dev, dws); |
e24c7452 | 531 | |
7063c0d9 FT |
532 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
533 | ret = dws->dma_ops->dma_init(dws); | |
534 | if (ret) { | |
3dbb3b98 | 535 | dev_warn(dev, "DMA init failed\n"); |
7063c0d9 | 536 | dws->dma_inited = 0; |
f89a6d8f AS |
537 | } else { |
538 | master->can_dma = dws->dma_ops->can_dma; | |
7063c0d9 FT |
539 | } |
540 | } | |
541 | ||
e24c7452 | 542 | spi_master_set_devdata(master, dws); |
04f421e7 | 543 | ret = devm_spi_register_master(dev, master); |
e24c7452 FT |
544 | if (ret) { |
545 | dev_err(&master->dev, "problem registering spi master\n"); | |
ec37e8e1 | 546 | goto err_dma_exit; |
e24c7452 FT |
547 | } |
548 | ||
53288fe9 | 549 | dw_spi_debugfs_init(dws); |
e24c7452 FT |
550 | return 0; |
551 | ||
ec37e8e1 | 552 | err_dma_exit: |
7063c0d9 FT |
553 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
554 | dws->dma_ops->dma_exit(dws); | |
e24c7452 | 555 | spi_enable_chip(dws, 0); |
e24c7452 FT |
556 | err_free_master: |
557 | spi_master_put(master); | |
e24c7452 FT |
558 | return ret; |
559 | } | |
79290a2a | 560 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
e24c7452 | 561 | |
fd4a319b | 562 | void dw_spi_remove_host(struct dw_spi *dws) |
e24c7452 | 563 | { |
e24c7452 FT |
564 | if (!dws) |
565 | return; | |
53288fe9 | 566 | dw_spi_debugfs_remove(dws); |
e24c7452 | 567 | |
7063c0d9 FT |
568 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
569 | dws->dma_ops->dma_exit(dws); | |
e24c7452 FT |
570 | spi_enable_chip(dws, 0); |
571 | /* Disable clk */ | |
572 | spi_set_clk(dws, 0); | |
e24c7452 | 573 | } |
79290a2a | 574 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
e24c7452 FT |
575 | |
576 | int dw_spi_suspend_host(struct dw_spi *dws) | |
577 | { | |
578 | int ret = 0; | |
579 | ||
ec37e8e1 | 580 | ret = spi_master_suspend(dws->master); |
e24c7452 FT |
581 | if (ret) |
582 | return ret; | |
583 | spi_enable_chip(dws, 0); | |
584 | spi_set_clk(dws, 0); | |
585 | return ret; | |
586 | } | |
79290a2a | 587 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
e24c7452 FT |
588 | |
589 | int dw_spi_resume_host(struct dw_spi *dws) | |
590 | { | |
591 | int ret; | |
592 | ||
30b4b703 | 593 | spi_hw_init(&dws->master->dev, dws); |
ec37e8e1 | 594 | ret = spi_master_resume(dws->master); |
e24c7452 FT |
595 | if (ret) |
596 | dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); | |
597 | return ret; | |
598 | } | |
79290a2a | 599 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
e24c7452 FT |
600 | |
601 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
602 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); | |
603 | MODULE_LICENSE("GPL v2"); |