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011f23a3 MW |
1 | /* |
2 | * Driver for Cirrus Logic EP93xx SPI controller. | |
3 | * | |
626a96db | 4 | * Copyright (C) 2010-2011 Mika Westerberg |
011f23a3 MW |
5 | * |
6 | * Explicit FIFO handling code was inspired by amba-pl022 driver. | |
7 | * | |
8 | * Chip select support using other than built-in GPIOs by H. Hartley Sweeten. | |
9 | * | |
10 | * For more information about the SPI controller see documentation on Cirrus | |
11 | * Logic web site: | |
12 | * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/io.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/device.h> | |
626a96db | 24 | #include <linux/dmaengine.h> |
011f23a3 MW |
25 | #include <linux/bitops.h> |
26 | #include <linux/interrupt.h> | |
5bdb7613 | 27 | #include <linux/module.h> |
011f23a3 | 28 | #include <linux/platform_device.h> |
011f23a3 | 29 | #include <linux/sched.h> |
626a96db | 30 | #include <linux/scatterlist.h> |
011f23a3 MW |
31 | #include <linux/spi/spi.h> |
32 | ||
a3b29245 AB |
33 | #include <linux/platform_data/dma-ep93xx.h> |
34 | #include <linux/platform_data/spi-ep93xx.h> | |
011f23a3 MW |
35 | |
36 | #define SSPCR0 0x0000 | |
37 | #define SSPCR0_MODE_SHIFT 6 | |
38 | #define SSPCR0_SCR_SHIFT 8 | |
39 | ||
40 | #define SSPCR1 0x0004 | |
41 | #define SSPCR1_RIE BIT(0) | |
42 | #define SSPCR1_TIE BIT(1) | |
43 | #define SSPCR1_RORIE BIT(2) | |
44 | #define SSPCR1_LBM BIT(3) | |
45 | #define SSPCR1_SSE BIT(4) | |
46 | #define SSPCR1_MS BIT(5) | |
47 | #define SSPCR1_SOD BIT(6) | |
48 | ||
49 | #define SSPDR 0x0008 | |
50 | ||
51 | #define SSPSR 0x000c | |
52 | #define SSPSR_TFE BIT(0) | |
53 | #define SSPSR_TNF BIT(1) | |
54 | #define SSPSR_RNE BIT(2) | |
55 | #define SSPSR_RFF BIT(3) | |
56 | #define SSPSR_BSY BIT(4) | |
57 | #define SSPCPSR 0x0010 | |
58 | ||
59 | #define SSPIIR 0x0014 | |
60 | #define SSPIIR_RIS BIT(0) | |
61 | #define SSPIIR_TIS BIT(1) | |
62 | #define SSPIIR_RORIS BIT(2) | |
63 | #define SSPICR SSPIIR | |
64 | ||
65 | /* timeout in milliseconds */ | |
66 | #define SPI_TIMEOUT 5 | |
67 | /* maximum depth of RX/TX FIFO */ | |
68 | #define SPI_FIFO_SIZE 8 | |
69 | ||
70 | /** | |
71 | * struct ep93xx_spi - EP93xx SPI controller structure | |
011f23a3 MW |
72 | * @pdev: pointer to platform device |
73 | * @clk: clock for the controller | |
74 | * @regs_base: pointer to ioremap()'d registers | |
626a96db | 75 | * @sspdr_phys: physical address of the SSPDR register |
011f23a3 | 76 | * @wait: wait here until given transfer is completed |
011f23a3 MW |
77 | * @current_msg: message that is currently processed (or %NULL if none) |
78 | * @tx: current byte in transfer to transmit | |
79 | * @rx: current byte in transfer to receive | |
80 | * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one | |
81 | * frame decreases this level and sending one frame increases it. | |
626a96db MW |
82 | * @dma_rx: RX DMA channel |
83 | * @dma_tx: TX DMA channel | |
84 | * @dma_rx_data: RX parameters passed to the DMA engine | |
85 | * @dma_tx_data: TX parameters passed to the DMA engine | |
86 | * @rx_sgt: sg table for RX transfers | |
87 | * @tx_sgt: sg table for TX transfers | |
88 | * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by | |
89 | * the client | |
011f23a3 MW |
90 | */ |
91 | struct ep93xx_spi { | |
011f23a3 MW |
92 | const struct platform_device *pdev; |
93 | struct clk *clk; | |
94 | void __iomem *regs_base; | |
626a96db | 95 | unsigned long sspdr_phys; |
011f23a3 | 96 | struct completion wait; |
011f23a3 MW |
97 | struct spi_message *current_msg; |
98 | size_t tx; | |
99 | size_t rx; | |
100 | size_t fifo_level; | |
626a96db MW |
101 | struct dma_chan *dma_rx; |
102 | struct dma_chan *dma_tx; | |
103 | struct ep93xx_dma_data dma_rx_data; | |
104 | struct ep93xx_dma_data dma_tx_data; | |
105 | struct sg_table rx_sgt; | |
106 | struct sg_table tx_sgt; | |
107 | void *zeropage; | |
011f23a3 MW |
108 | }; |
109 | ||
110 | /** | |
111 | * struct ep93xx_spi_chip - SPI device hardware settings | |
112 | * @spi: back pointer to the SPI device | |
011f23a3 | 113 | * @ops: private chip operations |
011f23a3 MW |
114 | */ |
115 | struct ep93xx_spi_chip { | |
116 | const struct spi_device *spi; | |
011f23a3 MW |
117 | struct ep93xx_spi_chip_ops *ops; |
118 | }; | |
119 | ||
120 | /* converts bits per word to CR0.DSS value */ | |
121 | #define bits_per_word_to_dss(bpw) ((bpw) - 1) | |
122 | ||
8d7586bd HS |
123 | static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi, |
124 | u16 reg, u8 value) | |
011f23a3 | 125 | { |
8d7586bd | 126 | writeb(value, espi->regs_base + reg); |
011f23a3 MW |
127 | } |
128 | ||
8d7586bd | 129 | static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg) |
011f23a3 | 130 | { |
8d7586bd | 131 | return readb(spi->regs_base + reg); |
011f23a3 MW |
132 | } |
133 | ||
8d7586bd HS |
134 | static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi, |
135 | u16 reg, u16 value) | |
011f23a3 | 136 | { |
8d7586bd | 137 | writew(value, espi->regs_base + reg); |
011f23a3 MW |
138 | } |
139 | ||
8d7586bd | 140 | static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg) |
011f23a3 | 141 | { |
8d7586bd | 142 | return readw(spi->regs_base + reg); |
011f23a3 MW |
143 | } |
144 | ||
145 | static int ep93xx_spi_enable(const struct ep93xx_spi *espi) | |
146 | { | |
147 | u8 regval; | |
148 | int err; | |
149 | ||
150 | err = clk_enable(espi->clk); | |
151 | if (err) | |
152 | return err; | |
153 | ||
154 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
155 | regval |= SSPCR1_SSE; | |
156 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static void ep93xx_spi_disable(const struct ep93xx_spi *espi) | |
162 | { | |
163 | u8 regval; | |
164 | ||
165 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
166 | regval &= ~SSPCR1_SSE; | |
167 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
168 | ||
169 | clk_disable(espi->clk); | |
170 | } | |
171 | ||
172 | static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) | |
173 | { | |
174 | u8 regval; | |
175 | ||
176 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
177 | regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
178 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
179 | } | |
180 | ||
181 | static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) | |
182 | { | |
183 | u8 regval; | |
184 | ||
185 | regval = ep93xx_spi_read_u8(espi, SSPCR1); | |
186 | regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); | |
187 | ep93xx_spi_write_u8(espi, SSPCR1, regval); | |
188 | } | |
189 | ||
190 | /** | |
191 | * ep93xx_spi_calc_divisors() - calculates SPI clock divisors | |
192 | * @espi: ep93xx SPI controller struct | |
011f23a3 | 193 | * @rate: desired SPI output clock rate |
f7ef1da9 HS |
194 | * @div_cpsr: pointer to return the cpsr (pre-scaler) divider |
195 | * @div_scr: pointer to return the scr divider | |
011f23a3 MW |
196 | */ |
197 | static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, | |
56fc0b42 | 198 | u32 rate, u8 *div_cpsr, u8 *div_scr) |
011f23a3 | 199 | { |
56fc0b42 | 200 | struct spi_master *master = platform_get_drvdata(espi->pdev); |
011f23a3 MW |
201 | unsigned long spi_clk_rate = clk_get_rate(espi->clk); |
202 | int cpsr, scr; | |
203 | ||
204 | /* | |
205 | * Make sure that max value is between values supported by the | |
206 | * controller. Note that minimum value is already checked in | |
84ddb3c1 | 207 | * ep93xx_spi_transfer_one_message(). |
011f23a3 | 208 | */ |
56fc0b42 | 209 | rate = clamp(rate, master->min_speed_hz, master->max_speed_hz); |
011f23a3 MW |
210 | |
211 | /* | |
212 | * Calculate divisors so that we can get speed according the | |
213 | * following formula: | |
214 | * rate = spi_clock_rate / (cpsr * (1 + scr)) | |
215 | * | |
216 | * cpsr must be even number and starts from 2, scr can be any number | |
217 | * between 0 and 255. | |
218 | */ | |
219 | for (cpsr = 2; cpsr <= 254; cpsr += 2) { | |
220 | for (scr = 0; scr <= 255; scr++) { | |
221 | if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { | |
f7ef1da9 HS |
222 | *div_scr = (u8)scr; |
223 | *div_cpsr = (u8)cpsr; | |
011f23a3 MW |
224 | return 0; |
225 | } | |
226 | } | |
227 | } | |
228 | ||
229 | return -EINVAL; | |
230 | } | |
231 | ||
232 | static void ep93xx_spi_cs_control(struct spi_device *spi, bool control) | |
233 | { | |
234 | struct ep93xx_spi_chip *chip = spi_get_ctldata(spi); | |
235 | int value = (spi->mode & SPI_CS_HIGH) ? control : !control; | |
236 | ||
237 | if (chip->ops && chip->ops->cs_control) | |
238 | chip->ops->cs_control(spi, value); | |
239 | } | |
240 | ||
241 | /** | |
242 | * ep93xx_spi_setup() - setup an SPI device | |
243 | * @spi: SPI device to setup | |
244 | * | |
245 | * This function sets up SPI device mode, speed etc. Can be called multiple | |
246 | * times for a single device. Returns %0 in case of success, negative error in | |
247 | * case of failure. When this function returns success, the device is | |
248 | * deselected. | |
249 | */ | |
250 | static int ep93xx_spi_setup(struct spi_device *spi) | |
251 | { | |
252 | struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); | |
253 | struct ep93xx_spi_chip *chip; | |
254 | ||
011f23a3 MW |
255 | chip = spi_get_ctldata(spi); |
256 | if (!chip) { | |
257 | dev_dbg(&espi->pdev->dev, "initial setup for %s\n", | |
258 | spi->modalias); | |
259 | ||
260 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); | |
261 | if (!chip) | |
262 | return -ENOMEM; | |
263 | ||
264 | chip->spi = spi; | |
265 | chip->ops = spi->controller_data; | |
266 | ||
267 | if (chip->ops && chip->ops->setup) { | |
268 | int ret = chip->ops->setup(spi); | |
175a3edc | 269 | |
011f23a3 MW |
270 | if (ret) { |
271 | kfree(chip); | |
272 | return ret; | |
273 | } | |
274 | } | |
275 | ||
276 | spi_set_ctldata(spi, chip); | |
277 | } | |
278 | ||
011f23a3 MW |
279 | ep93xx_spi_cs_control(spi, false); |
280 | return 0; | |
281 | } | |
282 | ||
011f23a3 MW |
283 | /** |
284 | * ep93xx_spi_cleanup() - cleans up master controller specific state | |
285 | * @spi: SPI device to cleanup | |
286 | * | |
287 | * This function releases master controller specific state for given @spi | |
288 | * device. | |
289 | */ | |
290 | static void ep93xx_spi_cleanup(struct spi_device *spi) | |
291 | { | |
292 | struct ep93xx_spi_chip *chip; | |
293 | ||
294 | chip = spi_get_ctldata(spi); | |
295 | if (chip) { | |
296 | if (chip->ops && chip->ops->cleanup) | |
297 | chip->ops->cleanup(spi); | |
298 | spi_set_ctldata(spi, NULL); | |
299 | kfree(chip); | |
300 | } | |
301 | } | |
302 | ||
303 | /** | |
304 | * ep93xx_spi_chip_setup() - configures hardware according to given @chip | |
305 | * @espi: ep93xx SPI controller struct | |
306 | * @chip: chip specific settings | |
f7ef1da9 | 307 | * @speed_hz: transfer speed |
d9b65dfd | 308 | * @bits_per_word: transfer bits_per_word |
011f23a3 | 309 | */ |
f7ef1da9 HS |
310 | static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, |
311 | const struct ep93xx_spi_chip *chip, | |
312 | u32 speed_hz, u8 bits_per_word) | |
011f23a3 | 313 | { |
d9b65dfd | 314 | u8 dss = bits_per_word_to_dss(bits_per_word); |
f7ef1da9 HS |
315 | u8 div_cpsr = 0; |
316 | u8 div_scr = 0; | |
011f23a3 | 317 | u16 cr0; |
f7ef1da9 HS |
318 | int err; |
319 | ||
320 | err = ep93xx_spi_calc_divisors(espi, speed_hz, &div_cpsr, &div_scr); | |
321 | if (err) | |
322 | return err; | |
011f23a3 | 323 | |
f7ef1da9 | 324 | cr0 = div_scr << SSPCR0_SCR_SHIFT; |
011f23a3 | 325 | cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT; |
d9b65dfd | 326 | cr0 |= dss; |
011f23a3 MW |
327 | |
328 | dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", | |
f7ef1da9 | 329 | chip->spi->mode, div_cpsr, div_scr, dss); |
a1829d2b | 330 | dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0); |
011f23a3 | 331 | |
f7ef1da9 | 332 | ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr); |
011f23a3 | 333 | ep93xx_spi_write_u16(espi, SSPCR0, cr0); |
f7ef1da9 HS |
334 | |
335 | return 0; | |
011f23a3 MW |
336 | } |
337 | ||
011f23a3 MW |
338 | static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) |
339 | { | |
701c3587 | 340 | if (t->bits_per_word > 8) { |
011f23a3 MW |
341 | u16 tx_val = 0; |
342 | ||
343 | if (t->tx_buf) | |
344 | tx_val = ((u16 *)t->tx_buf)[espi->tx]; | |
345 | ep93xx_spi_write_u16(espi, SSPDR, tx_val); | |
346 | espi->tx += sizeof(tx_val); | |
347 | } else { | |
348 | u8 tx_val = 0; | |
349 | ||
350 | if (t->tx_buf) | |
351 | tx_val = ((u8 *)t->tx_buf)[espi->tx]; | |
352 | ep93xx_spi_write_u8(espi, SSPDR, tx_val); | |
353 | espi->tx += sizeof(tx_val); | |
354 | } | |
355 | } | |
356 | ||
357 | static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) | |
358 | { | |
701c3587 | 359 | if (t->bits_per_word > 8) { |
011f23a3 MW |
360 | u16 rx_val; |
361 | ||
362 | rx_val = ep93xx_spi_read_u16(espi, SSPDR); | |
363 | if (t->rx_buf) | |
364 | ((u16 *)t->rx_buf)[espi->rx] = rx_val; | |
365 | espi->rx += sizeof(rx_val); | |
366 | } else { | |
367 | u8 rx_val; | |
368 | ||
369 | rx_val = ep93xx_spi_read_u8(espi, SSPDR); | |
370 | if (t->rx_buf) | |
371 | ((u8 *)t->rx_buf)[espi->rx] = rx_val; | |
372 | espi->rx += sizeof(rx_val); | |
373 | } | |
374 | } | |
375 | ||
376 | /** | |
377 | * ep93xx_spi_read_write() - perform next RX/TX transfer | |
378 | * @espi: ep93xx SPI controller struct | |
379 | * | |
380 | * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If | |
381 | * called several times, the whole transfer will be completed. Returns | |
382 | * %-EINPROGRESS when current transfer was not yet completed otherwise %0. | |
383 | * | |
384 | * When this function is finished, RX FIFO should be empty and TX FIFO should be | |
385 | * full. | |
386 | */ | |
387 | static int ep93xx_spi_read_write(struct ep93xx_spi *espi) | |
388 | { | |
389 | struct spi_message *msg = espi->current_msg; | |
390 | struct spi_transfer *t = msg->state; | |
391 | ||
392 | /* read as long as RX FIFO has frames in it */ | |
393 | while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { | |
394 | ep93xx_do_read(espi, t); | |
395 | espi->fifo_level--; | |
396 | } | |
397 | ||
398 | /* write as long as TX FIFO has room */ | |
399 | while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) { | |
400 | ep93xx_do_write(espi, t); | |
401 | espi->fifo_level++; | |
402 | } | |
403 | ||
626a96db | 404 | if (espi->rx == t->len) |
011f23a3 | 405 | return 0; |
011f23a3 MW |
406 | |
407 | return -EINPROGRESS; | |
408 | } | |
409 | ||
626a96db MW |
410 | static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi) |
411 | { | |
412 | /* | |
413 | * Now everything is set up for the current transfer. We prime the TX | |
414 | * FIFO, enable interrupts, and wait for the transfer to complete. | |
415 | */ | |
416 | if (ep93xx_spi_read_write(espi)) { | |
417 | ep93xx_spi_enable_interrupts(espi); | |
418 | wait_for_completion(&espi->wait); | |
419 | } | |
420 | } | |
421 | ||
422 | /** | |
423 | * ep93xx_spi_dma_prepare() - prepares a DMA transfer | |
424 | * @espi: ep93xx SPI controller struct | |
425 | * @dir: DMA transfer direction | |
426 | * | |
427 | * Function configures the DMA, maps the buffer and prepares the DMA | |
428 | * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR | |
429 | * in case of failure. | |
430 | */ | |
431 | static struct dma_async_tx_descriptor * | |
d4b9b578 | 432 | ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) |
626a96db MW |
433 | { |
434 | struct spi_transfer *t = espi->current_msg->state; | |
435 | struct dma_async_tx_descriptor *txd; | |
436 | enum dma_slave_buswidth buswidth; | |
437 | struct dma_slave_config conf; | |
438 | struct scatterlist *sg; | |
439 | struct sg_table *sgt; | |
440 | struct dma_chan *chan; | |
441 | const void *buf, *pbuf; | |
442 | size_t len = t->len; | |
443 | int i, ret, nents; | |
444 | ||
701c3587 | 445 | if (t->bits_per_word > 8) |
626a96db MW |
446 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; |
447 | else | |
448 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
449 | ||
450 | memset(&conf, 0, sizeof(conf)); | |
451 | conf.direction = dir; | |
452 | ||
d4b9b578 | 453 | if (dir == DMA_DEV_TO_MEM) { |
626a96db MW |
454 | chan = espi->dma_rx; |
455 | buf = t->rx_buf; | |
456 | sgt = &espi->rx_sgt; | |
457 | ||
458 | conf.src_addr = espi->sspdr_phys; | |
459 | conf.src_addr_width = buswidth; | |
460 | } else { | |
461 | chan = espi->dma_tx; | |
462 | buf = t->tx_buf; | |
463 | sgt = &espi->tx_sgt; | |
464 | ||
465 | conf.dst_addr = espi->sspdr_phys; | |
466 | conf.dst_addr_width = buswidth; | |
467 | } | |
468 | ||
469 | ret = dmaengine_slave_config(chan, &conf); | |
470 | if (ret) | |
471 | return ERR_PTR(ret); | |
472 | ||
473 | /* | |
474 | * We need to split the transfer into PAGE_SIZE'd chunks. This is | |
475 | * because we are using @espi->zeropage to provide a zero RX buffer | |
476 | * for the TX transfers and we have only allocated one page for that. | |
477 | * | |
478 | * For performance reasons we allocate a new sg_table only when | |
479 | * needed. Otherwise we will re-use the current one. Eventually the | |
480 | * last sg_table is released in ep93xx_spi_release_dma(). | |
481 | */ | |
482 | ||
483 | nents = DIV_ROUND_UP(len, PAGE_SIZE); | |
484 | if (nents != sgt->nents) { | |
485 | sg_free_table(sgt); | |
486 | ||
487 | ret = sg_alloc_table(sgt, nents, GFP_KERNEL); | |
488 | if (ret) | |
489 | return ERR_PTR(ret); | |
490 | } | |
491 | ||
492 | pbuf = buf; | |
493 | for_each_sg(sgt->sgl, sg, sgt->nents, i) { | |
494 | size_t bytes = min_t(size_t, len, PAGE_SIZE); | |
495 | ||
496 | if (buf) { | |
497 | sg_set_page(sg, virt_to_page(pbuf), bytes, | |
498 | offset_in_page(pbuf)); | |
499 | } else { | |
500 | sg_set_page(sg, virt_to_page(espi->zeropage), | |
501 | bytes, 0); | |
502 | } | |
503 | ||
504 | pbuf += bytes; | |
505 | len -= bytes; | |
506 | } | |
507 | ||
508 | if (WARN_ON(len)) { | |
a1829d2b | 509 | dev_warn(&espi->pdev->dev, "len = %zu expected 0!\n", len); |
626a96db MW |
510 | return ERR_PTR(-EINVAL); |
511 | } | |
512 | ||
513 | nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
514 | if (!nents) | |
515 | return ERR_PTR(-ENOMEM); | |
516 | ||
d4b9b578 | 517 | txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK); |
626a96db MW |
518 | if (!txd) { |
519 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
520 | return ERR_PTR(-ENOMEM); | |
521 | } | |
522 | return txd; | |
523 | } | |
524 | ||
525 | /** | |
526 | * ep93xx_spi_dma_finish() - finishes with a DMA transfer | |
527 | * @espi: ep93xx SPI controller struct | |
528 | * @dir: DMA transfer direction | |
529 | * | |
530 | * Function finishes with the DMA transfer. After this, the DMA buffer is | |
531 | * unmapped. | |
532 | */ | |
533 | static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, | |
d4b9b578 | 534 | enum dma_transfer_direction dir) |
626a96db MW |
535 | { |
536 | struct dma_chan *chan; | |
537 | struct sg_table *sgt; | |
538 | ||
d4b9b578 | 539 | if (dir == DMA_DEV_TO_MEM) { |
626a96db MW |
540 | chan = espi->dma_rx; |
541 | sgt = &espi->rx_sgt; | |
542 | } else { | |
543 | chan = espi->dma_tx; | |
544 | sgt = &espi->tx_sgt; | |
545 | } | |
546 | ||
547 | dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir); | |
548 | } | |
549 | ||
550 | static void ep93xx_spi_dma_callback(void *callback_param) | |
551 | { | |
552 | complete(callback_param); | |
553 | } | |
554 | ||
555 | static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) | |
556 | { | |
557 | struct spi_message *msg = espi->current_msg; | |
558 | struct dma_async_tx_descriptor *rxd, *txd; | |
559 | ||
d4b9b578 | 560 | rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); |
626a96db MW |
561 | if (IS_ERR(rxd)) { |
562 | dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); | |
563 | msg->status = PTR_ERR(rxd); | |
564 | return; | |
565 | } | |
566 | ||
d4b9b578 | 567 | txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); |
626a96db | 568 | if (IS_ERR(txd)) { |
d4b9b578 | 569 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); |
626a96db MW |
570 | dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd)); |
571 | msg->status = PTR_ERR(txd); | |
572 | return; | |
573 | } | |
574 | ||
575 | /* We are ready when RX is done */ | |
576 | rxd->callback = ep93xx_spi_dma_callback; | |
577 | rxd->callback_param = &espi->wait; | |
578 | ||
579 | /* Now submit both descriptors and wait while they finish */ | |
580 | dmaengine_submit(rxd); | |
581 | dmaengine_submit(txd); | |
582 | ||
583 | dma_async_issue_pending(espi->dma_rx); | |
584 | dma_async_issue_pending(espi->dma_tx); | |
585 | ||
586 | wait_for_completion(&espi->wait); | |
587 | ||
d4b9b578 HS |
588 | ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV); |
589 | ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); | |
626a96db MW |
590 | } |
591 | ||
011f23a3 MW |
592 | /** |
593 | * ep93xx_spi_process_transfer() - processes one SPI transfer | |
594 | * @espi: ep93xx SPI controller struct | |
595 | * @msg: current message | |
596 | * @t: transfer to process | |
597 | * | |
598 | * This function processes one SPI transfer given in @t. Function waits until | |
599 | * transfer is complete (may sleep) and updates @msg->status based on whether | |
25985edc | 600 | * transfer was successfully processed or not. |
011f23a3 MW |
601 | */ |
602 | static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi, | |
603 | struct spi_message *msg, | |
604 | struct spi_transfer *t) | |
605 | { | |
606 | struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi); | |
4870c217 | 607 | int err; |
011f23a3 MW |
608 | |
609 | msg->state = t; | |
610 | ||
f7ef1da9 | 611 | err = ep93xx_spi_chip_setup(espi, chip, t->speed_hz, t->bits_per_word); |
4870c217 | 612 | if (err) { |
f7ef1da9 HS |
613 | dev_err(&espi->pdev->dev, |
614 | "failed to setup chip for transfer\n"); | |
4870c217 HS |
615 | msg->status = err; |
616 | return; | |
617 | } | |
011f23a3 | 618 | |
011f23a3 MW |
619 | espi->rx = 0; |
620 | espi->tx = 0; | |
621 | ||
622 | /* | |
626a96db MW |
623 | * There is no point of setting up DMA for the transfers which will |
624 | * fit into the FIFO and can be transferred with a single interrupt. | |
625 | * So in these cases we will be using PIO and don't bother for DMA. | |
011f23a3 | 626 | */ |
626a96db MW |
627 | if (espi->dma_rx && t->len > SPI_FIFO_SIZE) |
628 | ep93xx_spi_dma_transfer(espi); | |
629 | else | |
630 | ep93xx_spi_pio_transfer(espi); | |
011f23a3 MW |
631 | |
632 | /* | |
633 | * In case of error during transmit, we bail out from processing | |
634 | * the message. | |
635 | */ | |
636 | if (msg->status) | |
637 | return; | |
638 | ||
626a96db MW |
639 | msg->actual_length += t->len; |
640 | ||
011f23a3 MW |
641 | /* |
642 | * After this transfer is finished, perform any possible | |
643 | * post-transfer actions requested by the protocol driver. | |
644 | */ | |
645 | if (t->delay_usecs) { | |
646 | set_current_state(TASK_UNINTERRUPTIBLE); | |
647 | schedule_timeout(usecs_to_jiffies(t->delay_usecs)); | |
648 | } | |
649 | if (t->cs_change) { | |
650 | if (!list_is_last(&t->transfer_list, &msg->transfers)) { | |
651 | /* | |
652 | * In case protocol driver is asking us to drop the | |
653 | * chipselect briefly, we let the scheduler to handle | |
654 | * any "delay" here. | |
655 | */ | |
656 | ep93xx_spi_cs_control(msg->spi, false); | |
657 | cond_resched(); | |
658 | ep93xx_spi_cs_control(msg->spi, true); | |
659 | } | |
660 | } | |
011f23a3 MW |
661 | } |
662 | ||
663 | /* | |
664 | * ep93xx_spi_process_message() - process one SPI message | |
665 | * @espi: ep93xx SPI controller struct | |
666 | * @msg: message to process | |
667 | * | |
668 | * This function processes a single SPI message. We go through all transfers in | |
669 | * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is | |
670 | * asserted during the whole message (unless per transfer cs_change is set). | |
671 | * | |
672 | * @msg->status contains %0 in case of success or negative error code in case of | |
673 | * failure. | |
674 | */ | |
675 | static void ep93xx_spi_process_message(struct ep93xx_spi *espi, | |
676 | struct spi_message *msg) | |
677 | { | |
678 | unsigned long timeout; | |
679 | struct spi_transfer *t; | |
680 | int err; | |
681 | ||
682 | /* | |
683 | * Enable the SPI controller and its clock. | |
684 | */ | |
685 | err = ep93xx_spi_enable(espi); | |
686 | if (err) { | |
687 | dev_err(&espi->pdev->dev, "failed to enable SPI controller\n"); | |
688 | msg->status = err; | |
689 | return; | |
690 | } | |
691 | ||
692 | /* | |
693 | * Just to be sure: flush any data from RX FIFO. | |
694 | */ | |
695 | timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); | |
696 | while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { | |
697 | if (time_after(jiffies, timeout)) { | |
698 | dev_warn(&espi->pdev->dev, | |
699 | "timeout while flushing RX FIFO\n"); | |
700 | msg->status = -ETIMEDOUT; | |
701 | return; | |
702 | } | |
703 | ep93xx_spi_read_u16(espi, SSPDR); | |
704 | } | |
705 | ||
706 | /* | |
707 | * We explicitly handle FIFO level. This way we don't have to check TX | |
708 | * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns. | |
709 | */ | |
710 | espi->fifo_level = 0; | |
711 | ||
712 | /* | |
4870c217 | 713 | * Assert the chipselect. |
011f23a3 | 714 | */ |
011f23a3 MW |
715 | ep93xx_spi_cs_control(msg->spi, true); |
716 | ||
717 | list_for_each_entry(t, &msg->transfers, transfer_list) { | |
718 | ep93xx_spi_process_transfer(espi, msg, t); | |
719 | if (msg->status) | |
720 | break; | |
721 | } | |
722 | ||
723 | /* | |
724 | * Now the whole message is transferred (or failed for some reason). We | |
725 | * deselect the device and disable the SPI controller. | |
726 | */ | |
727 | ep93xx_spi_cs_control(msg->spi, false); | |
728 | ep93xx_spi_disable(espi); | |
729 | } | |
730 | ||
84ddb3c1 HS |
731 | static int ep93xx_spi_transfer_one_message(struct spi_master *master, |
732 | struct spi_message *msg) | |
011f23a3 | 733 | { |
84ddb3c1 | 734 | struct ep93xx_spi *espi = spi_master_get_devdata(master); |
011f23a3 | 735 | |
84ddb3c1 HS |
736 | msg->state = NULL; |
737 | msg->status = 0; | |
738 | msg->actual_length = 0; | |
011f23a3 | 739 | |
84ddb3c1 HS |
740 | espi->current_msg = msg; |
741 | ep93xx_spi_process_message(espi, msg); | |
011f23a3 | 742 | espi->current_msg = NULL; |
011f23a3 | 743 | |
84ddb3c1 HS |
744 | spi_finalize_current_message(master); |
745 | ||
746 | return 0; | |
011f23a3 MW |
747 | } |
748 | ||
749 | static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) | |
750 | { | |
751 | struct ep93xx_spi *espi = dev_id; | |
752 | u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); | |
753 | ||
754 | /* | |
755 | * If we got ROR (receive overrun) interrupt we know that something is | |
756 | * wrong. Just abort the message. | |
757 | */ | |
758 | if (unlikely(irq_status & SSPIIR_RORIS)) { | |
759 | /* clear the overrun interrupt */ | |
760 | ep93xx_spi_write_u8(espi, SSPICR, 0); | |
761 | dev_warn(&espi->pdev->dev, | |
762 | "receive overrun, aborting the message\n"); | |
763 | espi->current_msg->status = -EIO; | |
764 | } else { | |
765 | /* | |
766 | * Interrupt is either RX (RIS) or TX (TIS). For both cases we | |
767 | * simply execute next data transfer. | |
768 | */ | |
769 | if (ep93xx_spi_read_write(espi)) { | |
770 | /* | |
771 | * In normal case, there still is some processing left | |
772 | * for current transfer. Let's wait for the next | |
773 | * interrupt then. | |
774 | */ | |
775 | return IRQ_HANDLED; | |
776 | } | |
777 | } | |
778 | ||
779 | /* | |
780 | * Current transfer is finished, either with error or with success. In | |
781 | * any case we disable interrupts and notify the worker to handle | |
782 | * any post-processing of the message. | |
783 | */ | |
784 | ep93xx_spi_disable_interrupts(espi); | |
785 | complete(&espi->wait); | |
786 | return IRQ_HANDLED; | |
787 | } | |
788 | ||
626a96db MW |
789 | static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) |
790 | { | |
791 | if (ep93xx_dma_chan_is_m2p(chan)) | |
792 | return false; | |
793 | ||
794 | chan->private = filter_param; | |
795 | return true; | |
796 | } | |
797 | ||
798 | static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) | |
799 | { | |
800 | dma_cap_mask_t mask; | |
801 | int ret; | |
802 | ||
803 | espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL); | |
804 | if (!espi->zeropage) | |
805 | return -ENOMEM; | |
806 | ||
807 | dma_cap_zero(mask); | |
808 | dma_cap_set(DMA_SLAVE, mask); | |
809 | ||
810 | espi->dma_rx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 811 | espi->dma_rx_data.direction = DMA_DEV_TO_MEM; |
626a96db MW |
812 | espi->dma_rx_data.name = "ep93xx-spi-rx"; |
813 | ||
814 | espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
815 | &espi->dma_rx_data); | |
816 | if (!espi->dma_rx) { | |
817 | ret = -ENODEV; | |
818 | goto fail_free_page; | |
819 | } | |
820 | ||
821 | espi->dma_tx_data.port = EP93XX_DMA_SSP; | |
a485df4b | 822 | espi->dma_tx_data.direction = DMA_MEM_TO_DEV; |
626a96db MW |
823 | espi->dma_tx_data.name = "ep93xx-spi-tx"; |
824 | ||
825 | espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, | |
826 | &espi->dma_tx_data); | |
827 | if (!espi->dma_tx) { | |
828 | ret = -ENODEV; | |
829 | goto fail_release_rx; | |
830 | } | |
831 | ||
832 | return 0; | |
833 | ||
834 | fail_release_rx: | |
835 | dma_release_channel(espi->dma_rx); | |
836 | espi->dma_rx = NULL; | |
837 | fail_free_page: | |
838 | free_page((unsigned long)espi->zeropage); | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
843 | static void ep93xx_spi_release_dma(struct ep93xx_spi *espi) | |
844 | { | |
845 | if (espi->dma_rx) { | |
846 | dma_release_channel(espi->dma_rx); | |
847 | sg_free_table(&espi->rx_sgt); | |
848 | } | |
849 | if (espi->dma_tx) { | |
850 | dma_release_channel(espi->dma_tx); | |
851 | sg_free_table(&espi->tx_sgt); | |
852 | } | |
853 | ||
854 | if (espi->zeropage) | |
855 | free_page((unsigned long)espi->zeropage); | |
856 | } | |
857 | ||
fd4a319b | 858 | static int ep93xx_spi_probe(struct platform_device *pdev) |
011f23a3 MW |
859 | { |
860 | struct spi_master *master; | |
861 | struct ep93xx_spi_info *info; | |
862 | struct ep93xx_spi *espi; | |
863 | struct resource *res; | |
6d6467ee | 864 | int irq; |
011f23a3 MW |
865 | int error; |
866 | ||
8074cf06 | 867 | info = dev_get_platdata(&pdev->dev); |
011f23a3 | 868 | |
48a7776e HS |
869 | irq = platform_get_irq(pdev, 0); |
870 | if (irq < 0) { | |
871 | dev_err(&pdev->dev, "failed to get irq resources\n"); | |
872 | return -EBUSY; | |
873 | } | |
874 | ||
875 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
876 | if (!res) { | |
877 | dev_err(&pdev->dev, "unable to get iomem resource\n"); | |
878 | return -ENODEV; | |
879 | } | |
880 | ||
011f23a3 | 881 | master = spi_alloc_master(&pdev->dev, sizeof(*espi)); |
b2d185ed | 882 | if (!master) |
011f23a3 | 883 | return -ENOMEM; |
011f23a3 MW |
884 | |
885 | master->setup = ep93xx_spi_setup; | |
84ddb3c1 | 886 | master->transfer_one_message = ep93xx_spi_transfer_one_message; |
011f23a3 MW |
887 | master->cleanup = ep93xx_spi_cleanup; |
888 | master->bus_num = pdev->id; | |
889 | master->num_chipselect = info->num_chipselect; | |
890 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 891 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
011f23a3 MW |
892 | |
893 | platform_set_drvdata(pdev, master); | |
894 | ||
895 | espi = spi_master_get_devdata(master); | |
896 | ||
e6eb8d9b | 897 | espi->clk = devm_clk_get(&pdev->dev, NULL); |
011f23a3 MW |
898 | if (IS_ERR(espi->clk)) { |
899 | dev_err(&pdev->dev, "unable to get spi clock\n"); | |
900 | error = PTR_ERR(espi->clk); | |
901 | goto fail_release_master; | |
902 | } | |
903 | ||
011f23a3 MW |
904 | init_completion(&espi->wait); |
905 | ||
906 | /* | |
907 | * Calculate maximum and minimum supported clock rates | |
908 | * for the controller. | |
909 | */ | |
56fc0b42 AL |
910 | master->max_speed_hz = clk_get_rate(espi->clk) / 2; |
911 | master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256); | |
011f23a3 MW |
912 | espi->pdev = pdev; |
913 | ||
626a96db | 914 | espi->sspdr_phys = res->start + SSPDR; |
6d6467ee | 915 | |
b0ee5605 TR |
916 | espi->regs_base = devm_ioremap_resource(&pdev->dev, res); |
917 | if (IS_ERR(espi->regs_base)) { | |
918 | error = PTR_ERR(espi->regs_base); | |
e6eb8d9b | 919 | goto fail_release_master; |
011f23a3 MW |
920 | } |
921 | ||
6d6467ee HH |
922 | error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, |
923 | 0, "ep93xx-spi", espi); | |
011f23a3 MW |
924 | if (error) { |
925 | dev_err(&pdev->dev, "failed to request irq\n"); | |
e6eb8d9b | 926 | goto fail_release_master; |
011f23a3 MW |
927 | } |
928 | ||
626a96db MW |
929 | if (info->use_dma && ep93xx_spi_setup_dma(espi)) |
930 | dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); | |
931 | ||
011f23a3 MW |
932 | /* make sure that the hardware is disabled */ |
933 | ep93xx_spi_write_u8(espi, SSPCR1, 0); | |
934 | ||
434eaf3b | 935 | error = devm_spi_register_master(&pdev->dev, master); |
011f23a3 MW |
936 | if (error) { |
937 | dev_err(&pdev->dev, "failed to register SPI master\n"); | |
84ddb3c1 | 938 | goto fail_free_dma; |
011f23a3 MW |
939 | } |
940 | ||
941 | dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n", | |
6d6467ee | 942 | (unsigned long)res->start, irq); |
011f23a3 MW |
943 | |
944 | return 0; | |
945 | ||
626a96db MW |
946 | fail_free_dma: |
947 | ep93xx_spi_release_dma(espi); | |
011f23a3 MW |
948 | fail_release_master: |
949 | spi_master_put(master); | |
011f23a3 MW |
950 | |
951 | return error; | |
952 | } | |
953 | ||
fd4a319b | 954 | static int ep93xx_spi_remove(struct platform_device *pdev) |
011f23a3 MW |
955 | { |
956 | struct spi_master *master = platform_get_drvdata(pdev); | |
957 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | |
011f23a3 | 958 | |
626a96db | 959 | ep93xx_spi_release_dma(espi); |
011f23a3 | 960 | |
011f23a3 MW |
961 | return 0; |
962 | } | |
963 | ||
964 | static struct platform_driver ep93xx_spi_driver = { | |
965 | .driver = { | |
966 | .name = "ep93xx-spi", | |
011f23a3 | 967 | }, |
940ab889 | 968 | .probe = ep93xx_spi_probe, |
fd4a319b | 969 | .remove = ep93xx_spi_remove, |
011f23a3 | 970 | }; |
940ab889 | 971 | module_platform_driver(ep93xx_spi_driver); |
011f23a3 MW |
972 | |
973 | MODULE_DESCRIPTION("EP93xx SPI Controller driver"); | |
974 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); | |
975 | MODULE_LICENSE("GPL"); | |
976 | MODULE_ALIAS("platform:ep93xx-spi"); |