Commit | Line | Data |
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8b60d6c2 MH |
1 | /* |
2 | * Freescale eSPI controller driver. | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
8b60d6c2 | 11 | #include <linux/delay.h> |
a3108360 | 12 | #include <linux/err.h> |
8b60d6c2 | 13 | #include <linux/fsl_devices.h> |
a3108360 | 14 | #include <linux/interrupt.h> |
a3108360 | 15 | #include <linux/module.h> |
8b60d6c2 MH |
16 | #include <linux/mm.h> |
17 | #include <linux/of.h> | |
5af50730 RH |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
8b60d6c2 | 20 | #include <linux/of_platform.h> |
a3108360 XL |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spi/spi.h> | |
e9abb4db | 23 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
24 | #include <sysdev/fsl_soc.h> |
25 | ||
ca632f55 | 26 | #include "spi-fsl-lib.h" |
8b60d6c2 MH |
27 | |
28 | /* eSPI Controller registers */ | |
29 | struct fsl_espi_reg { | |
30 | __be32 mode; /* 0x000 - eSPI mode register */ | |
31 | __be32 event; /* 0x004 - eSPI event register */ | |
32 | __be32 mask; /* 0x008 - eSPI mask register */ | |
33 | __be32 command; /* 0x00c - eSPI command register */ | |
34 | __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/ | |
35 | __be32 receive; /* 0x014 - eSPI receive FIFO access register*/ | |
36 | u8 res[8]; /* 0x018 - 0x01c reserved */ | |
37 | __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */ | |
38 | }; | |
39 | ||
40 | struct fsl_espi_transfer { | |
41 | const void *tx_buf; | |
42 | void *rx_buf; | |
43 | unsigned len; | |
8b60d6c2 MH |
44 | }; |
45 | ||
46 | /* eSPI Controller mode register definitions */ | |
47 | #define SPMODE_ENABLE (1 << 31) | |
48 | #define SPMODE_LOOP (1 << 30) | |
49 | #define SPMODE_TXTHR(x) ((x) << 8) | |
50 | #define SPMODE_RXTHR(x) ((x) << 0) | |
51 | ||
52 | /* eSPI Controller CS mode register definitions */ | |
53 | #define CSMODE_CI_INACTIVEHIGH (1 << 31) | |
54 | #define CSMODE_CP_BEGIN_EDGECLK (1 << 30) | |
55 | #define CSMODE_REV (1 << 29) | |
56 | #define CSMODE_DIV16 (1 << 28) | |
57 | #define CSMODE_PM(x) ((x) << 24) | |
58 | #define CSMODE_POL_1 (1 << 20) | |
59 | #define CSMODE_LEN(x) ((x) << 16) | |
60 | #define CSMODE_BEF(x) ((x) << 12) | |
61 | #define CSMODE_AFT(x) ((x) << 8) | |
62 | #define CSMODE_CG(x) ((x) << 3) | |
63 | ||
64 | /* Default mode/csmode for eSPI controller */ | |
65 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3)) | |
66 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ | |
67 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
68 | ||
69 | /* SPIE register values */ | |
70 | #define SPIE_NE 0x00000200 /* Not empty */ | |
71 | #define SPIE_NF 0x00000100 /* Not full */ | |
72 | ||
73 | /* SPIM register values */ | |
74 | #define SPIM_NE 0x00000200 /* Not empty */ | |
75 | #define SPIM_NF 0x00000100 /* Not full */ | |
76 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) | |
77 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
78 | ||
79 | /* SPCOM register values */ | |
80 | #define SPCOM_CS(x) ((x) << 30) | |
81 | #define SPCOM_TRANLEN(x) ((x) << 0) | |
5cfa1e4e | 82 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 83 | |
e9abb4db HK |
84 | #define AUTOSUSPEND_TIMEOUT 2000 |
85 | ||
7c159aa8 HK |
86 | static unsigned int fsl_espi_copy_to_buf(struct spi_message *m, |
87 | struct mpc8xxx_spi *mspi) | |
88 | { | |
89 | unsigned int tx_only = 0; | |
90 | struct spi_transfer *t; | |
91 | u8 *buf = mspi->local_buf; | |
92 | ||
93 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
94 | if (t->tx_buf) { | |
95 | memcpy(buf, t->tx_buf, t->len); | |
96 | if (!t->rx_buf) | |
97 | tx_only += t->len; | |
98 | } else { | |
99 | memset(buf, 0, t->len); | |
100 | } | |
101 | buf += t->len; | |
102 | } | |
103 | ||
104 | return tx_only; | |
105 | } | |
106 | ||
8b60d6c2 MH |
107 | static void fsl_espi_change_mode(struct spi_device *spi) |
108 | { | |
109 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
110 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
111 | struct fsl_espi_reg *reg_base = mspi->reg_base; | |
112 | __be32 __iomem *mode = ®_base->csmode[spi->chip_select]; | |
113 | __be32 __iomem *espi_mode = ®_base->mode; | |
114 | u32 tmp; | |
115 | unsigned long flags; | |
116 | ||
117 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
118 | local_irq_save(flags); | |
119 | ||
120 | /* Turn off SPI unit prior changing mode */ | |
121 | tmp = mpc8xxx_spi_read_reg(espi_mode); | |
122 | mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE); | |
123 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); | |
124 | mpc8xxx_spi_write_reg(espi_mode, tmp); | |
125 | ||
126 | local_irq_restore(flags); | |
127 | } | |
128 | ||
129 | static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi) | |
130 | { | |
131 | u32 data; | |
132 | u16 data_h; | |
133 | u16 data_l; | |
134 | const u32 *tx = mpc8xxx_spi->tx; | |
135 | ||
136 | if (!tx) | |
137 | return 0; | |
138 | ||
139 | data = *tx++ << mpc8xxx_spi->tx_shift; | |
140 | data_l = data & 0xffff; | |
141 | data_h = (data >> 16) & 0xffff; | |
142 | swab16s(&data_l); | |
143 | swab16s(&data_h); | |
144 | data = data_h | data_l; | |
145 | ||
146 | mpc8xxx_spi->tx = tx; | |
147 | return data; | |
148 | } | |
149 | ||
ea616ee2 | 150 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
151 | struct spi_transfer *t) |
152 | { | |
153 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
154 | int bits_per_word = 0; | |
155 | u8 pm; | |
156 | u32 hz = 0; | |
157 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
158 | ||
159 | if (t) { | |
160 | bits_per_word = t->bits_per_word; | |
161 | hz = t->speed_hz; | |
162 | } | |
163 | ||
164 | /* spi_transfer level calls that work per-word */ | |
165 | if (!bits_per_word) | |
166 | bits_per_word = spi->bits_per_word; | |
167 | ||
8b60d6c2 MH |
168 | if (!hz) |
169 | hz = spi->max_speed_hz; | |
170 | ||
171 | cs->rx_shift = 0; | |
172 | cs->tx_shift = 0; | |
173 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; | |
174 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
175 | if (bits_per_word <= 8) { | |
176 | cs->rx_shift = 8 - bits_per_word; | |
51faed69 | 177 | } else { |
8b60d6c2 MH |
178 | cs->rx_shift = 16 - bits_per_word; |
179 | if (spi->mode & SPI_LSB_FIRST) | |
180 | cs->get_tx = fsl_espi_tx_buf_lsb; | |
8b60d6c2 MH |
181 | } |
182 | ||
183 | mpc8xxx_spi->rx_shift = cs->rx_shift; | |
184 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
185 | mpc8xxx_spi->get_rx = cs->get_rx; | |
186 | mpc8xxx_spi->get_tx = cs->get_tx; | |
187 | ||
8b60d6c2 MH |
188 | /* mask out bits we are going to set */ |
189 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
190 | ||
a755af52 | 191 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 MH |
192 | |
193 | if ((mpc8xxx_spi->spibrg / hz) > 64) { | |
194 | cs->hw_mode |= CSMODE_DIV16; | |
35faa55c | 195 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); |
8b60d6c2 | 196 | |
87bf5ab8 | 197 | WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " |
8b60d6c2 | 198 | "Will use %d Hz instead.\n", dev_name(&spi->dev), |
87bf5ab8 SAS |
199 | hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1))); |
200 | if (pm > 33) | |
201 | pm = 33; | |
8b60d6c2 | 202 | } else { |
35faa55c | 203 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); |
8b60d6c2 MH |
204 | } |
205 | if (pm) | |
206 | pm--; | |
87bf5ab8 SAS |
207 | if (pm < 2) |
208 | pm = 2; | |
8b60d6c2 MH |
209 | |
210 | cs->hw_mode |= CSMODE_PM(pm); | |
211 | ||
212 | fsl_espi_change_mode(spi); | |
8b60d6c2 MH |
213 | } |
214 | ||
bbb55f6d | 215 | static void fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t, |
8b60d6c2 MH |
216 | unsigned int len) |
217 | { | |
218 | u32 word; | |
219 | struct fsl_espi_reg *reg_base = mspi->reg_base; | |
220 | ||
221 | mspi->count = len; | |
222 | ||
223 | /* enable rx ints */ | |
224 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); | |
225 | ||
226 | /* transmit word */ | |
227 | word = mspi->get_tx(mspi); | |
228 | mpc8xxx_spi_write_reg(®_base->transmit, word); | |
8b60d6c2 MH |
229 | } |
230 | ||
231 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) | |
232 | { | |
233 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
234 | struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; | |
235 | unsigned int len = t->len; | |
8b60d6c2 MH |
236 | int ret; |
237 | ||
8b60d6c2 MH |
238 | mpc8xxx_spi->len = t->len; |
239 | len = roundup(len, 4) / 4; | |
240 | ||
241 | mpc8xxx_spi->tx = t->tx_buf; | |
242 | mpc8xxx_spi->rx = t->rx_buf; | |
243 | ||
16735d02 | 244 | reinit_completion(&mpc8xxx_spi->done); |
8b60d6c2 MH |
245 | |
246 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
5cfa1e4e | 247 | if (t->len > SPCOM_TRANLEN_MAX) { |
8b60d6c2 MH |
248 | dev_err(mpc8xxx_spi->dev, "Transaction length (%d)" |
249 | " beyond the SPCOM[TRANLEN] field\n", t->len); | |
250 | return -EINVAL; | |
251 | } | |
252 | mpc8xxx_spi_write_reg(®_base->command, | |
253 | (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); | |
254 | ||
bbb55f6d | 255 | fsl_espi_cpu_bufs(mpc8xxx_spi, t, len); |
8b60d6c2 | 256 | |
aa70e567 NH |
257 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
258 | ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); | |
259 | if (ret == 0) | |
260 | dev_err(mpc8xxx_spi->dev, | |
261 | "Transaction hanging up (left %d bytes)\n", | |
262 | mpc8xxx_spi->count); | |
8b60d6c2 MH |
263 | |
264 | /* disable rx ints */ | |
265 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
266 | ||
267 | return mpc8xxx_spi->count; | |
268 | } | |
269 | ||
e33a3ade HK |
270 | static int fsl_espi_do_trans(struct spi_message *m, |
271 | struct fsl_espi_transfer *tr) | |
8b60d6c2 MH |
272 | { |
273 | struct spi_device *spi = m->spi; | |
274 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
275 | struct fsl_espi_transfer *espi_trans = tr; | |
8b60d6c2 | 276 | struct spi_transfer *t, *first, trans; |
e33a3ade | 277 | int ret = 0; |
8b60d6c2 | 278 | |
8b60d6c2 MH |
279 | memset(&trans, 0, sizeof(trans)); |
280 | ||
281 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
282 | transfer_list); | |
283 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
284 | if ((first->bits_per_word != t->bits_per_word) || | |
285 | (first->speed_hz != t->speed_hz)) { | |
f6bd03a7 JN |
286 | dev_err(mspi->dev, |
287 | "bits_per_word/speed_hz should be same for the same SPI transfer\n"); | |
e33a3ade | 288 | return -EINVAL; |
8b60d6c2 MH |
289 | } |
290 | ||
291 | trans.speed_hz = t->speed_hz; | |
292 | trans.bits_per_word = t->bits_per_word; | |
293 | trans.delay_usecs = max(first->delay_usecs, t->delay_usecs); | |
294 | } | |
295 | ||
296 | trans.len = espi_trans->len; | |
297 | trans.tx_buf = espi_trans->tx_buf; | |
298 | trans.rx_buf = espi_trans->rx_buf; | |
8b60d6c2 | 299 | |
71581a15 | 300 | fsl_espi_setup_transfer(spi, &trans); |
8b60d6c2 | 301 | |
dbd4fefb | 302 | if (trans.len) |
e33a3ade | 303 | ret = fsl_espi_bufs(spi, &trans); |
8b60d6c2 | 304 | |
e33a3ade HK |
305 | if (ret) |
306 | ret = -EMSGSIZE; | |
8b60d6c2 | 307 | |
dbd4fefb HK |
308 | if (trans.delay_usecs) |
309 | udelay(trans.delay_usecs); | |
8b60d6c2 | 310 | |
8b60d6c2 | 311 | fsl_espi_setup_transfer(spi, NULL); |
e33a3ade HK |
312 | |
313 | return ret; | |
8b60d6c2 MH |
314 | } |
315 | ||
e33a3ade HK |
316 | static int fsl_espi_cmd_trans(struct spi_message *m, |
317 | struct fsl_espi_transfer *trans, u8 *rx_buff) | |
8b60d6c2 | 318 | { |
1423877b | 319 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
8b60d6c2 | 320 | struct fsl_espi_transfer *espi_trans = trans; |
e33a3ade | 321 | int ret; |
8b60d6c2 | 322 | |
7c159aa8 | 323 | fsl_espi_copy_to_buf(m, mspi); |
8b60d6c2 | 324 | |
1423877b HK |
325 | espi_trans->tx_buf = mspi->local_buf; |
326 | espi_trans->rx_buf = mspi->local_buf; | |
e33a3ade | 327 | ret = fsl_espi_do_trans(m, espi_trans); |
8b60d6c2 | 328 | |
e33a3ade | 329 | return ret; |
8b60d6c2 MH |
330 | } |
331 | ||
e33a3ade HK |
332 | static int fsl_espi_rw_trans(struct spi_message *m, |
333 | struct fsl_espi_transfer *trans, u8 *rx_buff) | |
8b60d6c2 | 334 | { |
1423877b | 335 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
7c159aa8 | 336 | unsigned int tx_only; |
e33a3ade | 337 | int ret; |
8b60d6c2 | 338 | |
7c159aa8 | 339 | tx_only = fsl_espi_copy_to_buf(m, mspi); |
8b60d6c2 | 340 | |
1423877b HK |
341 | trans->tx_buf = mspi->local_buf; |
342 | trans->rx_buf = mspi->local_buf; | |
e33a3ade | 343 | ret = fsl_espi_do_trans(m, trans); |
8b60d6c2 | 344 | |
e33a3ade | 345 | if (!ret) { |
02a595d5 HK |
346 | /* If there is at least one RX byte then copy it to rx_buff */ |
347 | if (trans->len > tx_only) | |
348 | memcpy(rx_buff, trans->rx_buf + tx_only, | |
349 | trans->len - tx_only); | |
8b60d6c2 | 350 | } |
e33a3ade HK |
351 | |
352 | return ret; | |
8b60d6c2 MH |
353 | } |
354 | ||
c592becb HK |
355 | static int fsl_espi_do_one_msg(struct spi_master *master, |
356 | struct spi_message *m) | |
8b60d6c2 MH |
357 | { |
358 | struct spi_transfer *t; | |
359 | u8 *rx_buf = NULL; | |
2000058e | 360 | unsigned int xfer_len = 0; |
8b60d6c2 | 361 | struct fsl_espi_transfer espi_trans; |
e33a3ade | 362 | int ret; |
8b60d6c2 MH |
363 | |
364 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
daae020c | 365 | if (t->rx_buf) |
8b60d6c2 | 366 | rx_buf = t->rx_buf; |
2000058e JR |
367 | if ((t->tx_buf) || (t->rx_buf)) |
368 | xfer_len += t->len; | |
8b60d6c2 MH |
369 | } |
370 | ||
2000058e | 371 | espi_trans.len = xfer_len; |
8b60d6c2 MH |
372 | |
373 | if (!rx_buf) | |
e33a3ade | 374 | ret = fsl_espi_cmd_trans(m, &espi_trans, NULL); |
8b60d6c2 | 375 | else |
e33a3ade | 376 | ret = fsl_espi_rw_trans(m, &espi_trans, rx_buf); |
8b60d6c2 | 377 | |
5cd7b8be HK |
378 | m->actual_length = ret ? 0 : espi_trans.len; |
379 | ||
0319d499 HK |
380 | if (m->status == -EINPROGRESS) |
381 | m->status = ret; | |
382 | ||
c592becb | 383 | spi_finalize_current_message(master); |
0319d499 HK |
384 | |
385 | return ret; | |
8b60d6c2 MH |
386 | } |
387 | ||
388 | static int fsl_espi_setup(struct spi_device *spi) | |
389 | { | |
390 | struct mpc8xxx_spi *mpc8xxx_spi; | |
391 | struct fsl_espi_reg *reg_base; | |
8b60d6c2 MH |
392 | u32 hw_mode; |
393 | u32 loop_mode; | |
d9f26748 | 394 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 MH |
395 | |
396 | if (!spi->max_speed_hz) | |
397 | return -EINVAL; | |
398 | ||
399 | if (!cs) { | |
d9f26748 | 400 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
401 | if (!cs) |
402 | return -ENOMEM; | |
d9f26748 | 403 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
404 | } |
405 | ||
406 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
407 | reg_base = mpc8xxx_spi->reg_base; | |
408 | ||
e9abb4db HK |
409 | pm_runtime_get_sync(mpc8xxx_spi->dev); |
410 | ||
25985edc | 411 | hw_mode = cs->hw_mode; /* Save original settings */ |
8b60d6c2 MH |
412 | cs->hw_mode = mpc8xxx_spi_read_reg( |
413 | ®_base->csmode[spi->chip_select]); | |
414 | /* mask out bits we are going to set */ | |
415 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
416 | | CSMODE_REV); | |
417 | ||
418 | if (spi->mode & SPI_CPHA) | |
419 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
420 | if (spi->mode & SPI_CPOL) | |
421 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
422 | if (!(spi->mode & SPI_LSB_FIRST)) | |
423 | cs->hw_mode |= CSMODE_REV; | |
424 | ||
425 | /* Handle the loop mode */ | |
426 | loop_mode = mpc8xxx_spi_read_reg(®_base->mode); | |
427 | loop_mode &= ~SPMODE_LOOP; | |
428 | if (spi->mode & SPI_LOOP) | |
429 | loop_mode |= SPMODE_LOOP; | |
430 | mpc8xxx_spi_write_reg(®_base->mode, loop_mode); | |
431 | ||
ea616ee2 | 432 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db HK |
433 | |
434 | pm_runtime_mark_last_busy(mpc8xxx_spi->dev); | |
435 | pm_runtime_put_autosuspend(mpc8xxx_spi->dev); | |
436 | ||
8b60d6c2 MH |
437 | return 0; |
438 | } | |
439 | ||
d9f26748 AL |
440 | static void fsl_espi_cleanup(struct spi_device *spi) |
441 | { | |
442 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); | |
443 | ||
444 | kfree(cs); | |
445 | spi_set_ctldata(spi, NULL); | |
446 | } | |
447 | ||
10ed1e6d | 448 | static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
8b60d6c2 MH |
449 | { |
450 | struct fsl_espi_reg *reg_base = mspi->reg_base; | |
451 | ||
452 | /* We need handle RX first */ | |
453 | if (events & SPIE_NE) { | |
e6289d63 MH |
454 | u32 rx_data, tmp; |
455 | u8 rx_data_8; | |
6319a680 | 456 | int rx_nr_bytes = 4; |
a12ddd60 | 457 | int ret; |
8b60d6c2 MH |
458 | |
459 | /* Spin until RX is done */ | |
a12ddd60 NH |
460 | if (SPIE_RXCNT(events) < min(4, mspi->len)) { |
461 | ret = spin_event_timeout( | |
462 | !(SPIE_RXCNT(events = | |
463 | mpc8xxx_spi_read_reg(®_base->event)) < | |
464 | min(4, mspi->len)), | |
465 | 10000, 0); /* 10 msec */ | |
466 | if (!ret) | |
467 | dev_err(mspi->dev, | |
468 | "tired waiting for SPIE_RXCNT\n"); | |
8b60d6c2 | 469 | } |
8b60d6c2 | 470 | |
e6289d63 MH |
471 | if (mspi->len >= 4) { |
472 | rx_data = mpc8xxx_spi_read_reg(®_base->receive); | |
6319a680 NH |
473 | } else if (mspi->len <= 0) { |
474 | dev_err(mspi->dev, | |
475 | "unexpected RX(SPIE_NE) interrupt occurred,\n" | |
476 | "(local rxlen %d bytes, reg rxlen %d bytes)\n", | |
477 | min(4, mspi->len), SPIE_RXCNT(events)); | |
478 | rx_nr_bytes = 0; | |
e6289d63 | 479 | } else { |
6319a680 | 480 | rx_nr_bytes = mspi->len; |
e6289d63 MH |
481 | tmp = mspi->len; |
482 | rx_data = 0; | |
483 | while (tmp--) { | |
484 | rx_data_8 = in_8((u8 *)®_base->receive); | |
485 | rx_data |= (rx_data_8 << (tmp * 8)); | |
486 | } | |
487 | ||
488 | rx_data <<= (4 - mspi->len) * 8; | |
489 | } | |
490 | ||
6319a680 | 491 | mspi->len -= rx_nr_bytes; |
8b60d6c2 MH |
492 | |
493 | if (mspi->rx) | |
494 | mspi->get_rx(rx_data, mspi); | |
495 | } | |
496 | ||
497 | if (!(events & SPIE_NF)) { | |
498 | int ret; | |
499 | ||
500 | /* spin until TX is done */ | |
501 | ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg( | |
7a0a1759 | 502 | ®_base->event)) & SPIE_NF), 1000, 0); |
8b60d6c2 MH |
503 | if (!ret) { |
504 | dev_err(mspi->dev, "tired waiting for SPIE_NF\n"); | |
7a0a1759 JW |
505 | |
506 | /* Clear the SPIE bits */ | |
507 | mpc8xxx_spi_write_reg(®_base->event, events); | |
508 | complete(&mspi->done); | |
8b60d6c2 MH |
509 | return; |
510 | } | |
511 | } | |
512 | ||
513 | /* Clear the events */ | |
514 | mpc8xxx_spi_write_reg(®_base->event, events); | |
515 | ||
516 | mspi->count -= 1; | |
517 | if (mspi->count) { | |
518 | u32 word = mspi->get_tx(mspi); | |
519 | ||
520 | mpc8xxx_spi_write_reg(®_base->transmit, word); | |
521 | } else { | |
522 | complete(&mspi->done); | |
523 | } | |
524 | } | |
525 | ||
526 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
527 | { | |
528 | struct mpc8xxx_spi *mspi = context_data; | |
529 | struct fsl_espi_reg *reg_base = mspi->reg_base; | |
530 | irqreturn_t ret = IRQ_NONE; | |
531 | u32 events; | |
532 | ||
533 | /* Get interrupt events(tx/rx) */ | |
534 | events = mpc8xxx_spi_read_reg(®_base->event); | |
535 | if (events) | |
536 | ret = IRQ_HANDLED; | |
537 | ||
538 | dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); | |
539 | ||
540 | fsl_espi_cpu_irq(mspi, events); | |
541 | ||
542 | return ret; | |
543 | } | |
544 | ||
e9abb4db HK |
545 | #ifdef CONFIG_PM |
546 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 547 | { |
e9abb4db HK |
548 | struct spi_master *master = dev_get_drvdata(dev); |
549 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
550 | struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; | |
75506d0e HK |
551 | u32 regval; |
552 | ||
75506d0e HK |
553 | regval = mpc8xxx_spi_read_reg(®_base->mode); |
554 | regval &= ~SPMODE_ENABLE; | |
555 | mpc8xxx_spi_write_reg(®_base->mode, regval); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
e9abb4db | 560 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 561 | { |
e9abb4db HK |
562 | struct spi_master *master = dev_get_drvdata(dev); |
563 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
564 | struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; | |
75506d0e HK |
565 | u32 regval; |
566 | ||
75506d0e HK |
567 | regval = mpc8xxx_spi_read_reg(®_base->mode); |
568 | regval |= SPMODE_ENABLE; | |
569 | mpc8xxx_spi_write_reg(®_base->mode, regval); | |
570 | ||
571 | return 0; | |
572 | } | |
e9abb4db | 573 | #endif |
75506d0e | 574 | |
02a595d5 | 575 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
576 | { |
577 | return SPCOM_TRANLEN_MAX; | |
578 | } | |
579 | ||
fd4a319b | 580 | static struct spi_master * fsl_espi_probe(struct device *dev, |
8b60d6c2 MH |
581 | struct resource *mem, unsigned int irq) |
582 | { | |
8074cf06 | 583 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
584 | struct spi_master *master; |
585 | struct mpc8xxx_spi *mpc8xxx_spi; | |
586 | struct fsl_espi_reg *reg_base; | |
d0fb47a5 JW |
587 | struct device_node *nc; |
588 | const __be32 *prop; | |
589 | u32 regval, csmode; | |
590 | int i, len, ret = 0; | |
8b60d6c2 MH |
591 | |
592 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); | |
593 | if (!master) { | |
594 | ret = -ENOMEM; | |
595 | goto err; | |
596 | } | |
597 | ||
598 | dev_set_drvdata(dev, master); | |
599 | ||
c592becb | 600 | mpc8xxx_spi_probe(dev, mem, irq); |
8b60d6c2 | 601 | |
24778be2 | 602 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 603 | master->setup = fsl_espi_setup; |
d9f26748 | 604 | master->cleanup = fsl_espi_cleanup; |
c592becb | 605 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 606 | master->auto_runtime_pm = true; |
02a595d5 | 607 | master->max_message_size = fsl_espi_max_message_size; |
8b60d6c2 MH |
608 | |
609 | mpc8xxx_spi = spi_master_get_devdata(master); | |
8b60d6c2 | 610 | |
1423877b HK |
611 | mpc8xxx_spi->local_buf = |
612 | devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL); | |
613 | if (!mpc8xxx_spi->local_buf) { | |
614 | ret = -ENOMEM; | |
615 | goto err_probe; | |
616 | } | |
617 | ||
4178b6b1 | 618 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
619 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
620 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
8b60d6c2 MH |
621 | goto err_probe; |
622 | } | |
623 | ||
624 | reg_base = mpc8xxx_spi->reg_base; | |
625 | ||
626 | /* Register for SPI Interrupt */ | |
4178b6b1 | 627 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq, |
8b60d6c2 MH |
628 | 0, "fsl_espi", mpc8xxx_spi); |
629 | if (ret) | |
4178b6b1 | 630 | goto err_probe; |
8b60d6c2 MH |
631 | |
632 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { | |
633 | mpc8xxx_spi->rx_shift = 16; | |
634 | mpc8xxx_spi->tx_shift = 24; | |
635 | } | |
636 | ||
637 | /* SPI controller initializations */ | |
638 | mpc8xxx_spi_write_reg(®_base->mode, 0); | |
639 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
640 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
641 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
642 | ||
643 | /* Init eSPI CS mode register */ | |
d0fb47a5 JW |
644 | for_each_available_child_of_node(master->dev.of_node, nc) { |
645 | /* get chip select */ | |
646 | prop = of_get_property(nc, "reg", &len); | |
647 | if (!prop || len < sizeof(*prop)) | |
648 | continue; | |
649 | i = be32_to_cpup(prop); | |
650 | if (i < 0 || i >= pdata->max_chipselect) | |
651 | continue; | |
652 | ||
653 | csmode = CSMODE_INIT_VAL; | |
654 | /* check if CSBEF is set in device tree */ | |
655 | prop = of_get_property(nc, "fsl,csbef", &len); | |
656 | if (prop && len >= sizeof(*prop)) { | |
657 | csmode &= ~(CSMODE_BEF(0xf)); | |
658 | csmode |= CSMODE_BEF(be32_to_cpup(prop)); | |
659 | } | |
660 | /* check if CSAFT is set in device tree */ | |
661 | prop = of_get_property(nc, "fsl,csaft", &len); | |
662 | if (prop && len >= sizeof(*prop)) { | |
663 | csmode &= ~(CSMODE_AFT(0xf)); | |
664 | csmode |= CSMODE_AFT(be32_to_cpup(prop)); | |
665 | } | |
666 | mpc8xxx_spi_write_reg(®_base->csmode[i], csmode); | |
667 | ||
668 | dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode); | |
669 | } | |
8b60d6c2 MH |
670 | |
671 | /* Enable SPI interface */ | |
672 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
673 | ||
674 | mpc8xxx_spi_write_reg(®_base->mode, regval); | |
675 | ||
e9abb4db HK |
676 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
677 | pm_runtime_use_autosuspend(dev); | |
678 | pm_runtime_set_active(dev); | |
679 | pm_runtime_enable(dev); | |
680 | pm_runtime_get_sync(dev); | |
681 | ||
4178b6b1 | 682 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 683 | if (ret < 0) |
e9abb4db | 684 | goto err_pm; |
8b60d6c2 MH |
685 | |
686 | dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq); | |
687 | ||
e9abb4db HK |
688 | pm_runtime_mark_last_busy(dev); |
689 | pm_runtime_put_autosuspend(dev); | |
690 | ||
8b60d6c2 MH |
691 | return master; |
692 | ||
e9abb4db HK |
693 | err_pm: |
694 | pm_runtime_put_noidle(dev); | |
695 | pm_runtime_disable(dev); | |
696 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
697 | err_probe: |
698 | spi_master_put(master); | |
699 | err: | |
700 | return ERR_PTR(ret); | |
701 | } | |
702 | ||
703 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
704 | { | |
705 | struct device_node *np = dev->of_node; | |
8074cf06 | 706 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
707 | const u32 *prop; |
708 | int len; | |
709 | ||
710 | prop = of_get_property(np, "fsl,espi-num-chipselects", &len); | |
711 | if (!prop || len < sizeof(*prop)) { | |
712 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); | |
713 | return -EINVAL; | |
714 | } | |
715 | ||
716 | pdata->max_chipselect = *prop; | |
717 | pdata->cs_control = NULL; | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
fd4a319b | 722 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
723 | { |
724 | struct device *dev = &ofdev->dev; | |
725 | struct device_node *np = ofdev->dev.of_node; | |
726 | struct spi_master *master; | |
727 | struct resource mem; | |
f7578496 | 728 | unsigned int irq; |
8b60d6c2 MH |
729 | int ret = -ENOMEM; |
730 | ||
18d306d1 | 731 | ret = of_mpc8xxx_spi_probe(ofdev); |
8b60d6c2 MH |
732 | if (ret) |
733 | return ret; | |
734 | ||
735 | ret = of_fsl_espi_get_chipselects(dev); | |
736 | if (ret) | |
737 | goto err; | |
738 | ||
739 | ret = of_address_to_resource(np, 0, &mem); | |
740 | if (ret) | |
741 | goto err; | |
742 | ||
f7578496 | 743 | irq = irq_of_parse_and_map(np, 0); |
7227cd18 | 744 | if (!irq) { |
8b60d6c2 MH |
745 | ret = -EINVAL; |
746 | goto err; | |
747 | } | |
748 | ||
f7578496 | 749 | master = fsl_espi_probe(dev, &mem, irq); |
8b60d6c2 MH |
750 | if (IS_ERR(master)) { |
751 | ret = PTR_ERR(master); | |
752 | goto err; | |
753 | } | |
754 | ||
755 | return 0; | |
756 | ||
757 | err: | |
758 | return ret; | |
759 | } | |
760 | ||
e9abb4db HK |
761 | static int of_fsl_espi_remove(struct platform_device *dev) |
762 | { | |
763 | pm_runtime_disable(&dev->dev); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
714bb654 HZ |
768 | #ifdef CONFIG_PM_SLEEP |
769 | static int of_fsl_espi_suspend(struct device *dev) | |
770 | { | |
771 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
772 | int ret; |
773 | ||
714bb654 HZ |
774 | ret = spi_master_suspend(master); |
775 | if (ret) { | |
776 | dev_warn(dev, "cannot suspend master\n"); | |
777 | return ret; | |
778 | } | |
779 | ||
e9abb4db HK |
780 | ret = pm_runtime_force_suspend(dev); |
781 | if (ret < 0) | |
782 | return ret; | |
783 | ||
784 | return 0; | |
714bb654 HZ |
785 | } |
786 | ||
787 | static int of_fsl_espi_resume(struct device *dev) | |
788 | { | |
789 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); | |
790 | struct spi_master *master = dev_get_drvdata(dev); | |
791 | struct mpc8xxx_spi *mpc8xxx_spi; | |
792 | struct fsl_espi_reg *reg_base; | |
793 | u32 regval; | |
e9abb4db | 794 | int i, ret; |
714bb654 HZ |
795 | |
796 | mpc8xxx_spi = spi_master_get_devdata(master); | |
797 | reg_base = mpc8xxx_spi->reg_base; | |
798 | ||
799 | /* SPI controller initializations */ | |
800 | mpc8xxx_spi_write_reg(®_base->mode, 0); | |
801 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
802 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
803 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
804 | ||
805 | /* Init eSPI CS mode register */ | |
806 | for (i = 0; i < pdata->max_chipselect; i++) | |
807 | mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL); | |
808 | ||
809 | /* Enable SPI interface */ | |
810 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
811 | ||
812 | mpc8xxx_spi_write_reg(®_base->mode, regval); | |
813 | ||
e9abb4db HK |
814 | ret = pm_runtime_force_resume(dev); |
815 | if (ret < 0) | |
816 | return ret; | |
817 | ||
714bb654 HZ |
818 | return spi_master_resume(master); |
819 | } | |
820 | #endif /* CONFIG_PM_SLEEP */ | |
821 | ||
822 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
823 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
824 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
825 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
826 | }; | |
827 | ||
8b60d6c2 MH |
828 | static const struct of_device_id of_fsl_espi_match[] = { |
829 | { .compatible = "fsl,mpc8536-espi" }, | |
830 | {} | |
831 | }; | |
832 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
833 | ||
18d306d1 | 834 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
835 | .driver = { |
836 | .name = "fsl_espi", | |
8b60d6c2 | 837 | .of_match_table = of_fsl_espi_match, |
714bb654 | 838 | .pm = &espi_pm, |
8b60d6c2 MH |
839 | }, |
840 | .probe = of_fsl_espi_probe, | |
e9abb4db | 841 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 842 | }; |
940ab889 | 843 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
844 | |
845 | MODULE_AUTHOR("Mingkai Hu"); | |
846 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
847 | MODULE_LICENSE("GPL"); |