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b36ece83 MH |
1 | /* |
2 | * Freescale SPI/eSPI controller driver library. | |
3 | * | |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
7 | * | |
8 | * CPM SPI and QE buffer descriptors mode support: | |
9 | * Copyright (c) 2009 MontaVista Software, Inc. | |
10 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
11 | * | |
12 | * Copyright 2010 Freescale Semiconductor, Inc. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms of the GNU General Public License as published by the | |
16 | * Free Software Foundation; either version 2 of the License, or (at your | |
17 | * option) any later version. | |
18 | */ | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/fsl_devices.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/of_platform.h> | |
d57a4282 | 25 | #include <linux/spi/spi.h> |
e8beacbb | 26 | #ifdef CONFIG_FSL_SOC |
b36ece83 | 27 | #include <sysdev/fsl_soc.h> |
e8beacbb | 28 | #endif |
b36ece83 | 29 | |
ca632f55 | 30 | #include "spi-fsl-lib.h" |
b36ece83 MH |
31 | |
32 | #define MPC8XXX_SPI_RX_BUF(type) \ | |
33 | void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \ | |
34 | { \ | |
35 | type *rx = mpc8xxx_spi->rx; \ | |
36 | *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \ | |
37 | mpc8xxx_spi->rx = rx; \ | |
38 | } | |
39 | ||
40 | #define MPC8XXX_SPI_TX_BUF(type) \ | |
41 | u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \ | |
42 | { \ | |
43 | u32 data; \ | |
44 | const type *tx = mpc8xxx_spi->tx; \ | |
45 | if (!tx) \ | |
46 | return 0; \ | |
47 | data = *tx++ << mpc8xxx_spi->tx_shift; \ | |
48 | mpc8xxx_spi->tx = tx; \ | |
49 | return data; \ | |
50 | } | |
51 | ||
52 | MPC8XXX_SPI_RX_BUF(u8) | |
53 | MPC8XXX_SPI_RX_BUF(u16) | |
54 | MPC8XXX_SPI_RX_BUF(u32) | |
55 | MPC8XXX_SPI_TX_BUF(u8) | |
56 | MPC8XXX_SPI_TX_BUF(u16) | |
57 | MPC8XXX_SPI_TX_BUF(u32) | |
58 | ||
59 | struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata) | |
60 | { | |
61 | return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata); | |
62 | } | |
63 | ||
d0864323 | 64 | static void mpc8xxx_spi_work(struct work_struct *work) |
b36ece83 MH |
65 | { |
66 | struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi, | |
67 | work); | |
68 | ||
69 | spin_lock_irq(&mpc8xxx_spi->lock); | |
70 | while (!list_empty(&mpc8xxx_spi->queue)) { | |
71 | struct spi_message *m = container_of(mpc8xxx_spi->queue.next, | |
72 | struct spi_message, queue); | |
73 | ||
74 | list_del_init(&m->queue); | |
75 | spin_unlock_irq(&mpc8xxx_spi->lock); | |
76 | ||
77 | if (mpc8xxx_spi->spi_do_one_msg) | |
78 | mpc8xxx_spi->spi_do_one_msg(m); | |
79 | ||
80 | spin_lock_irq(&mpc8xxx_spi->lock); | |
81 | } | |
82 | spin_unlock_irq(&mpc8xxx_spi->lock); | |
83 | } | |
84 | ||
85 | int mpc8xxx_spi_transfer(struct spi_device *spi, | |
86 | struct spi_message *m) | |
87 | { | |
88 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
89 | unsigned long flags; | |
90 | ||
91 | m->actual_length = 0; | |
92 | m->status = -EINPROGRESS; | |
93 | ||
94 | spin_lock_irqsave(&mpc8xxx_spi->lock, flags); | |
95 | list_add_tail(&m->queue, &mpc8xxx_spi->queue); | |
96 | queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work); | |
97 | spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags); | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
b36ece83 MH |
102 | const char *mpc8xxx_spi_strmode(unsigned int flags) |
103 | { | |
104 | if (flags & SPI_QE_CPU_MODE) { | |
105 | return "QE CPU"; | |
106 | } else if (flags & SPI_CPM_MODE) { | |
107 | if (flags & SPI_QE) | |
108 | return "QE"; | |
109 | else if (flags & SPI_CPM2) | |
110 | return "CPM2"; | |
111 | else | |
112 | return "CPM1"; | |
113 | } | |
114 | return "CPU"; | |
115 | } | |
116 | ||
117 | int mpc8xxx_spi_probe(struct device *dev, struct resource *mem, | |
118 | unsigned int irq) | |
119 | { | |
8074cf06 | 120 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
b36ece83 MH |
121 | struct spi_master *master; |
122 | struct mpc8xxx_spi *mpc8xxx_spi; | |
123 | int ret = 0; | |
124 | ||
125 | master = dev_get_drvdata(dev); | |
126 | ||
127 | /* the spi->mode bits understood by this driver: */ | |
128 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | |
129 | | SPI_LSB_FIRST | SPI_LOOP; | |
130 | ||
131 | master->transfer = mpc8xxx_spi_transfer; | |
b36ece83 MH |
132 | master->dev.of_node = dev->of_node; |
133 | ||
134 | mpc8xxx_spi = spi_master_get_devdata(master); | |
135 | mpc8xxx_spi->dev = dev; | |
136 | mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8; | |
137 | mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8; | |
138 | mpc8xxx_spi->flags = pdata->flags; | |
139 | mpc8xxx_spi->spibrg = pdata->sysclk; | |
140 | mpc8xxx_spi->irq = irq; | |
141 | ||
142 | mpc8xxx_spi->rx_shift = 0; | |
143 | mpc8xxx_spi->tx_shift = 0; | |
144 | ||
145 | init_completion(&mpc8xxx_spi->done); | |
146 | ||
147 | master->bus_num = pdata->bus_num; | |
148 | master->num_chipselect = pdata->max_chipselect; | |
149 | ||
150 | spin_lock_init(&mpc8xxx_spi->lock); | |
151 | init_completion(&mpc8xxx_spi->done); | |
152 | INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work); | |
153 | INIT_LIST_HEAD(&mpc8xxx_spi->queue); | |
154 | ||
155 | mpc8xxx_spi->workqueue = create_singlethread_workqueue( | |
156 | dev_name(master->dev.parent)); | |
157 | if (mpc8xxx_spi->workqueue == NULL) { | |
158 | ret = -EBUSY; | |
159 | goto err; | |
160 | } | |
161 | ||
162 | return 0; | |
163 | ||
164 | err: | |
165 | return ret; | |
166 | } | |
167 | ||
fd4a319b | 168 | int mpc8xxx_spi_remove(struct device *dev) |
b36ece83 MH |
169 | { |
170 | struct mpc8xxx_spi *mpc8xxx_spi; | |
171 | struct spi_master *master; | |
172 | ||
173 | master = dev_get_drvdata(dev); | |
174 | mpc8xxx_spi = spi_master_get_devdata(master); | |
175 | ||
176 | flush_workqueue(mpc8xxx_spi->workqueue); | |
177 | destroy_workqueue(mpc8xxx_spi->workqueue); | |
178 | spi_unregister_master(master); | |
179 | ||
180 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); | |
181 | ||
182 | if (mpc8xxx_spi->spi_remove) | |
183 | mpc8xxx_spi->spi_remove(mpc8xxx_spi); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
fd4a319b | 188 | int of_mpc8xxx_spi_probe(struct platform_device *ofdev) |
b36ece83 MH |
189 | { |
190 | struct device *dev = &ofdev->dev; | |
191 | struct device_node *np = ofdev->dev.of_node; | |
192 | struct mpc8xxx_spi_probe_info *pinfo; | |
193 | struct fsl_spi_platform_data *pdata; | |
194 | const void *prop; | |
195 | int ret = -ENOMEM; | |
196 | ||
7282326b | 197 | pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL); |
b36ece83 | 198 | if (!pinfo) |
ef4bbdec | 199 | return ret; |
b36ece83 MH |
200 | |
201 | pdata = &pinfo->pdata; | |
202 | dev->platform_data = pdata; | |
203 | ||
204 | /* Allocate bus num dynamically. */ | |
205 | pdata->bus_num = -1; | |
206 | ||
e8beacbb | 207 | #ifdef CONFIG_FSL_SOC |
b36ece83 MH |
208 | /* SPI controller is either clocked from QE or SoC clock. */ |
209 | pdata->sysclk = get_brgfreq(); | |
210 | if (pdata->sysclk == -1) { | |
211 | pdata->sysclk = fsl_get_sys_freq(); | |
7282326b AL |
212 | if (pdata->sysclk == -1) |
213 | return -ENODEV; | |
b36ece83 | 214 | } |
e8beacbb AL |
215 | #else |
216 | ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk); | |
217 | if (ret) | |
7282326b | 218 | return ret; |
e8beacbb | 219 | #endif |
b36ece83 MH |
220 | |
221 | prop = of_get_property(np, "mode", NULL); | |
222 | if (prop && !strcmp(prop, "cpu-qe")) | |
223 | pdata->flags = SPI_QE_CPU_MODE; | |
224 | else if (prop && !strcmp(prop, "qe")) | |
225 | pdata->flags = SPI_CPM_MODE | SPI_QE; | |
226 | else if (of_device_is_compatible(np, "fsl,cpm2-spi")) | |
227 | pdata->flags = SPI_CPM_MODE | SPI_CPM2; | |
228 | else if (of_device_is_compatible(np, "fsl,cpm1-spi")) | |
229 | pdata->flags = SPI_CPM_MODE | SPI_CPM1; | |
230 | ||
231 | return 0; | |
b36ece83 | 232 | } |