Commit | Line | Data |
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b5f3294f SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright (C) 2008 Juergen Beisert | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the | |
16 | * Free Software Foundation | |
17 | * 51 Franklin Street, Fifth Floor | |
18 | * Boston, MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/completion.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/gpio.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/platform_device.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
b5f3294f SH |
34 | #include <linux/spi/spi.h> |
35 | #include <linux/spi/spi_bitbang.h> | |
36 | #include <linux/types.h> | |
37 | ||
38 | #include <mach/spi.h> | |
39 | ||
40 | #define DRIVER_NAME "spi_imx" | |
41 | ||
42 | #define MXC_CSPIRXDATA 0x00 | |
43 | #define MXC_CSPITXDATA 0x04 | |
44 | #define MXC_CSPICTRL 0x08 | |
45 | #define MXC_CSPIINT 0x0c | |
46 | #define MXC_RESET 0x1c | |
47 | ||
48 | /* generic defines to abstract from the different register layouts */ | |
49 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
50 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
51 | ||
6cdeb002 | 52 | struct spi_imx_config { |
b5f3294f SH |
53 | unsigned int speed_hz; |
54 | unsigned int bpw; | |
55 | unsigned int mode; | |
3b2aa89e | 56 | u8 cs; |
b5f3294f SH |
57 | }; |
58 | ||
f4ba6315 | 59 | enum spi_imx_devtype { |
04ee5854 SG |
60 | IMX1_CSPI, |
61 | IMX21_CSPI, | |
62 | IMX27_CSPI, | |
63 | IMX31_CSPI, | |
64 | IMX35_CSPI, /* CSPI on all i.mx except above */ | |
65 | IMX51_ECSPI, /* ECSPI on i.mx51 and later */ | |
f4ba6315 UKK |
66 | }; |
67 | ||
68 | struct spi_imx_data; | |
69 | ||
70 | struct spi_imx_devtype_data { | |
71 | void (*intctrl)(struct spi_imx_data *, int); | |
72 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); | |
73 | void (*trigger)(struct spi_imx_data *); | |
74 | int (*rx_available)(struct spi_imx_data *); | |
1723e66b | 75 | void (*reset)(struct spi_imx_data *); |
04ee5854 | 76 | enum spi_imx_devtype devtype; |
f4ba6315 UKK |
77 | }; |
78 | ||
6cdeb002 | 79 | struct spi_imx_data { |
b5f3294f SH |
80 | struct spi_bitbang bitbang; |
81 | ||
82 | struct completion xfer_done; | |
83 | void *base; | |
84 | int irq; | |
85 | struct clk *clk; | |
86 | unsigned long spi_clk; | |
87 | int *chipselect; | |
88 | ||
89 | unsigned int count; | |
6cdeb002 UKK |
90 | void (*tx)(struct spi_imx_data *); |
91 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
92 | void *rx_buf; |
93 | const void *tx_buf; | |
94 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
95 | ||
edd501bb | 96 | struct spi_imx_devtype_data *devtype_data; |
b5f3294f SH |
97 | }; |
98 | ||
04ee5854 SG |
99 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
100 | { | |
101 | return d->devtype_data->devtype == IMX27_CSPI; | |
102 | } | |
103 | ||
104 | static inline int is_imx35_cspi(struct spi_imx_data *d) | |
105 | { | |
106 | return d->devtype_data->devtype == IMX35_CSPI; | |
107 | } | |
108 | ||
109 | static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) | |
110 | { | |
111 | return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8; | |
112 | } | |
113 | ||
b5f3294f | 114 | #define MXC_SPI_BUF_RX(type) \ |
6cdeb002 | 115 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 116 | { \ |
6cdeb002 | 117 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 118 | \ |
6cdeb002 UKK |
119 | if (spi_imx->rx_buf) { \ |
120 | *(type *)spi_imx->rx_buf = val; \ | |
121 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f SH |
122 | } \ |
123 | } | |
124 | ||
125 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 126 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
127 | { \ |
128 | type val = 0; \ | |
129 | \ | |
6cdeb002 UKK |
130 | if (spi_imx->tx_buf) { \ |
131 | val = *(type *)spi_imx->tx_buf; \ | |
132 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
133 | } \ |
134 | \ | |
6cdeb002 | 135 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 136 | \ |
6cdeb002 | 137 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
138 | } |
139 | ||
140 | MXC_SPI_BUF_RX(u8) | |
141 | MXC_SPI_BUF_TX(u8) | |
142 | MXC_SPI_BUF_RX(u16) | |
143 | MXC_SPI_BUF_TX(u16) | |
144 | MXC_SPI_BUF_RX(u32) | |
145 | MXC_SPI_BUF_TX(u32) | |
146 | ||
147 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
148 | * (which is currently not the case in this driver) | |
149 | */ | |
150 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
151 | 256, 384, 512, 768, 1024}; | |
152 | ||
153 | /* MX21, MX27 */ | |
6cdeb002 | 154 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
04ee5854 | 155 | unsigned int fspi, unsigned int max) |
b5f3294f | 156 | { |
04ee5854 | 157 | int i; |
b5f3294f SH |
158 | |
159 | for (i = 2; i < max; i++) | |
160 | if (fspi * mxc_clkdivs[i] >= fin) | |
161 | return i; | |
162 | ||
163 | return max; | |
164 | } | |
165 | ||
0b599603 | 166 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 167 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
b5f3294f SH |
168 | unsigned int fspi) |
169 | { | |
170 | int i, div = 4; | |
171 | ||
172 | for (i = 0; i < 7; i++) { | |
173 | if (fspi * div >= fin) | |
174 | return i; | |
175 | div <<= 1; | |
176 | } | |
177 | ||
178 | return 7; | |
179 | } | |
180 | ||
66de757c SG |
181 | #define MX51_ECSPI_CTRL 0x08 |
182 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) | |
183 | #define MX51_ECSPI_CTRL_XCH (1 << 2) | |
184 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) | |
185 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 | |
186 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | |
187 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) | |
188 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 | |
189 | ||
190 | #define MX51_ECSPI_CONFIG 0x0c | |
191 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | |
192 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | |
193 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | |
194 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | |
195 | ||
196 | #define MX51_ECSPI_INT 0x10 | |
197 | #define MX51_ECSPI_INT_TEEN (1 << 0) | |
198 | #define MX51_ECSPI_INT_RREN (1 << 3) | |
199 | ||
200 | #define MX51_ECSPI_STAT 0x18 | |
201 | #define MX51_ECSPI_STAT_RR (1 << 3) | |
0b599603 UKK |
202 | |
203 | /* MX51 eCSPI */ | |
66de757c | 204 | static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi) |
0b599603 UKK |
205 | { |
206 | /* | |
207 | * there are two 4-bit dividers, the pre-divider divides by | |
208 | * $pre, the post-divider by 2^$post | |
209 | */ | |
210 | unsigned int pre, post; | |
211 | ||
212 | if (unlikely(fspi > fin)) | |
213 | return 0; | |
214 | ||
215 | post = fls(fin) - fls(fspi); | |
216 | if (fin > fspi << post) | |
217 | post++; | |
218 | ||
219 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
220 | ||
221 | post = max(4U, post) - 4; | |
222 | if (unlikely(post > 0xf)) { | |
223 | pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", | |
224 | __func__, fspi, fin); | |
225 | return 0xff; | |
226 | } | |
227 | ||
228 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
229 | ||
230 | pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", | |
231 | __func__, fin, fspi, post, pre); | |
66de757c SG |
232 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
233 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); | |
0b599603 UKK |
234 | } |
235 | ||
66de757c | 236 | static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
0b599603 UKK |
237 | { |
238 | unsigned val = 0; | |
239 | ||
240 | if (enable & MXC_INT_TE) | |
66de757c | 241 | val |= MX51_ECSPI_INT_TEEN; |
0b599603 UKK |
242 | |
243 | if (enable & MXC_INT_RR) | |
66de757c | 244 | val |= MX51_ECSPI_INT_RREN; |
0b599603 | 245 | |
66de757c | 246 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
0b599603 UKK |
247 | } |
248 | ||
66de757c | 249 | static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
0b599603 UKK |
250 | { |
251 | u32 reg; | |
252 | ||
66de757c SG |
253 | reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
254 | reg |= MX51_ECSPI_CTRL_XCH; | |
255 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); | |
0b599603 UKK |
256 | } |
257 | ||
66de757c | 258 | static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, |
0b599603 UKK |
259 | struct spi_imx_config *config) |
260 | { | |
66de757c | 261 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0; |
0b599603 | 262 | |
f020c39e SH |
263 | /* |
264 | * The hardware seems to have a race condition when changing modes. The | |
265 | * current assumption is that the selection of the channel arrives | |
266 | * earlier in the hardware than the mode bits when they are written at | |
267 | * the same time. | |
268 | * So set master mode for all channels as we do not support slave mode. | |
269 | */ | |
66de757c | 270 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; |
0b599603 UKK |
271 | |
272 | /* set clock speed */ | |
66de757c | 273 | ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz); |
0b599603 UKK |
274 | |
275 | /* set chip select to use */ | |
66de757c | 276 | ctrl |= MX51_ECSPI_CTRL_CS(config->cs); |
0b599603 | 277 | |
66de757c | 278 | ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; |
0b599603 | 279 | |
66de757c | 280 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); |
0b599603 UKK |
281 | |
282 | if (config->mode & SPI_CPHA) | |
66de757c | 283 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); |
0b599603 UKK |
284 | |
285 | if (config->mode & SPI_CPOL) | |
66de757c | 286 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); |
0b599603 UKK |
287 | |
288 | if (config->mode & SPI_CS_HIGH) | |
66de757c | 289 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); |
0b599603 | 290 | |
66de757c SG |
291 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); |
292 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); | |
0b599603 UKK |
293 | |
294 | return 0; | |
295 | } | |
296 | ||
66de757c | 297 | static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
0b599603 | 298 | { |
66de757c | 299 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
0b599603 UKK |
300 | } |
301 | ||
66de757c | 302 | static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
0b599603 UKK |
303 | { |
304 | /* drain receive buffer */ | |
66de757c | 305 | while (mx51_ecspi_rx_available(spi_imx)) |
0b599603 UKK |
306 | readl(spi_imx->base + MXC_CSPIRXDATA); |
307 | } | |
308 | ||
b5f3294f SH |
309 | #define MX31_INTREG_TEEN (1 << 0) |
310 | #define MX31_INTREG_RREN (1 << 3) | |
311 | ||
312 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
313 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
314 | #define MX31_CSPICTRL_XCH (1 << 2) | |
315 | #define MX31_CSPICTRL_POL (1 << 4) | |
316 | #define MX31_CSPICTRL_PHA (1 << 5) | |
317 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
318 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
319 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
320 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
321 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
322 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
323 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
324 | ||
325 | #define MX31_CSPISTATUS 0x14 | |
326 | #define MX31_STATUS_RR (1 << 3) | |
327 | ||
328 | /* These functions also work for the i.MX35, but be aware that | |
329 | * the i.MX35 has a slightly different register layout for bits | |
330 | * we do not use here. | |
331 | */ | |
f4ba6315 | 332 | static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
333 | { |
334 | unsigned int val = 0; | |
335 | ||
336 | if (enable & MXC_INT_TE) | |
337 | val |= MX31_INTREG_TEEN; | |
338 | if (enable & MXC_INT_RR) | |
339 | val |= MX31_INTREG_RREN; | |
340 | ||
6cdeb002 | 341 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
342 | } |
343 | ||
f4ba6315 | 344 | static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
345 | { |
346 | unsigned int reg; | |
347 | ||
6cdeb002 | 348 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 349 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 350 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
351 | } |
352 | ||
2a64a90a | 353 | static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, |
1723e66b UKK |
354 | struct spi_imx_config *config) |
355 | { | |
356 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
3b2aa89e | 357 | int cs = spi_imx->chipselect[config->cs]; |
1723e66b UKK |
358 | |
359 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << | |
360 | MX31_CSPICTRL_DR_SHIFT; | |
361 | ||
04ee5854 | 362 | if (is_imx35_cspi(spi_imx)) { |
2a64a90a SG |
363 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; |
364 | reg |= MX31_CSPICTRL_SSCTL; | |
365 | } else { | |
366 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; | |
367 | } | |
1723e66b UKK |
368 | |
369 | if (config->mode & SPI_CPHA) | |
370 | reg |= MX31_CSPICTRL_PHA; | |
371 | if (config->mode & SPI_CPOL) | |
372 | reg |= MX31_CSPICTRL_POL; | |
373 | if (config->mode & SPI_CS_HIGH) | |
374 | reg |= MX31_CSPICTRL_SSPOL; | |
3b2aa89e | 375 | if (cs < 0) |
2a64a90a | 376 | reg |= (cs + 32) << |
04ee5854 SG |
377 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
378 | MX31_CSPICTRL_CS_SHIFT); | |
1723e66b UKK |
379 | |
380 | writel(reg, spi_imx->base + MXC_CSPICTRL); | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
f4ba6315 | 385 | static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 386 | { |
6cdeb002 | 387 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
388 | } |
389 | ||
2a64a90a | 390 | static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
391 | { |
392 | /* drain receive buffer */ | |
2a64a90a | 393 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
1723e66b UKK |
394 | readl(spi_imx->base + MXC_CSPIRXDATA); |
395 | } | |
396 | ||
3451fb15 SG |
397 | #define MX21_INTREG_RR (1 << 4) |
398 | #define MX21_INTREG_TEEN (1 << 9) | |
399 | #define MX21_INTREG_RREN (1 << 13) | |
400 | ||
401 | #define MX21_CSPICTRL_POL (1 << 5) | |
402 | #define MX21_CSPICTRL_PHA (1 << 6) | |
403 | #define MX21_CSPICTRL_SSPOL (1 << 8) | |
404 | #define MX21_CSPICTRL_XCH (1 << 9) | |
405 | #define MX21_CSPICTRL_ENABLE (1 << 10) | |
406 | #define MX21_CSPICTRL_MASTER (1 << 11) | |
407 | #define MX21_CSPICTRL_DR_SHIFT 14 | |
408 | #define MX21_CSPICTRL_CS_SHIFT 19 | |
409 | ||
410 | static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) | |
b5f3294f SH |
411 | { |
412 | unsigned int val = 0; | |
413 | ||
414 | if (enable & MXC_INT_TE) | |
3451fb15 | 415 | val |= MX21_INTREG_TEEN; |
b5f3294f | 416 | if (enable & MXC_INT_RR) |
3451fb15 | 417 | val |= MX21_INTREG_RREN; |
b5f3294f | 418 | |
6cdeb002 | 419 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
420 | } |
421 | ||
3451fb15 | 422 | static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
423 | { |
424 | unsigned int reg; | |
425 | ||
6cdeb002 | 426 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
3451fb15 | 427 | reg |= MX21_CSPICTRL_XCH; |
6cdeb002 | 428 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
429 | } |
430 | ||
3451fb15 | 431 | static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 432 | struct spi_imx_config *config) |
b5f3294f | 433 | { |
3451fb15 | 434 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; |
3b2aa89e | 435 | int cs = spi_imx->chipselect[config->cs]; |
04ee5854 | 436 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
b5f3294f | 437 | |
04ee5854 | 438 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << |
3451fb15 | 439 | MX21_CSPICTRL_DR_SHIFT; |
b5f3294f SH |
440 | reg |= config->bpw - 1; |
441 | ||
442 | if (config->mode & SPI_CPHA) | |
3451fb15 | 443 | reg |= MX21_CSPICTRL_PHA; |
b5f3294f | 444 | if (config->mode & SPI_CPOL) |
3451fb15 | 445 | reg |= MX21_CSPICTRL_POL; |
b5f3294f | 446 | if (config->mode & SPI_CS_HIGH) |
3451fb15 | 447 | reg |= MX21_CSPICTRL_SSPOL; |
3b2aa89e | 448 | if (cs < 0) |
3451fb15 | 449 | reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; |
b5f3294f | 450 | |
6cdeb002 | 451 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
3451fb15 | 456 | static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 457 | { |
3451fb15 | 458 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
b5f3294f SH |
459 | } |
460 | ||
3451fb15 | 461 | static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
462 | { |
463 | writel(1, spi_imx->base + MXC_RESET); | |
464 | } | |
465 | ||
b5f3294f SH |
466 | #define MX1_INTREG_RR (1 << 3) |
467 | #define MX1_INTREG_TEEN (1 << 8) | |
468 | #define MX1_INTREG_RREN (1 << 11) | |
469 | ||
470 | #define MX1_CSPICTRL_POL (1 << 4) | |
471 | #define MX1_CSPICTRL_PHA (1 << 5) | |
472 | #define MX1_CSPICTRL_XCH (1 << 8) | |
473 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
474 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
475 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
476 | ||
f4ba6315 | 477 | static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
478 | { |
479 | unsigned int val = 0; | |
480 | ||
481 | if (enable & MXC_INT_TE) | |
482 | val |= MX1_INTREG_TEEN; | |
483 | if (enable & MXC_INT_RR) | |
484 | val |= MX1_INTREG_RREN; | |
485 | ||
6cdeb002 | 486 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
487 | } |
488 | ||
f4ba6315 | 489 | static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
490 | { |
491 | unsigned int reg; | |
492 | ||
6cdeb002 | 493 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 494 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 495 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
496 | } |
497 | ||
f4ba6315 | 498 | static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 499 | struct spi_imx_config *config) |
b5f3294f SH |
500 | { |
501 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | |
502 | ||
6cdeb002 | 503 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
504 | MX1_CSPICTRL_DR_SHIFT; |
505 | reg |= config->bpw - 1; | |
506 | ||
507 | if (config->mode & SPI_CPHA) | |
508 | reg |= MX1_CSPICTRL_PHA; | |
509 | if (config->mode & SPI_CPOL) | |
510 | reg |= MX1_CSPICTRL_POL; | |
511 | ||
6cdeb002 | 512 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
513 | |
514 | return 0; | |
515 | } | |
516 | ||
f4ba6315 | 517 | static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 518 | { |
6cdeb002 | 519 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
520 | } |
521 | ||
1723e66b UKK |
522 | static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) |
523 | { | |
524 | writel(1, spi_imx->base + MXC_RESET); | |
525 | } | |
526 | ||
04ee5854 SG |
527 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
528 | .intctrl = mx1_intctrl, | |
529 | .config = mx1_config, | |
530 | .trigger = mx1_trigger, | |
531 | .rx_available = mx1_rx_available, | |
532 | .reset = mx1_reset, | |
533 | .devtype = IMX1_CSPI, | |
534 | }; | |
535 | ||
536 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |
537 | .intctrl = mx21_intctrl, | |
538 | .config = mx21_config, | |
539 | .trigger = mx21_trigger, | |
540 | .rx_available = mx21_rx_available, | |
541 | .reset = mx21_reset, | |
542 | .devtype = IMX21_CSPI, | |
543 | }; | |
544 | ||
545 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |
546 | /* i.mx27 cspi shares the functions with i.mx21 one */ | |
547 | .intctrl = mx21_intctrl, | |
548 | .config = mx21_config, | |
549 | .trigger = mx21_trigger, | |
550 | .rx_available = mx21_rx_available, | |
551 | .reset = mx21_reset, | |
552 | .devtype = IMX27_CSPI, | |
553 | }; | |
554 | ||
555 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |
556 | .intctrl = mx31_intctrl, | |
557 | .config = mx31_config, | |
558 | .trigger = mx31_trigger, | |
559 | .rx_available = mx31_rx_available, | |
560 | .reset = mx31_reset, | |
561 | .devtype = IMX31_CSPI, | |
562 | }; | |
563 | ||
564 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |
565 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ | |
566 | .intctrl = mx31_intctrl, | |
567 | .config = mx31_config, | |
568 | .trigger = mx31_trigger, | |
569 | .rx_available = mx31_rx_available, | |
570 | .reset = mx31_reset, | |
571 | .devtype = IMX35_CSPI, | |
572 | }; | |
573 | ||
574 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |
575 | .intctrl = mx51_ecspi_intctrl, | |
576 | .config = mx51_ecspi_config, | |
577 | .trigger = mx51_ecspi_trigger, | |
578 | .rx_available = mx51_ecspi_rx_available, | |
579 | .reset = mx51_ecspi_reset, | |
580 | .devtype = IMX51_ECSPI, | |
581 | }; | |
582 | ||
583 | static struct platform_device_id spi_imx_devtype[] = { | |
584 | { | |
585 | .name = "imx1-cspi", | |
586 | .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, | |
587 | }, { | |
588 | .name = "imx21-cspi", | |
589 | .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, | |
590 | }, { | |
591 | .name = "imx27-cspi", | |
592 | .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, | |
593 | }, { | |
594 | .name = "imx31-cspi", | |
595 | .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, | |
596 | }, { | |
597 | .name = "imx35-cspi", | |
598 | .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, | |
599 | }, { | |
600 | .name = "imx51-ecspi", | |
601 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, | |
602 | }, { | |
603 | /* sentinel */ | |
604 | } | |
f4ba6315 UKK |
605 | }; |
606 | ||
6cdeb002 | 607 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 608 | { |
6cdeb002 | 609 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
6cdeb002 | 610 | int gpio = spi_imx->chipselect[spi->chip_select]; |
e6a0a8bf UKK |
611 | int active = is_active != BITBANG_CS_INACTIVE; |
612 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | |
b5f3294f | 613 | |
e6a0a8bf | 614 | if (gpio < 0) |
b5f3294f | 615 | return; |
b5f3294f | 616 | |
e6a0a8bf | 617 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
b5f3294f SH |
618 | } |
619 | ||
6cdeb002 | 620 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 621 | { |
04ee5854 | 622 | while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { |
6cdeb002 | 623 | if (!spi_imx->count) |
b5f3294f | 624 | break; |
6cdeb002 UKK |
625 | spi_imx->tx(spi_imx); |
626 | spi_imx->txfifo++; | |
b5f3294f SH |
627 | } |
628 | ||
edd501bb | 629 | spi_imx->devtype_data->trigger(spi_imx); |
b5f3294f SH |
630 | } |
631 | ||
6cdeb002 | 632 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 633 | { |
6cdeb002 | 634 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 635 | |
edd501bb | 636 | while (spi_imx->devtype_data->rx_available(spi_imx)) { |
6cdeb002 UKK |
637 | spi_imx->rx(spi_imx); |
638 | spi_imx->txfifo--; | |
b5f3294f SH |
639 | } |
640 | ||
6cdeb002 UKK |
641 | if (spi_imx->count) { |
642 | spi_imx_push(spi_imx); | |
b5f3294f SH |
643 | return IRQ_HANDLED; |
644 | } | |
645 | ||
6cdeb002 | 646 | if (spi_imx->txfifo) { |
b5f3294f SH |
647 | /* No data left to push, but still waiting for rx data, |
648 | * enable receive data available interrupt. | |
649 | */ | |
edd501bb | 650 | spi_imx->devtype_data->intctrl( |
f4ba6315 | 651 | spi_imx, MXC_INT_RR); |
b5f3294f SH |
652 | return IRQ_HANDLED; |
653 | } | |
654 | ||
edd501bb | 655 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
6cdeb002 | 656 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
657 | |
658 | return IRQ_HANDLED; | |
659 | } | |
660 | ||
6cdeb002 | 661 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
662 | struct spi_transfer *t) |
663 | { | |
6cdeb002 UKK |
664 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
665 | struct spi_imx_config config; | |
b5f3294f SH |
666 | |
667 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | |
668 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | |
669 | config.mode = spi->mode; | |
3b2aa89e | 670 | config.cs = spi->chip_select; |
b5f3294f | 671 | |
462d26b5 SH |
672 | if (!config.speed_hz) |
673 | config.speed_hz = spi->max_speed_hz; | |
674 | if (!config.bpw) | |
675 | config.bpw = spi->bits_per_word; | |
676 | if (!config.speed_hz) | |
677 | config.speed_hz = spi->max_speed_hz; | |
678 | ||
e6a0a8bf UKK |
679 | /* Initialize the functions for transfer */ |
680 | if (config.bpw <= 8) { | |
681 | spi_imx->rx = spi_imx_buf_rx_u8; | |
682 | spi_imx->tx = spi_imx_buf_tx_u8; | |
683 | } else if (config.bpw <= 16) { | |
684 | spi_imx->rx = spi_imx_buf_rx_u16; | |
685 | spi_imx->tx = spi_imx_buf_tx_u16; | |
686 | } else if (config.bpw <= 32) { | |
687 | spi_imx->rx = spi_imx_buf_rx_u32; | |
688 | spi_imx->tx = spi_imx_buf_tx_u32; | |
689 | } else | |
690 | BUG(); | |
691 | ||
edd501bb | 692 | spi_imx->devtype_data->config(spi_imx, &config); |
b5f3294f SH |
693 | |
694 | return 0; | |
695 | } | |
696 | ||
6cdeb002 | 697 | static int spi_imx_transfer(struct spi_device *spi, |
b5f3294f SH |
698 | struct spi_transfer *transfer) |
699 | { | |
6cdeb002 | 700 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 701 | |
6cdeb002 UKK |
702 | spi_imx->tx_buf = transfer->tx_buf; |
703 | spi_imx->rx_buf = transfer->rx_buf; | |
704 | spi_imx->count = transfer->len; | |
705 | spi_imx->txfifo = 0; | |
b5f3294f | 706 | |
6cdeb002 | 707 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 708 | |
6cdeb002 | 709 | spi_imx_push(spi_imx); |
b5f3294f | 710 | |
edd501bb | 711 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 712 | |
6cdeb002 | 713 | wait_for_completion(&spi_imx->xfer_done); |
b5f3294f SH |
714 | |
715 | return transfer->len; | |
716 | } | |
717 | ||
6cdeb002 | 718 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 719 | { |
6c23e5d4 SH |
720 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
721 | int gpio = spi_imx->chipselect[spi->chip_select]; | |
722 | ||
f4d4ecfe | 723 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
724 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
725 | ||
6c23e5d4 SH |
726 | if (gpio >= 0) |
727 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); | |
728 | ||
6cdeb002 | 729 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
730 | |
731 | return 0; | |
732 | } | |
733 | ||
6cdeb002 | 734 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
735 | { |
736 | } | |
737 | ||
965346e3 | 738 | static int __devinit spi_imx_probe(struct platform_device *pdev) |
b5f3294f SH |
739 | { |
740 | struct spi_imx_master *mxc_platform_info; | |
741 | struct spi_master *master; | |
6cdeb002 | 742 | struct spi_imx_data *spi_imx; |
b5f3294f SH |
743 | struct resource *res; |
744 | int i, ret; | |
745 | ||
980f3bee | 746 | mxc_platform_info = dev_get_platdata(&pdev->dev); |
b5f3294f SH |
747 | if (!mxc_platform_info) { |
748 | dev_err(&pdev->dev, "can't get the platform data\n"); | |
749 | return -EINVAL; | |
750 | } | |
751 | ||
6cdeb002 | 752 | master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); |
b5f3294f SH |
753 | if (!master) |
754 | return -ENOMEM; | |
755 | ||
756 | platform_set_drvdata(pdev, master); | |
757 | ||
758 | master->bus_num = pdev->id; | |
759 | master->num_chipselect = mxc_platform_info->num_chipselect; | |
760 | ||
6cdeb002 UKK |
761 | spi_imx = spi_master_get_devdata(master); |
762 | spi_imx->bitbang.master = spi_master_get(master); | |
763 | spi_imx->chipselect = mxc_platform_info->chipselect; | |
b5f3294f SH |
764 | |
765 | for (i = 0; i < master->num_chipselect; i++) { | |
6cdeb002 | 766 | if (spi_imx->chipselect[i] < 0) |
b5f3294f | 767 | continue; |
6cdeb002 | 768 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); |
b5f3294f | 769 | if (ret) { |
bbd050af JO |
770 | while (i > 0) { |
771 | i--; | |
6cdeb002 | 772 | if (spi_imx->chipselect[i] >= 0) |
bbd050af JO |
773 | gpio_free(spi_imx->chipselect[i]); |
774 | } | |
775 | dev_err(&pdev->dev, "can't get cs gpios\n"); | |
b5f3294f SH |
776 | goto out_master_put; |
777 | } | |
b5f3294f SH |
778 | } |
779 | ||
6cdeb002 UKK |
780 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
781 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
782 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
783 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
784 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
3910f2cf | 785 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
b5f3294f | 786 | |
6cdeb002 | 787 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 788 | |
89342174 | 789 | spi_imx->devtype_data = |
04ee5854 | 790 | (struct spi_imx_devtype_data *) pdev->id_entry->driver_data; |
f4ba6315 | 791 | |
b5f3294f SH |
792 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
793 | if (!res) { | |
794 | dev_err(&pdev->dev, "can't get platform resource\n"); | |
795 | ret = -ENOMEM; | |
796 | goto out_gpio_free; | |
797 | } | |
798 | ||
799 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { | |
800 | dev_err(&pdev->dev, "request_mem_region failed\n"); | |
801 | ret = -EBUSY; | |
802 | goto out_gpio_free; | |
803 | } | |
804 | ||
6cdeb002 UKK |
805 | spi_imx->base = ioremap(res->start, resource_size(res)); |
806 | if (!spi_imx->base) { | |
b5f3294f SH |
807 | ret = -EINVAL; |
808 | goto out_release_mem; | |
809 | } | |
810 | ||
6cdeb002 | 811 | spi_imx->irq = platform_get_irq(pdev, 0); |
73575938 | 812 | if (spi_imx->irq < 0) { |
b5f3294f SH |
813 | ret = -EINVAL; |
814 | goto out_iounmap; | |
815 | } | |
816 | ||
6cdeb002 | 817 | ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); |
b5f3294f | 818 | if (ret) { |
6cdeb002 | 819 | dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); |
b5f3294f SH |
820 | goto out_iounmap; |
821 | } | |
822 | ||
6cdeb002 UKK |
823 | spi_imx->clk = clk_get(&pdev->dev, NULL); |
824 | if (IS_ERR(spi_imx->clk)) { | |
b5f3294f | 825 | dev_err(&pdev->dev, "unable to get clock\n"); |
6cdeb002 | 826 | ret = PTR_ERR(spi_imx->clk); |
b5f3294f SH |
827 | goto out_free_irq; |
828 | } | |
829 | ||
6cdeb002 UKK |
830 | clk_enable(spi_imx->clk); |
831 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk); | |
b5f3294f | 832 | |
edd501bb | 833 | spi_imx->devtype_data->reset(spi_imx); |
ce1807b2 | 834 | |
edd501bb | 835 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
b5f3294f | 836 | |
6cdeb002 | 837 | ret = spi_bitbang_start(&spi_imx->bitbang); |
b5f3294f SH |
838 | if (ret) { |
839 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
840 | goto out_clk_put; | |
841 | } | |
842 | ||
843 | dev_info(&pdev->dev, "probed\n"); | |
844 | ||
845 | return ret; | |
846 | ||
847 | out_clk_put: | |
6cdeb002 UKK |
848 | clk_disable(spi_imx->clk); |
849 | clk_put(spi_imx->clk); | |
b5f3294f | 850 | out_free_irq: |
6cdeb002 | 851 | free_irq(spi_imx->irq, spi_imx); |
b5f3294f | 852 | out_iounmap: |
6cdeb002 | 853 | iounmap(spi_imx->base); |
b5f3294f SH |
854 | out_release_mem: |
855 | release_mem_region(res->start, resource_size(res)); | |
856 | out_gpio_free: | |
857 | for (i = 0; i < master->num_chipselect; i++) | |
6cdeb002 UKK |
858 | if (spi_imx->chipselect[i] >= 0) |
859 | gpio_free(spi_imx->chipselect[i]); | |
b5f3294f SH |
860 | out_master_put: |
861 | spi_master_put(master); | |
862 | kfree(master); | |
863 | platform_set_drvdata(pdev, NULL); | |
864 | return ret; | |
865 | } | |
866 | ||
965346e3 | 867 | static int __devexit spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
868 | { |
869 | struct spi_master *master = platform_get_drvdata(pdev); | |
870 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6cdeb002 | 871 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
b5f3294f SH |
872 | int i; |
873 | ||
6cdeb002 | 874 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 875 | |
6cdeb002 UKK |
876 | writel(0, spi_imx->base + MXC_CSPICTRL); |
877 | clk_disable(spi_imx->clk); | |
878 | clk_put(spi_imx->clk); | |
879 | free_irq(spi_imx->irq, spi_imx); | |
880 | iounmap(spi_imx->base); | |
b5f3294f SH |
881 | |
882 | for (i = 0; i < master->num_chipselect; i++) | |
6cdeb002 UKK |
883 | if (spi_imx->chipselect[i] >= 0) |
884 | gpio_free(spi_imx->chipselect[i]); | |
b5f3294f SH |
885 | |
886 | spi_master_put(master); | |
887 | ||
888 | release_mem_region(res->start, resource_size(res)); | |
889 | ||
890 | platform_set_drvdata(pdev, NULL); | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
6cdeb002 | 895 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
896 | .driver = { |
897 | .name = DRIVER_NAME, | |
898 | .owner = THIS_MODULE, | |
899 | }, | |
f4ba6315 | 900 | .id_table = spi_imx_devtype, |
6cdeb002 | 901 | .probe = spi_imx_probe, |
965346e3 | 902 | .remove = __devexit_p(spi_imx_remove), |
b5f3294f SH |
903 | }; |
904 | ||
6cdeb002 | 905 | static int __init spi_imx_init(void) |
b5f3294f | 906 | { |
6cdeb002 | 907 | return platform_driver_register(&spi_imx_driver); |
b5f3294f SH |
908 | } |
909 | ||
6cdeb002 | 910 | static void __exit spi_imx_exit(void) |
b5f3294f | 911 | { |
6cdeb002 | 912 | platform_driver_unregister(&spi_imx_driver); |
b5f3294f SH |
913 | } |
914 | ||
6cdeb002 UKK |
915 | module_init(spi_imx_init); |
916 | module_exit(spi_imx_exit); | |
b5f3294f SH |
917 | |
918 | MODULE_DESCRIPTION("SPI Master Controller driver"); | |
919 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
920 | MODULE_LICENSE("GPL"); |