Commit | Line | Data |
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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
ccdc7bf9 SO |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
ccdc7bf9 SO |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
25 | #include <linux/dmaengine.h> |
26 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
27 | #include <linux/platform_device.h> |
28 | #include <linux/err.h> | |
29 | #include <linux/clk.h> | |
30 | #include <linux/io.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
1f1a4384 | 32 | #include <linux/pm_runtime.h> |
d5a80031 BC |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
d33f473d | 35 | #include <linux/gcd.h> |
ccdc7bf9 SO |
36 | |
37 | #include <linux/spi/spi.h> | |
bc7f9bbc | 38 | #include <linux/gpio.h> |
ccdc7bf9 | 39 | |
2203747c | 40 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
41 | |
42 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
faee9b05 | 43 | #define OMAP2_MCSPI_MAX_DIVIDER 4096 |
d33f473d IS |
44 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
45 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 46 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
47 | |
48 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
49 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
50 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
51 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
52 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
53 | #define OMAP2_MCSPI_SYST 0x24 | |
54 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 55 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
56 | |
57 | /* per-channel banks, 0x14 bytes each, first is: */ | |
58 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
59 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
60 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
61 | #define OMAP2_MCSPI_TX0 0x38 | |
62 | #define OMAP2_MCSPI_RX0 0x3c | |
63 | ||
64 | /* per-register bitmasks: */ | |
d33f473d | 65 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 66 | |
7a8fa725 JH |
67 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
68 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
69 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 70 | |
7a8fa725 JH |
71 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
72 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 73 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 74 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 75 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
76 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
77 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 78 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
79 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
80 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
81 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
82 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
83 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
84 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
85 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
86 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
87 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
faee9b05 | 88 | #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) |
ccdc7bf9 | 89 | |
7a8fa725 JH |
90 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
91 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
92 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 93 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 94 | |
7a8fa725 | 95 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
faee9b05 | 96 | #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) |
ccdc7bf9 | 97 | |
7a8fa725 | 98 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
99 | |
100 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
101 | struct omap2_mcspi_dma { | |
53741ed8 RK |
102 | struct dma_chan *dma_tx; |
103 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
104 | |
105 | int dma_tx_sync_dev; | |
106 | int dma_rx_sync_dev; | |
107 | ||
108 | struct completion dma_tx_completion; | |
109 | struct completion dma_rx_completion; | |
74f3aaad MP |
110 | |
111 | char dma_rx_ch_name[14]; | |
112 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
113 | }; |
114 | ||
115 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
116 | * cache operations; better heuristics consider wordsize and bitrate. | |
117 | */ | |
8b66c134 | 118 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
119 | |
120 | ||
1bd897f8 BC |
121 | /* |
122 | * Used for context save and restore, structure members to be updated whenever | |
123 | * corresponding registers are modified. | |
124 | */ | |
125 | struct omap2_mcspi_regs { | |
126 | u32 modulctrl; | |
127 | u32 wakeupenable; | |
128 | struct list_head cs; | |
129 | }; | |
130 | ||
ccdc7bf9 | 131 | struct omap2_mcspi { |
ccdc7bf9 | 132 | struct spi_master *master; |
ccdc7bf9 SO |
133 | /* Virtual base address of the controller */ |
134 | void __iomem *base; | |
e5480b73 | 135 | unsigned long phys; |
ccdc7bf9 SO |
136 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
137 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 138 | struct device *dev; |
1bd897f8 | 139 | struct omap2_mcspi_regs ctx; |
d33f473d | 140 | int fifo_depth; |
0384e90b | 141 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
142 | }; |
143 | ||
144 | struct omap2_mcspi_cs { | |
145 | void __iomem *base; | |
e5480b73 | 146 | unsigned long phys; |
ccdc7bf9 | 147 | int word_len; |
97ca0d6c | 148 | u16 mode; |
89c05372 | 149 | struct list_head node; |
a41ae1ad | 150 | /* Context save and restore shadow register */ |
faee9b05 | 151 | u32 chconf0, chctrl0; |
a41ae1ad H |
152 | }; |
153 | ||
ccdc7bf9 SO |
154 | static inline void mcspi_write_reg(struct spi_master *master, |
155 | int idx, u32 val) | |
156 | { | |
157 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
158 | ||
21b2ce5e | 159 | writel_relaxed(val, mcspi->base + idx); |
ccdc7bf9 SO |
160 | } |
161 | ||
162 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
163 | { | |
164 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
165 | ||
21b2ce5e | 166 | return readl_relaxed(mcspi->base + idx); |
ccdc7bf9 SO |
167 | } |
168 | ||
169 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
170 | int idx, u32 val) | |
171 | { | |
172 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
173 | ||
21b2ce5e | 174 | writel_relaxed(val, cs->base + idx); |
ccdc7bf9 SO |
175 | } |
176 | ||
177 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
178 | { | |
179 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
180 | ||
21b2ce5e | 181 | return readl_relaxed(cs->base + idx); |
ccdc7bf9 SO |
182 | } |
183 | ||
a41ae1ad H |
184 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
185 | { | |
186 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
187 | ||
188 | return cs->chconf0; | |
189 | } | |
190 | ||
191 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
192 | { | |
193 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
194 | ||
195 | cs->chconf0 = val; | |
196 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 197 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
198 | } |
199 | ||
56cd5c15 IS |
200 | static inline int mcspi_bytes_per_word(int word_len) |
201 | { | |
202 | if (word_len <= 8) | |
203 | return 1; | |
204 | else if (word_len <= 16) | |
205 | return 2; | |
206 | else /* word_len <= 32 */ | |
207 | return 4; | |
208 | } | |
209 | ||
ccdc7bf9 SO |
210 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
211 | int is_read, int enable) | |
212 | { | |
213 | u32 l, rw; | |
214 | ||
a41ae1ad | 215 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
216 | |
217 | if (is_read) /* 1 is read, 0 write */ | |
218 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
219 | else | |
220 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
221 | ||
af4e944d S |
222 | if (enable) |
223 | l |= rw; | |
224 | else | |
225 | l &= ~rw; | |
226 | ||
a41ae1ad | 227 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
228 | } |
229 | ||
230 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
231 | { | |
faee9b05 | 232 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
233 | u32 l; |
234 | ||
faee9b05 SS |
235 | l = cs->chctrl0; |
236 | if (enable) | |
237 | l |= OMAP2_MCSPI_CHCTRL_EN; | |
238 | else | |
239 | l &= ~OMAP2_MCSPI_CHCTRL_EN; | |
240 | cs->chctrl0 = l; | |
241 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
4743a0f8 RT |
242 | /* Flash post-writes */ |
243 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
244 | } |
245 | ||
ddcad7e9 | 246 | static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) |
ccdc7bf9 | 247 | { |
5f74db10 | 248 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
ccdc7bf9 SO |
249 | u32 l; |
250 | ||
4373f8b6 MW |
251 | /* The controller handles the inverted chip selects |
252 | * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert | |
253 | * the inversion from the core spi_set_cs function. | |
254 | */ | |
255 | if (spi->mode & SPI_CS_HIGH) | |
256 | enable = !enable; | |
257 | ||
ddcad7e9 | 258 | if (spi->controller_state) { |
5f74db10 SR |
259 | int err = pm_runtime_get_sync(mcspi->dev); |
260 | if (err < 0) { | |
261 | dev_err(mcspi->dev, "failed to get sync: %d\n", err); | |
262 | return; | |
263 | } | |
264 | ||
ddcad7e9 | 265 | l = mcspi_cached_chconf0(spi); |
af4e944d | 266 | |
ddcad7e9 MW |
267 | if (enable) |
268 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
269 | else | |
270 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
271 | ||
272 | mcspi_write_chconf0(spi, l); | |
5f74db10 SR |
273 | |
274 | pm_runtime_mark_last_busy(mcspi->dev); | |
275 | pm_runtime_put_autosuspend(mcspi->dev); | |
ddcad7e9 | 276 | } |
ccdc7bf9 SO |
277 | } |
278 | ||
279 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
280 | { | |
1bd897f8 BC |
281 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
282 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
283 | u32 l; |
284 | ||
1bd897f8 BC |
285 | /* |
286 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
287 | * to single-channel master mode |
288 | */ | |
289 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
290 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
291 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 292 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 293 | |
1bd897f8 | 294 | ctx->modulctrl = l; |
a41ae1ad H |
295 | } |
296 | ||
d33f473d IS |
297 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
298 | struct spi_transfer *t, int enable) | |
299 | { | |
300 | struct spi_master *master = spi->master; | |
301 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
302 | struct omap2_mcspi *mcspi; | |
303 | unsigned int wcnt; | |
5db542ed | 304 | int max_fifo_depth, fifo_depth, bytes_per_word; |
d33f473d IS |
305 | u32 chconf, xferlevel; |
306 | ||
307 | mcspi = spi_master_get_devdata(master); | |
308 | ||
309 | chconf = mcspi_cached_chconf0(spi); | |
310 | if (enable) { | |
311 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
312 | if (t->len % bytes_per_word != 0) | |
313 | goto disable_fifo; | |
314 | ||
5db542ed IS |
315 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
316 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
317 | else | |
318 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
319 | ||
320 | fifo_depth = gcd(t->len, max_fifo_depth); | |
d33f473d IS |
321 | if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) |
322 | goto disable_fifo; | |
323 | ||
324 | wcnt = t->len / bytes_per_word; | |
325 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
326 | goto disable_fifo; | |
327 | ||
328 | xferlevel = wcnt << 16; | |
329 | if (t->rx_buf != NULL) { | |
330 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
331 | xferlevel |= (fifo_depth - 1) << 8; | |
5db542ed IS |
332 | } |
333 | if (t->tx_buf != NULL) { | |
d33f473d IS |
334 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
335 | xferlevel |= fifo_depth - 1; | |
336 | } | |
337 | ||
338 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
339 | mcspi_write_chconf0(spi, chconf); | |
340 | mcspi->fifo_depth = fifo_depth; | |
341 | ||
342 | return; | |
343 | } | |
344 | ||
345 | disable_fifo: | |
346 | if (t->rx_buf != NULL) | |
347 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
3d0763c0 JV |
348 | |
349 | if (t->tx_buf != NULL) | |
d33f473d IS |
350 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; |
351 | ||
352 | mcspi_write_chconf0(spi, chconf); | |
353 | mcspi->fifo_depth = 0; | |
354 | } | |
355 | ||
a41ae1ad H |
356 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
357 | { | |
1bd897f8 BC |
358 | struct spi_master *spi_cntrl = mcspi->master; |
359 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
360 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
361 | |
362 | /* McSPI: context restore */ | |
1bd897f8 BC |
363 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
364 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 365 | |
1bd897f8 | 366 | list_for_each_entry(cs, &ctx->cs, node) |
21b2ce5e | 367 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 368 | } |
ccdc7bf9 | 369 | |
2764c500 IK |
370 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
371 | { | |
372 | unsigned long timeout; | |
373 | ||
374 | timeout = jiffies + msecs_to_jiffies(1000); | |
21b2ce5e | 375 | while (!(readl_relaxed(reg) & bit)) { |
ff23fa3b | 376 | if (time_after(jiffies, timeout)) { |
21b2ce5e | 377 | if (!(readl_relaxed(reg) & bit)) |
ff23fa3b SAS |
378 | return -ETIMEDOUT; |
379 | else | |
380 | return 0; | |
381 | } | |
2764c500 IK |
382 | cpu_relax(); |
383 | } | |
384 | return 0; | |
385 | } | |
386 | ||
53741ed8 RK |
387 | static void omap2_mcspi_rx_callback(void *data) |
388 | { | |
389 | struct spi_device *spi = data; | |
390 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
391 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
392 | ||
53741ed8 RK |
393 | /* We must disable the DMA RX request */ |
394 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
395 | |
396 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
397 | } |
398 | ||
399 | static void omap2_mcspi_tx_callback(void *data) | |
400 | { | |
401 | struct spi_device *spi = data; | |
402 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
403 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
404 | ||
53741ed8 RK |
405 | /* We must disable the DMA TX request */ |
406 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
407 | |
408 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
409 | } |
410 | ||
d7b4394e S |
411 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
412 | struct spi_transfer *xfer, | |
413 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
414 | { |
415 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 416 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 417 | unsigned int count; |
ccdc7bf9 SO |
418 | |
419 | mcspi = spi_master_get_devdata(spi->master); | |
420 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 421 | count = xfer->len; |
ccdc7bf9 | 422 | |
d7b4394e | 423 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
424 | struct dma_async_tx_descriptor *tx; |
425 | struct scatterlist sg; | |
426 | ||
427 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
428 | ||
429 | sg_init_table(&sg, 1); | |
430 | sg_dma_address(&sg) = xfer->tx_dma; | |
431 | sg_dma_len(&sg) = xfer->len; | |
432 | ||
433 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 434 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
435 | if (tx) { |
436 | tx->callback = omap2_mcspi_tx_callback; | |
437 | tx->callback_param = spi; | |
438 | dmaengine_submit(tx); | |
439 | } else { | |
440 | /* FIXME: fall back to PIO? */ | |
441 | } | |
442 | } | |
d7b4394e S |
443 | dma_async_issue_pending(mcspi_dma->dma_tx); |
444 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
445 | ||
d7b4394e | 446 | } |
53741ed8 | 447 | |
d7b4394e S |
448 | static unsigned |
449 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
450 | struct dma_slave_config cfg, | |
451 | unsigned es) | |
452 | { | |
453 | struct omap2_mcspi *mcspi; | |
454 | struct omap2_mcspi_dma *mcspi_dma; | |
d33f473d | 455 | unsigned int count, dma_count; |
d7b4394e S |
456 | u32 l; |
457 | int elements = 0; | |
458 | int word_len, element_count; | |
459 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
460 | mcspi = spi_master_get_devdata(spi->master); | |
461 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
462 | count = xfer->len; | |
d33f473d IS |
463 | dma_count = xfer->len; |
464 | ||
465 | if (mcspi->fifo_depth == 0) | |
466 | dma_count -= es; | |
467 | ||
d7b4394e S |
468 | word_len = cs->word_len; |
469 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 470 | |
d7b4394e S |
471 | if (word_len <= 8) |
472 | element_count = count; | |
473 | else if (word_len <= 16) | |
474 | element_count = count >> 1; | |
475 | else /* word_len <= 32 */ | |
476 | element_count = count >> 2; | |
477 | ||
478 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
479 | struct dma_async_tx_descriptor *tx; |
480 | struct scatterlist sg; | |
53741ed8 RK |
481 | |
482 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
483 | ||
d33f473d IS |
484 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
485 | dma_count -= es; | |
53741ed8 RK |
486 | |
487 | sg_init_table(&sg, 1); | |
488 | sg_dma_address(&sg) = xfer->rx_dma; | |
d33f473d | 489 | sg_dma_len(&sg) = dma_count; |
53741ed8 RK |
490 | |
491 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
492 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
493 | DMA_CTRL_ACK); | |
53741ed8 RK |
494 | if (tx) { |
495 | tx->callback = omap2_mcspi_rx_callback; | |
496 | tx->callback_param = spi; | |
497 | dmaengine_submit(tx); | |
498 | } else { | |
d7b4394e | 499 | /* FIXME: fall back to PIO? */ |
2764c500 | 500 | } |
ccdc7bf9 SO |
501 | } |
502 | ||
d7b4394e S |
503 | dma_async_issue_pending(mcspi_dma->dma_rx); |
504 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 505 | |
d7b4394e S |
506 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
507 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
508 | DMA_FROM_DEVICE); | |
d33f473d IS |
509 | |
510 | if (mcspi->fifo_depth > 0) | |
511 | return count; | |
512 | ||
d7b4394e | 513 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 514 | |
d7b4394e | 515 | elements = element_count - 1; |
4743a0f8 | 516 | |
d7b4394e S |
517 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
518 | elements--; | |
4743a0f8 | 519 | |
57c5c28d | 520 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 521 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
522 | u32 w; |
523 | ||
524 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
525 | if (word_len <= 8) | |
d7b4394e | 526 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 527 | else if (word_len <= 16) |
d7b4394e | 528 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 529 | else /* word_len <= 32 */ |
d7b4394e | 530 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 531 | } else { |
56cd5c15 | 532 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 533 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 534 | count -= (bytes_per_word << 1); |
d7b4394e S |
535 | omap2_mcspi_set_enable(spi, 1); |
536 | return count; | |
57c5c28d | 537 | } |
ccdc7bf9 | 538 | } |
d7b4394e S |
539 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
540 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
541 | u32 w; | |
542 | ||
543 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
544 | if (word_len <= 8) | |
545 | ((u8 *)xfer->rx_buf)[elements] = w; | |
546 | else if (word_len <= 16) | |
547 | ((u16 *)xfer->rx_buf)[elements] = w; | |
548 | else /* word_len <= 32 */ | |
549 | ((u32 *)xfer->rx_buf)[elements] = w; | |
550 | } else { | |
a1829d2b | 551 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 552 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
553 | } |
554 | omap2_mcspi_set_enable(spi, 1); | |
555 | return count; | |
556 | } | |
557 | ||
558 | static unsigned | |
559 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
560 | { | |
561 | struct omap2_mcspi *mcspi; | |
562 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
563 | struct omap2_mcspi_dma *mcspi_dma; | |
564 | unsigned int count; | |
565 | u32 l; | |
566 | u8 *rx; | |
567 | const u8 *tx; | |
568 | struct dma_slave_config cfg; | |
569 | enum dma_slave_buswidth width; | |
570 | unsigned es; | |
d33f473d | 571 | u32 burst; |
e47a682a | 572 | void __iomem *chstat_reg; |
d33f473d IS |
573 | void __iomem *irqstat_reg; |
574 | int wait_res; | |
d7b4394e S |
575 | |
576 | mcspi = spi_master_get_devdata(spi->master); | |
577 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
578 | l = mcspi_cached_chconf0(spi); | |
579 | ||
580 | ||
581 | if (cs->word_len <= 8) { | |
582 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
583 | es = 1; | |
584 | } else if (cs->word_len <= 16) { | |
585 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
586 | es = 2; | |
587 | } else { | |
588 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
589 | es = 4; | |
590 | } | |
591 | ||
d33f473d IS |
592 | count = xfer->len; |
593 | burst = 1; | |
594 | ||
595 | if (mcspi->fifo_depth > 0) { | |
596 | if (count > mcspi->fifo_depth) | |
597 | burst = mcspi->fifo_depth / es; | |
598 | else | |
599 | burst = count / es; | |
600 | } | |
601 | ||
d7b4394e S |
602 | memset(&cfg, 0, sizeof(cfg)); |
603 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
604 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
605 | cfg.src_addr_width = width; | |
606 | cfg.dst_addr_width = width; | |
d33f473d IS |
607 | cfg.src_maxburst = burst; |
608 | cfg.dst_maxburst = burst; | |
d7b4394e S |
609 | |
610 | rx = xfer->rx_buf; | |
611 | tx = xfer->tx_buf; | |
612 | ||
d7b4394e S |
613 | if (tx != NULL) |
614 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
615 | ||
616 | if (rx != NULL) | |
e47a682a S |
617 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
618 | ||
619 | if (tx != NULL) { | |
e47a682a S |
620 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
621 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, | |
622 | DMA_TO_DEVICE); | |
623 | ||
d33f473d IS |
624 | if (mcspi->fifo_depth > 0) { |
625 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
626 | ||
627 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
628 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
629 | dev_err(&spi->dev, "EOW timed out\n"); | |
630 | ||
631 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
632 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
633 | } | |
634 | ||
e47a682a S |
635 | /* for TX_ONLY mode, be sure all words have shifted out */ |
636 | if (rx == NULL) { | |
d33f473d IS |
637 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
638 | if (mcspi->fifo_depth > 0) { | |
639 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
640 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
641 | if (wait_res < 0) | |
642 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
643 | } else { | |
644 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
645 | OMAP2_MCSPI_CHSTAT_TXS); | |
646 | if (wait_res < 0) | |
647 | dev_err(&spi->dev, "TXS timed out\n"); | |
648 | } | |
649 | if (wait_res >= 0 && | |
650 | (mcspi_wait_for_reg_bit(chstat_reg, | |
651 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
652 | dev_err(&spi->dev, "EOT timed out\n"); |
653 | } | |
654 | } | |
ccdc7bf9 SO |
655 | return count; |
656 | } | |
657 | ||
ccdc7bf9 SO |
658 | static unsigned |
659 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
660 | { | |
661 | struct omap2_mcspi *mcspi; | |
662 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
663 | unsigned int count, c; | |
664 | u32 l; | |
665 | void __iomem *base = cs->base; | |
666 | void __iomem *tx_reg; | |
667 | void __iomem *rx_reg; | |
668 | void __iomem *chstat_reg; | |
669 | int word_len; | |
670 | ||
671 | mcspi = spi_master_get_devdata(spi->master); | |
672 | count = xfer->len; | |
673 | c = count; | |
674 | word_len = cs->word_len; | |
675 | ||
a41ae1ad | 676 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
677 | |
678 | /* We store the pre-calculated register addresses on stack to speed | |
679 | * up the transfer loop. */ | |
680 | tx_reg = base + OMAP2_MCSPI_TX0; | |
681 | rx_reg = base + OMAP2_MCSPI_RX0; | |
682 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
683 | ||
adef658d MJ |
684 | if (c < (word_len>>3)) |
685 | return 0; | |
686 | ||
ccdc7bf9 SO |
687 | if (word_len <= 8) { |
688 | u8 *rx; | |
689 | const u8 *tx; | |
690 | ||
691 | rx = xfer->rx_buf; | |
692 | tx = xfer->tx_buf; | |
693 | ||
694 | do { | |
feed9bab | 695 | c -= 1; |
ccdc7bf9 SO |
696 | if (tx != NULL) { |
697 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
698 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
699 | dev_err(&spi->dev, "TXS timed out\n"); | |
700 | goto out; | |
701 | } | |
079a176d | 702 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 703 | word_len, *tx); |
21b2ce5e | 704 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
705 | } |
706 | if (rx != NULL) { | |
707 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
708 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
709 | dev_err(&spi->dev, "RXS timed out\n"); | |
710 | goto out; | |
711 | } | |
4743a0f8 RT |
712 | |
713 | if (c == 1 && tx == NULL && | |
714 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
715 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 716 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 717 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 718 | word_len, *(rx - 1)); |
4743a0f8 RT |
719 | if (mcspi_wait_for_reg_bit(chstat_reg, |
720 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
721 | dev_err(&spi->dev, | |
722 | "RXS timed out\n"); | |
723 | goto out; | |
724 | } | |
725 | c = 0; | |
726 | } else if (c == 0 && tx == NULL) { | |
727 | omap2_mcspi_set_enable(spi, 0); | |
728 | } | |
729 | ||
21b2ce5e | 730 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 731 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 732 | word_len, *(rx - 1)); |
ccdc7bf9 | 733 | } |
95c5c3ab | 734 | } while (c); |
ccdc7bf9 SO |
735 | } else if (word_len <= 16) { |
736 | u16 *rx; | |
737 | const u16 *tx; | |
738 | ||
739 | rx = xfer->rx_buf; | |
740 | tx = xfer->tx_buf; | |
741 | do { | |
feed9bab | 742 | c -= 2; |
ccdc7bf9 SO |
743 | if (tx != NULL) { |
744 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
745 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
746 | dev_err(&spi->dev, "TXS timed out\n"); | |
747 | goto out; | |
748 | } | |
079a176d | 749 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 750 | word_len, *tx); |
21b2ce5e | 751 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
752 | } |
753 | if (rx != NULL) { | |
754 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
755 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
756 | dev_err(&spi->dev, "RXS timed out\n"); | |
757 | goto out; | |
758 | } | |
4743a0f8 RT |
759 | |
760 | if (c == 2 && tx == NULL && | |
761 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
762 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 763 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 764 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 765 | word_len, *(rx - 1)); |
4743a0f8 RT |
766 | if (mcspi_wait_for_reg_bit(chstat_reg, |
767 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
768 | dev_err(&spi->dev, | |
769 | "RXS timed out\n"); | |
770 | goto out; | |
771 | } | |
772 | c = 0; | |
773 | } else if (c == 0 && tx == NULL) { | |
774 | omap2_mcspi_set_enable(spi, 0); | |
775 | } | |
776 | ||
21b2ce5e | 777 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 778 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 779 | word_len, *(rx - 1)); |
ccdc7bf9 | 780 | } |
95c5c3ab | 781 | } while (c >= 2); |
ccdc7bf9 SO |
782 | } else if (word_len <= 32) { |
783 | u32 *rx; | |
784 | const u32 *tx; | |
785 | ||
786 | rx = xfer->rx_buf; | |
787 | tx = xfer->tx_buf; | |
788 | do { | |
feed9bab | 789 | c -= 4; |
ccdc7bf9 SO |
790 | if (tx != NULL) { |
791 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
792 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
793 | dev_err(&spi->dev, "TXS timed out\n"); | |
794 | goto out; | |
795 | } | |
079a176d | 796 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 797 | word_len, *tx); |
21b2ce5e | 798 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
799 | } |
800 | if (rx != NULL) { | |
801 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
802 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
803 | dev_err(&spi->dev, "RXS timed out\n"); | |
804 | goto out; | |
805 | } | |
4743a0f8 RT |
806 | |
807 | if (c == 4 && tx == NULL && | |
808 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
809 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 810 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 811 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 812 | word_len, *(rx - 1)); |
4743a0f8 RT |
813 | if (mcspi_wait_for_reg_bit(chstat_reg, |
814 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
815 | dev_err(&spi->dev, | |
816 | "RXS timed out\n"); | |
817 | goto out; | |
818 | } | |
819 | c = 0; | |
820 | } else if (c == 0 && tx == NULL) { | |
821 | omap2_mcspi_set_enable(spi, 0); | |
822 | } | |
823 | ||
21b2ce5e | 824 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 825 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 826 | word_len, *(rx - 1)); |
ccdc7bf9 | 827 | } |
95c5c3ab | 828 | } while (c >= 4); |
ccdc7bf9 SO |
829 | } |
830 | ||
831 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
832 | if (xfer->rx_buf == NULL) { | |
833 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
834 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
835 | dev_err(&spi->dev, "TXS timed out\n"); | |
836 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
837 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
838 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
839 | |
840 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
841 | * otherwise these rx datas will affect the direct following | |
842 | * RX_ONLY transfer. | |
843 | */ | |
844 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
845 | } |
846 | out: | |
4743a0f8 | 847 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
848 | return count - c; |
849 | } | |
850 | ||
57d9c10d HH |
851 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
852 | { | |
853 | u32 div; | |
854 | ||
855 | for (div = 0; div < 15; div++) | |
856 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
857 | return div; | |
858 | ||
859 | return 15; | |
860 | } | |
861 | ||
ccdc7bf9 SO |
862 | /* called only when no transfer is active to this device */ |
863 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
864 | struct spi_transfer *t) | |
865 | { | |
866 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
867 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 868 | struct spi_master *spi_cntrl; |
faee9b05 | 869 | u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; |
ccdc7bf9 | 870 | u8 word_len = spi->bits_per_word; |
9bd4517d | 871 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
872 | |
873 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 874 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
875 | |
876 | if (t != NULL && t->bits_per_word) | |
877 | word_len = t->bits_per_word; | |
878 | ||
879 | cs->word_len = word_len; | |
880 | ||
9bd4517d SE |
881 | if (t && t->speed_hz) |
882 | speed_hz = t->speed_hz; | |
883 | ||
57d9c10d | 884 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
faee9b05 SS |
885 | if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { |
886 | clkd = omap2_mcspi_calc_divisor(speed_hz); | |
887 | speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; | |
888 | clkg = 0; | |
889 | } else { | |
890 | div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; | |
891 | speed_hz = OMAP2_MCSPI_MAX_FREQ / div; | |
892 | clkd = (div - 1) & 0xf; | |
893 | extclk = (div - 1) >> 4; | |
894 | clkg = OMAP2_MCSPI_CHCONF_CLKG; | |
895 | } | |
ccdc7bf9 | 896 | |
a41ae1ad | 897 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
898 | |
899 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
900 | * REVISIT: this controller could support SPI_3WIRE mode. | |
901 | */ | |
2cd45179 | 902 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
903 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
904 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
905 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
906 | } else { | |
907 | l |= OMAP2_MCSPI_CHCONF_IS; | |
908 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
909 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
910 | } | |
ccdc7bf9 SO |
911 | |
912 | /* wordlength */ | |
913 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
914 | l |= (word_len - 1) << 7; | |
915 | ||
916 | /* set chipselect polarity; manage with FORCE */ | |
917 | if (!(spi->mode & SPI_CS_HIGH)) | |
918 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
919 | else | |
920 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
921 | ||
922 | /* set clock divisor */ | |
923 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
faee9b05 SS |
924 | l |= clkd << 2; |
925 | ||
926 | /* set clock granularity */ | |
927 | l &= ~OMAP2_MCSPI_CHCONF_CLKG; | |
928 | l |= clkg; | |
929 | if (clkg) { | |
930 | cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; | |
931 | cs->chctrl0 |= extclk << 8; | |
932 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
933 | } | |
ccdc7bf9 SO |
934 | |
935 | /* set SPI mode 0..3 */ | |
936 | if (spi->mode & SPI_CPOL) | |
937 | l |= OMAP2_MCSPI_CHCONF_POL; | |
938 | else | |
939 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
940 | if (spi->mode & SPI_CPHA) | |
941 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
942 | else | |
943 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
944 | ||
a41ae1ad | 945 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 | 946 | |
97ca0d6c MG |
947 | cs->mode = spi->mode; |
948 | ||
ccdc7bf9 | 949 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
faee9b05 | 950 | speed_hz, |
ccdc7bf9 SO |
951 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
952 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
ddc5cdf1 TL |
957 | /* |
958 | * Note that we currently allow DMA only if we get a channel | |
959 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
960 | */ | |
ccdc7bf9 SO |
961 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
962 | { | |
963 | struct spi_master *master = spi->master; | |
964 | struct omap2_mcspi *mcspi; | |
965 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
966 | dma_cap_mask_t mask; |
967 | unsigned sig; | |
ccdc7bf9 SO |
968 | |
969 | mcspi = spi_master_get_devdata(master); | |
970 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
971 | ||
53741ed8 RK |
972 | init_completion(&mcspi_dma->dma_rx_completion); |
973 | init_completion(&mcspi_dma->dma_tx_completion); | |
974 | ||
975 | dma_cap_zero(mask); | |
976 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 | 977 | sig = mcspi_dma->dma_rx_sync_dev; |
74f3aaad MP |
978 | |
979 | mcspi_dma->dma_rx = | |
980 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
981 | &sig, &master->dev, | |
982 | mcspi_dma->dma_rx_ch_name); | |
ddc5cdf1 TL |
983 | if (!mcspi_dma->dma_rx) |
984 | goto no_dma; | |
ccdc7bf9 | 985 | |
53741ed8 | 986 | sig = mcspi_dma->dma_tx_sync_dev; |
74f3aaad MP |
987 | mcspi_dma->dma_tx = |
988 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
989 | &sig, &master->dev, | |
990 | mcspi_dma->dma_tx_ch_name); | |
991 | ||
53741ed8 | 992 | if (!mcspi_dma->dma_tx) { |
53741ed8 RK |
993 | dma_release_channel(mcspi_dma->dma_rx); |
994 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 995 | goto no_dma; |
ccdc7bf9 SO |
996 | } |
997 | ||
ccdc7bf9 | 998 | return 0; |
ddc5cdf1 TL |
999 | |
1000 | no_dma: | |
1001 | dev_warn(&spi->dev, "not using DMA for McSPI\n"); | |
1002 | return -EAGAIN; | |
ccdc7bf9 SO |
1003 | } |
1004 | ||
ccdc7bf9 SO |
1005 | static int omap2_mcspi_setup(struct spi_device *spi) |
1006 | { | |
1007 | int ret; | |
1bd897f8 BC |
1008 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
1009 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
1010 | struct omap2_mcspi_dma *mcspi_dma; |
1011 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
1012 | ||
ccdc7bf9 SO |
1013 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
1014 | ||
1015 | if (!cs) { | |
10aa5a35 | 1016 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
1017 | if (!cs) |
1018 | return -ENOMEM; | |
1019 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 1020 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
97ca0d6c | 1021 | cs->mode = 0; |
a41ae1ad | 1022 | cs->chconf0 = 0; |
faee9b05 | 1023 | cs->chctrl0 = 0; |
ccdc7bf9 | 1024 | spi->controller_state = cs; |
89c05372 | 1025 | /* Link this to context save list */ |
1bd897f8 | 1026 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
1027 | } |
1028 | ||
8c7494a5 | 1029 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 1030 | ret = omap2_mcspi_request_dma(spi); |
ddc5cdf1 | 1031 | if (ret < 0 && ret != -EAGAIN) |
ccdc7bf9 SO |
1032 | return ret; |
1033 | } | |
1034 | ||
bc7f9bbc | 1035 | if (gpio_is_valid(spi->cs_gpio)) { |
c4339ac7 MW |
1036 | ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); |
1037 | if (ret) { | |
1038 | dev_err(&spi->dev, "failed to request gpio\n"); | |
1039 | return ret; | |
1040 | } | |
1041 | gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
bc7f9bbc MW |
1042 | } |
1043 | ||
034d3dc9 | 1044 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1045 | if (ret < 0) |
1046 | return ret; | |
a41ae1ad | 1047 | |
86eeb6fe | 1048 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
1049 | pm_runtime_mark_last_busy(mcspi->dev); |
1050 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1051 | |
1052 | return ret; | |
1053 | } | |
1054 | ||
1055 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
1056 | { | |
1057 | struct omap2_mcspi *mcspi; | |
1058 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1059 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1060 | |
1061 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1062 | |
5e774943 SE |
1063 | if (spi->controller_state) { |
1064 | /* Unlink controller state from context save list */ | |
1065 | cs = spi->controller_state; | |
1066 | list_del(&cs->node); | |
89c05372 | 1067 | |
10aa5a35 | 1068 | kfree(cs); |
5e774943 | 1069 | } |
ccdc7bf9 | 1070 | |
99f1a43f SE |
1071 | if (spi->chip_select < spi->master->num_chipselect) { |
1072 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1073 | ||
53741ed8 RK |
1074 | if (mcspi_dma->dma_rx) { |
1075 | dma_release_channel(mcspi_dma->dma_rx); | |
1076 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1077 | } |
53741ed8 RK |
1078 | if (mcspi_dma->dma_tx) { |
1079 | dma_release_channel(mcspi_dma->dma_tx); | |
1080 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1081 | } |
ccdc7bf9 | 1082 | } |
bc7f9bbc MW |
1083 | |
1084 | if (gpio_is_valid(spi->cs_gpio)) | |
1085 | gpio_free(spi->cs_gpio); | |
ccdc7bf9 SO |
1086 | } |
1087 | ||
b28cb941 MW |
1088 | static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi, |
1089 | struct spi_device *spi, struct spi_transfer *t) | |
ccdc7bf9 | 1090 | { |
ccdc7bf9 SO |
1091 | |
1092 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1093 | * -- although this controller would gladly |
ccdc7bf9 SO |
1094 | * arbitrate among multiple channels. This corresponds to "single |
1095 | * channel" master mode. As a side effect, we need to manage the | |
1096 | * chipselect with the FORCE bit ... CS != channel enable. | |
1097 | */ | |
ccdc7bf9 | 1098 | |
5cbc7ca9 | 1099 | struct spi_master *master; |
ddc5cdf1 | 1100 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1101 | struct omap2_mcspi_cs *cs; |
1102 | struct omap2_mcspi_device_config *cd; | |
1103 | int par_override = 0; | |
1104 | int status = 0; | |
1105 | u32 chconf; | |
ccdc7bf9 | 1106 | |
5cbc7ca9 | 1107 | master = spi->master; |
ddc5cdf1 | 1108 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1109 | cs = spi->controller_state; |
1110 | cd = spi->controller_data; | |
ccdc7bf9 | 1111 | |
97ca0d6c MG |
1112 | /* |
1113 | * The slave driver could have changed spi->mode in which case | |
1114 | * it will be different from cs->mode (the current hardware setup). | |
1115 | * If so, set par_override (even though its not a parity issue) so | |
1116 | * omap2_mcspi_setup_transfer will be called to configure the hardware | |
1117 | * with the correct mode on the first iteration of the loop below. | |
1118 | */ | |
1119 | if (spi->mode != cs->mode) | |
1120 | par_override = 1; | |
1121 | ||
d33f473d | 1122 | omap2_mcspi_set_enable(spi, 0); |
4743a0f8 | 1123 | |
a06b430f MW |
1124 | if (gpio_is_valid(spi->cs_gpio)) |
1125 | omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); | |
1126 | ||
b28cb941 MW |
1127 | if (par_override || |
1128 | (t->speed_hz != spi->max_speed_hz) || | |
1129 | (t->bits_per_word != spi->bits_per_word)) { | |
1130 | par_override = 1; | |
1131 | status = omap2_mcspi_setup_transfer(spi, t); | |
1132 | if (status < 0) | |
1133 | goto out; | |
1134 | if (t->speed_hz == spi->max_speed_hz && | |
1135 | t->bits_per_word == spi->bits_per_word) | |
1136 | par_override = 0; | |
1137 | } | |
1138 | if (cd && cd->cs_per_word) { | |
1139 | chconf = mcspi->ctx.modulctrl; | |
1140 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1141 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1142 | mcspi->ctx.modulctrl = | |
1143 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1144 | } | |
4743a0f8 | 1145 | |
b28cb941 MW |
1146 | chconf = mcspi_cached_chconf0(spi); |
1147 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1148 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
1149 | ||
1150 | if (t->tx_buf == NULL) | |
1151 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1152 | else if (t->rx_buf == NULL) | |
1153 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
1154 | ||
1155 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { | |
1156 | /* Turbo mode is for more than one word */ | |
1157 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1158 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1159 | } | |
ccdc7bf9 | 1160 | |
b28cb941 | 1161 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1162 | |
b28cb941 MW |
1163 | if (t->len) { |
1164 | unsigned count; | |
5fda88f5 | 1165 | |
b28cb941 MW |
1166 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1167 | (t->len >= DMA_MIN_BYTES)) | |
1168 | omap2_mcspi_set_fifo(spi, t, 1); | |
d33f473d | 1169 | |
b28cb941 | 1170 | omap2_mcspi_set_enable(spi, 1); |
d33f473d | 1171 | |
b28cb941 MW |
1172 | /* RX_ONLY mode needs dummy data in TX reg */ |
1173 | if (t->tx_buf == NULL) | |
1174 | writel_relaxed(0, cs->base | |
1175 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 1176 | |
b28cb941 MW |
1177 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1178 | (t->len >= DMA_MIN_BYTES)) | |
1179 | count = omap2_mcspi_txrx_dma(spi, t); | |
1180 | else | |
1181 | count = omap2_mcspi_txrx_pio(spi, t); | |
ccdc7bf9 | 1182 | |
b28cb941 MW |
1183 | if (count != t->len) { |
1184 | status = -EIO; | |
1185 | goto out; | |
ccdc7bf9 | 1186 | } |
b28cb941 | 1187 | } |
ccdc7bf9 | 1188 | |
b28cb941 | 1189 | omap2_mcspi_set_enable(spi, 0); |
d33f473d | 1190 | |
b28cb941 MW |
1191 | if (mcspi->fifo_depth > 0) |
1192 | omap2_mcspi_set_fifo(spi, t, 0); | |
1193 | ||
1194 | out: | |
5fda88f5 S |
1195 | /* Restore defaults if they were overriden */ |
1196 | if (par_override) { | |
1197 | par_override = 0; | |
1198 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1199 | } | |
ccdc7bf9 | 1200 | |
5cbc7ca9 MB |
1201 | if (cd && cd->cs_per_word) { |
1202 | chconf = mcspi->ctx.modulctrl; | |
1203 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1204 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1205 | mcspi->ctx.modulctrl = | |
1206 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1207 | } | |
1208 | ||
5fda88f5 | 1209 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1210 | |
a06b430f MW |
1211 | if (gpio_is_valid(spi->cs_gpio)) |
1212 | omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); | |
1213 | ||
d33f473d IS |
1214 | if (mcspi->fifo_depth > 0 && t) |
1215 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1216 | |
b28cb941 | 1217 | return status; |
ccdc7bf9 SO |
1218 | } |
1219 | ||
468a3208 NA |
1220 | static int omap2_mcspi_prepare_message(struct spi_master *master, |
1221 | struct spi_message *msg) | |
1222 | { | |
1223 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1224 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
1225 | struct omap2_mcspi_cs *cs; | |
1226 | ||
1227 | /* Only a single channel can have the FORCE bit enabled | |
1228 | * in its chconf0 register. | |
1229 | * Scan all channels and disable them except the current one. | |
1230 | * A FORCE can remain from a last transfer having cs_change enabled | |
1231 | */ | |
1232 | list_for_each_entry(cs, &ctx->cs, node) { | |
1233 | if (msg->spi->controller_state == cs) | |
1234 | continue; | |
1235 | ||
1236 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { | |
1237 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
1238 | writel_relaxed(cs->chconf0, | |
1239 | cs->base + OMAP2_MCSPI_CHCONF0); | |
1240 | readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); | |
1241 | } | |
1242 | } | |
1243 | ||
1244 | return 0; | |
1245 | } | |
1246 | ||
b28cb941 MW |
1247 | static int omap2_mcspi_transfer_one(struct spi_master *master, |
1248 | struct spi_device *spi, struct spi_transfer *t) | |
ccdc7bf9 SO |
1249 | { |
1250 | struct omap2_mcspi *mcspi; | |
ddc5cdf1 | 1251 | struct omap2_mcspi_dma *mcspi_dma; |
b28cb941 MW |
1252 | const void *tx_buf = t->tx_buf; |
1253 | void *rx_buf = t->rx_buf; | |
1254 | unsigned len = t->len; | |
ccdc7bf9 | 1255 | |
5fda88f5 | 1256 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1257 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
ccdc7bf9 | 1258 | |
b28cb941 MW |
1259 | if ((len && !(rx_buf || tx_buf))) { |
1260 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", | |
1261 | t->speed_hz, | |
1262 | len, | |
1263 | tx_buf ? "tx" : "", | |
1264 | rx_buf ? "rx" : "", | |
1265 | t->bits_per_word); | |
1266 | return -EINVAL; | |
1267 | } | |
1268 | ||
1269 | if (len < DMA_MIN_BYTES) | |
1270 | goto skip_dma_map; | |
1271 | ||
1272 | if (mcspi_dma->dma_tx && tx_buf != NULL) { | |
1273 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, | |
1274 | len, DMA_TO_DEVICE); | |
1275 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { | |
1276 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
1277 | 'T', len); | |
1278 | return -EINVAL; | |
ccdc7bf9 | 1279 | } |
b28cb941 MW |
1280 | } |
1281 | if (mcspi_dma->dma_rx && rx_buf != NULL) { | |
1282 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, | |
1283 | DMA_FROM_DEVICE); | |
1284 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { | |
1285 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
1286 | 'R', len); | |
1287 | if (tx_buf != NULL) | |
1288 | dma_unmap_single(mcspi->dev, t->tx_dma, | |
1289 | len, DMA_TO_DEVICE); | |
1290 | return -EINVAL; | |
ccdc7bf9 SO |
1291 | } |
1292 | } | |
1293 | ||
b28cb941 MW |
1294 | skip_dma_map: |
1295 | return omap2_mcspi_work_one(mcspi, spi, t); | |
ccdc7bf9 SO |
1296 | } |
1297 | ||
fd4a319b | 1298 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1299 | { |
1300 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1301 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1302 | int ret = 0; |
ccdc7bf9 | 1303 | |
034d3dc9 | 1304 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1305 | if (ret < 0) |
1306 | return ret; | |
ddb22195 | 1307 | |
39f8052d | 1308 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1309 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1310 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1311 | |
1312 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1313 | pm_runtime_mark_last_busy(mcspi->dev); |
1314 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1315 | return 0; |
1316 | } | |
1317 | ||
1f1a4384 G |
1318 | static int omap_mcspi_runtime_resume(struct device *dev) |
1319 | { | |
1320 | struct omap2_mcspi *mcspi; | |
1321 | struct spi_master *master; | |
1322 | ||
1323 | master = dev_get_drvdata(dev); | |
1324 | mcspi = spi_master_get_devdata(master); | |
1325 | omap2_mcspi_restore_ctx(mcspi); | |
1326 | ||
1327 | return 0; | |
1328 | } | |
1329 | ||
d5a80031 BC |
1330 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1331 | .regs_offset = 0, | |
1332 | }; | |
1333 | ||
1334 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1335 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1336 | }; | |
1337 | ||
1338 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1339 | { | |
1340 | .compatible = "ti,omap2-mcspi", | |
1341 | .data = &omap2_pdata, | |
1342 | }, | |
1343 | { | |
1344 | .compatible = "ti,omap4-mcspi", | |
1345 | .data = &omap4_pdata, | |
1346 | }, | |
1347 | { }, | |
1348 | }; | |
1349 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1350 | |
fd4a319b | 1351 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1352 | { |
1353 | struct spi_master *master; | |
83a01e72 | 1354 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1355 | struct omap2_mcspi *mcspi; |
1356 | struct resource *r; | |
1357 | int status = 0, i; | |
d5a80031 BC |
1358 | u32 regs_offset = 0; |
1359 | static int bus_num = 1; | |
1360 | struct device_node *node = pdev->dev.of_node; | |
1361 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1362 | |
1363 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1364 | if (master == NULL) { | |
1365 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1366 | return -ENOMEM; | |
1367 | } | |
1368 | ||
e7db06b5 DB |
1369 | /* the spi->mode bits understood by this driver: */ |
1370 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1371 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1372 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1373 | master->auto_runtime_pm = true; |
468a3208 | 1374 | master->prepare_message = omap2_mcspi_prepare_message; |
b28cb941 | 1375 | master->transfer_one = omap2_mcspi_transfer_one; |
ddcad7e9 | 1376 | master->set_cs = omap2_mcspi_set_cs; |
ccdc7bf9 | 1377 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 | 1378 | master->dev.of_node = node; |
aca0924b AL |
1379 | master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; |
1380 | master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; | |
d5a80031 | 1381 | |
24b5a82c | 1382 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1383 | |
1384 | mcspi = spi_master_get_devdata(master); | |
1385 | mcspi->master = master; | |
1386 | ||
d5a80031 BC |
1387 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1388 | if (match) { | |
1389 | u32 num_cs = 1; /* default number of chipselect */ | |
1390 | pdata = match->data; | |
1391 | ||
1392 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1393 | master->num_chipselect = num_cs; | |
1394 | master->bus_num = bus_num++; | |
2cd45179 DM |
1395 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1396 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1397 | } else { |
8074cf06 | 1398 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 BC |
1399 | master->num_chipselect = pdata->num_cs; |
1400 | if (pdev->id != -1) | |
1401 | master->bus_num = pdev->id; | |
0384e90b | 1402 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1403 | } |
1404 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1405 | |
ccdc7bf9 SO |
1406 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1407 | if (r == NULL) { | |
1408 | status = -ENODEV; | |
39f1b565 | 1409 | goto free_master; |
ccdc7bf9 | 1410 | } |
1458d160 | 1411 | |
d5a80031 BC |
1412 | r->start += regs_offset; |
1413 | r->end += regs_offset; | |
1458d160 | 1414 | mcspi->phys = r->start; |
ccdc7bf9 | 1415 | |
b0ee5605 TR |
1416 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1417 | if (IS_ERR(mcspi->base)) { | |
1418 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1419 | goto free_master; |
55c381e4 | 1420 | } |
ccdc7bf9 | 1421 | |
1f1a4384 | 1422 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1423 | |
1bd897f8 | 1424 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1425 | |
a6f936db AL |
1426 | mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, |
1427 | sizeof(struct omap2_mcspi_dma), | |
1428 | GFP_KERNEL); | |
1429 | if (mcspi->dma_channels == NULL) { | |
1430 | status = -ENOMEM; | |
1a77b127 | 1431 | goto free_master; |
a6f936db | 1432 | } |
ccdc7bf9 | 1433 | |
1a5d8190 | 1434 | for (i = 0; i < master->num_chipselect; i++) { |
74f3aaad MP |
1435 | char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; |
1436 | char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; | |
1a5d8190 C |
1437 | struct resource *dma_res; |
1438 | ||
74f3aaad MP |
1439 | sprintf(dma_rx_ch_name, "rx%d", i); |
1440 | if (!pdev->dev.of_node) { | |
1441 | dma_res = | |
1442 | platform_get_resource_byname(pdev, | |
1443 | IORESOURCE_DMA, | |
1444 | dma_rx_ch_name); | |
1445 | if (!dma_res) { | |
1446 | dev_dbg(&pdev->dev, | |
1447 | "cannot get DMA RX channel\n"); | |
1448 | status = -ENODEV; | |
1449 | break; | |
1450 | } | |
1a5d8190 | 1451 | |
74f3aaad MP |
1452 | mcspi->dma_channels[i].dma_rx_sync_dev = |
1453 | dma_res->start; | |
1a5d8190 | 1454 | } |
74f3aaad MP |
1455 | sprintf(dma_tx_ch_name, "tx%d", i); |
1456 | if (!pdev->dev.of_node) { | |
1457 | dma_res = | |
1458 | platform_get_resource_byname(pdev, | |
1459 | IORESOURCE_DMA, | |
1460 | dma_tx_ch_name); | |
1461 | if (!dma_res) { | |
1462 | dev_dbg(&pdev->dev, | |
1463 | "cannot get DMA TX channel\n"); | |
1464 | status = -ENODEV; | |
1465 | break; | |
1466 | } | |
1a5d8190 | 1467 | |
74f3aaad MP |
1468 | mcspi->dma_channels[i].dma_tx_sync_dev = |
1469 | dma_res->start; | |
1470 | } | |
ccdc7bf9 SO |
1471 | } |
1472 | ||
39f1b565 | 1473 | if (status < 0) |
a6f936db | 1474 | goto free_master; |
39f1b565 | 1475 | |
27b5284c S |
1476 | pm_runtime_use_autosuspend(&pdev->dev); |
1477 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1478 | pm_runtime_enable(&pdev->dev); |
1479 | ||
142e07be WY |
1480 | status = omap2_mcspi_master_setup(mcspi); |
1481 | if (status < 0) | |
39f1b565 | 1482 | goto disable_pm; |
ccdc7bf9 | 1483 | |
b95e02b7 | 1484 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1485 | if (status < 0) |
37a2d84a | 1486 | goto disable_pm; |
ccdc7bf9 SO |
1487 | |
1488 | return status; | |
1489 | ||
39f1b565 | 1490 | disable_pm: |
751c925c | 1491 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1492 | free_master: |
37a2d84a | 1493 | spi_master_put(master); |
ccdc7bf9 SO |
1494 | return status; |
1495 | } | |
1496 | ||
fd4a319b | 1497 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 | 1498 | { |
a6f936db AL |
1499 | struct spi_master *master = platform_get_drvdata(pdev); |
1500 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
ccdc7bf9 | 1501 | |
a93a2029 | 1502 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1503 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1504 | |
ccdc7bf9 SO |
1505 | return 0; |
1506 | } | |
1507 | ||
7e38c3c4 KS |
1508 | /* work with hotplug and coldplug */ |
1509 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1510 | ||
42ce7fd6 GC |
1511 | #ifdef CONFIG_SUSPEND |
1512 | /* | |
1513 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1514 | * unactive state when driver was suspend, then force it to unactive state at | |
1515 | * wake up. | |
1516 | */ | |
1517 | static int omap2_mcspi_resume(struct device *dev) | |
1518 | { | |
1519 | struct spi_master *master = dev_get_drvdata(dev); | |
1520 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1521 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1522 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1523 | |
034d3dc9 | 1524 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1525 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1526 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1527 | /* |
1528 | * We need to toggle CS state for OMAP take this | |
1529 | * change in account. | |
1530 | */ | |
af4e944d | 1531 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1532 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1533 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1534 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
42ce7fd6 GC |
1535 | } |
1536 | } | |
034d3dc9 S |
1537 | pm_runtime_mark_last_busy(mcspi->dev); |
1538 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1539 | return 0; |
1540 | } | |
1541 | #else | |
1542 | #define omap2_mcspi_resume NULL | |
1543 | #endif | |
1544 | ||
1545 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1546 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1547 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1548 | }; |
1549 | ||
ccdc7bf9 SO |
1550 | static struct platform_driver omap2_mcspi_driver = { |
1551 | .driver = { | |
1552 | .name = "omap2_mcspi", | |
d5a80031 BC |
1553 | .pm = &omap2_mcspi_pm_ops, |
1554 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1555 | }, |
7d6b6d83 | 1556 | .probe = omap2_mcspi_probe, |
fd4a319b | 1557 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1558 | }; |
1559 | ||
9fdca9df | 1560 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1561 | MODULE_LICENSE("GPL"); |