[deliverable/linux.git] / drivers / spi / spi-orion.c

/*
 * Marvell Orion SPI controller driver
 *
 * Author: Shadi Ammouri <shadi@marvell.com>
 * Copyright (C) 2007-2008 Marvell Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/sizes.h>
#include <asm/unaligned.h>

#define DRIVER_NAME			"orion_spi"

#define ORION_NUM_CHIPSELECTS		1 /* only one slave is supported*/
#define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */

#define ORION_SPI_IF_CTRL_REG		0x00
#define ORION_SPI_IF_CONFIG_REG		0x04
#define ORION_SPI_DATA_OUT_REG		0x08
#define ORION_SPI_DATA_IN_REG		0x0c
#define ORION_SPI_INT_CAUSE_REG		0x10

#define ORION_SPI_MODE_CPOL		(1 << 11)
#define ORION_SPI_MODE_CPHA		(1 << 12)
#define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
#define ORION_SPI_CLK_PRESCALE_MASK	0x1F
#define ORION_SPI_MODE_MASK		(ORION_SPI_MODE_CPOL | \
					 ORION_SPI_MODE_CPHA)

struct orion_spi {
	struct spi_master	*master;
	void __iomem		*base;
	unsigned int		max_speed;
	unsigned int		min_speed;
	struct clk              *clk;
};

static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
{
	return orion_spi->base + reg;
}

static inline void
orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val |= mask;
	writel(val, reg_addr);
}

static inline void
orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val &= ~mask;
	writel(val, reg_addr);
}

static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
{
	if (size == 16) {
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	} else if (size == 8) {
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	} else {
		pr_debug("Bad bits per word value %d (only 8 or 16 are allowed).\n",
			size);
		return -EINVAL;
	}

	return 0;
}

static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
{
	u32 tclk_hz;
	u32 rate;
	u32 prescale;
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	tclk_hz = clk_get_rate(orion_spi->clk);

	/*
	 * the supported rates are: 4,6,8...30
	 * round up as we look for equal or less speed
	 */
	rate = DIV_ROUND_UP(tclk_hz, speed);
	rate = roundup(rate, 2);

	/* check if requested speed is too small */
	if (rate > 30)
		return -EINVAL;

	if (rate < 4)
		rate = 4;

	/* Convert the rate to SPI clock divisor value.	*/
	prescale = 0x10 + rate/2;

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));

	return 0;
}

static void
orion_spi_mode_set(struct spi_device *spi)
{
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg &= ~ORION_SPI_MODE_MASK;
	if (spi->mode & SPI_CPOL)
		reg |= ORION_SPI_MODE_CPOL;
	if (spi->mode & SPI_CPHA)
		reg |= ORION_SPI_MODE_CPHA;
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
}

/*
 * called only when no transfer is active on the bus
 */
static int
orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct orion_spi *orion_spi;
	unsigned int speed = spi->max_speed_hz;
	unsigned int bits_per_word = spi->bits_per_word;
	int	rc;

	orion_spi = spi_master_get_devdata(spi->master);

	if ((t != NULL) && t->speed_hz)
		speed = t->speed_hz;

	if ((t != NULL) && t->bits_per_word)
		bits_per_word = t->bits_per_word;

	orion_spi_mode_set(spi);

	rc = orion_spi_baudrate_set(spi, speed);
	if (rc)
		return rc;

	return orion_spi_set_transfer_size(orion_spi, bits_per_word);
}

static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
{
	if (enable)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
}

static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
{
	int i;

	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
			return 1;
		else
			udelay(1);
	}

	return -1;
}

static inline int
orion_spi_write_read_8bit(struct spi_device *spi,
			  const u8 **tx_buf, u8 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(*(*tx_buf)++, tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		*(*rx_buf)++ = readl(rx_reg);

	return 1;
}

static inline int
orion_spi_write_read_16bit(struct spi_device *spi,
			   const u16 **tx_buf, u16 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);

	return 1;
}

static unsigned int
orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
{
	struct orion_spi *orion_spi;
	unsigned int count;
	int word_len;

	orion_spi = spi_master_get_devdata(spi->master);
	word_len = spi->bits_per_word;
	count = xfer->len;

	if (word_len == 8) {
		const u8 *tx = xfer->tx_buf;
		u8 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
				goto out;
			count--;
		} while (count);
	} else if (word_len == 16) {
		const u16 *tx = xfer->tx_buf;
		u16 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
				goto out;
			count -= 2;
		} while (count);
	}

out:
	return xfer->len - count;
}


static int orion_spi_transfer_one_message(struct spi_master *master,
					   struct spi_message *m)
{
	struct orion_spi *orion_spi = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	struct spi_transfer *t = NULL;
	int par_override = 0;
	int status = 0;
	int cs_active = 0;

	/* Load defaults */
	status = orion_spi_setup_transfer(spi, NULL);

	if (status < 0)
		goto msg_done;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		/* make sure buffer length is even when working in 16
		 * bit mode*/
		if ((t->bits_per_word == 16) && (t->len & 1)) {
			dev_err(&spi->dev,
				"message rejected : "
				"odd data length %d while in 16 bit mode\n",
				t->len);
			status = -EIO;
			goto msg_done;
		}

		if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
			dev_err(&spi->dev,
				"message rejected : "
				"device min speed (%d Hz) exceeds "
				"required transfer speed (%d Hz)\n",
				orion_spi->min_speed, t->speed_hz);
			status = -EIO;
			goto msg_done;
		}

		if (par_override || t->speed_hz || t->bits_per_word) {
			par_override = 1;
			status = orion_spi_setup_transfer(spi, t);
			if (status < 0)
				break;
			if (!t->speed_hz && !t->bits_per_word)
				par_override = 0;
		}

		if (!cs_active) {
			orion_spi_set_cs(orion_spi, 1);
			cs_active = 1;
		}

		if (t->len)
			m->actual_length += orion_spi_write_read(spi, t);

		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (t->cs_change) {
			orion_spi_set_cs(orion_spi, 0);
			cs_active = 0;
		}
	}

msg_done:
	if (cs_active)
		orion_spi_set_cs(orion_spi, 0);

	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static int orion_spi_reset(struct orion_spi *orion_spi)
{
	/* Verify that the CS is deasserted */
	orion_spi_set_cs(orion_spi, 0);

	return 0;
}

static int orion_spi_setup(struct spi_device *spi)
{
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	if ((spi->max_speed_hz == 0)
			|| (spi->max_speed_hz > orion_spi->max_speed))
		spi->max_speed_hz = orion_spi->max_speed;

	if (spi->max_speed_hz < orion_spi->min_speed) {
		dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
			spi->max_speed_hz);
		return -EINVAL;
	}

	/*
	 * baudrate & width will be set orion_spi_setup_transfer
	 */
	return 0;
}

static int orion_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;
	struct resource *r;
	unsigned long tclk_hz;
	int status = 0;
	const u32 *iprop;
	int size;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (master == NULL) {
		dev_dbg(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	if (pdev->id != -1)
		master->bus_num = pdev->id;
	if (pdev->dev.of_node) {
		iprop = of_get_property(pdev->dev.of_node, "cell-index",
					&size);
		if (iprop && size == sizeof(*iprop))
			master->bus_num = *iprop;
	}

	/* we support only mode 0, and no options */
	master->mode_bits = SPI_CPHA | SPI_CPOL;

	master->setup = orion_spi_setup;
	master->transfer_one_message = orion_spi_transfer_one_message;
	master->num_chipselect = ORION_NUM_CHIPSELECTS;

	platform_set_drvdata(pdev, master);

	spi = spi_master_get_devdata(master);
	spi->master = master;

	spi->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(spi->clk)) {
		status = PTR_ERR(spi->clk);
		goto out;
	}

	clk_prepare(spi->clk);
	clk_enable(spi->clk);
	tclk_hz = clk_get_rate(spi->clk);
	spi->max_speed = DIV_ROUND_UP(tclk_hz, 4);
	spi->min_speed = DIV_ROUND_UP(tclk_hz, 30);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	spi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(spi->base)) {
		status = PTR_ERR(spi->base);
		goto out_rel_clk;
	}

	if (orion_spi_reset(spi) < 0)
		goto out_rel_clk;

	master->dev.of_node = pdev->dev.of_node;
	status = devm_spi_register_master(&pdev->dev, master);
	if (status < 0)
		goto out_rel_clk;

	return status;

out_rel_clk:
	clk_disable_unprepare(spi->clk);
out:
	spi_master_put(master);
	return status;
}


static int orion_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;

	master = platform_get_drvdata(pdev);
	spi = spi_master_get_devdata(master);

	clk_disable_unprepare(spi->clk);

	return 0;
}

MODULE_ALIAS("platform:" DRIVER_NAME);

static const struct of_device_id orion_spi_of_match_table[] = {
	{ .compatible = "marvell,orion-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);

static struct platform_driver orion_spi_driver = {
	.driver = {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(orion_spi_of_match_table),
	},
	.probe		= orion_spi_probe,
	.remove		= orion_spi_remove,
};

module_platform_driver(orion_spi_driver);

MODULE_DESCRIPTION("Orion SPI driver");
MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
60cadec9	1	/*
ca632f55	2	* Marvell Orion SPI controller driver
60cadec9 SA	3	*
	4	* Author: Shadi Ammouri <shadi@marvell.com>
	5	* Copyright (C) 2007-2008 Marvell Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/delay.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/spi/spi.h>
d7614de4	19	#include <linux/module.h>
f814f9ac	20	#include <linux/of.h>
4574b886	21	#include <linux/clk.h>
895248f8	22	#include <linux/sizes.h>
60cadec9 SA	23	#include <asm/unaligned.h>
	24
	25	#define DRIVER_NAME "orion_spi"
	26
	27	#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
	28	#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
	29
	30	#define ORION_SPI_IF_CTRL_REG 0x00
	31	#define ORION_SPI_IF_CONFIG_REG 0x04
	32	#define ORION_SPI_DATA_OUT_REG 0x08
	33	#define ORION_SPI_DATA_IN_REG 0x0c
	34	#define ORION_SPI_INT_CAUSE_REG 0x10
	35
b15d5d70 JG	36	#define ORION_SPI_MODE_CPOL (1 << 11)
b15d5d70 JG	37	#define ORION_SPI_MODE_CPHA (1 << 12)
60cadec9 SA	38	#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
60cadec9 SA	39	#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
b15d5d70 JG	40	#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL \| \
b15d5d70 JG	41	ORION_SPI_MODE_CPHA)
60cadec9 SA	42
60cadec9 SA	43	struct orion_spi {
60cadec9 SA	44	struct spi_master *master;
	45	void __iomem *base;
	46	unsigned int max_speed;
	47	unsigned int min_speed;
4574b886	48	struct clk *clk;
60cadec9 SA	49	};
60cadec9 SA	50
60cadec9 SA	51	static inline void __iomem spi_reg(struct orion_spi orion_spi, u32 reg)
	52	{
	53	return orion_spi->base + reg;
	54	}
	55
	56	static inline void
	57	orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	58	{
	59	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	60	u32 val;
	61
	62	val = readl(reg_addr);
	63	val \|= mask;
	64	writel(val, reg_addr);
	65	}
	66
	67	static inline void
	68	orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	69	{
	70	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	71	u32 val;
	72
	73	val = readl(reg_addr);
	74	val &= ~mask;
	75	writel(val, reg_addr);
	76	}
	77
	78	static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
	79	{
	80	if (size == 16) {
	81	orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	82	ORION_SPI_IF_8_16_BIT_MODE);
	83	} else if (size == 8) {
	84	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	85	ORION_SPI_IF_8_16_BIT_MODE);
	86	} else {
3fed8068 JH	87	pr_debug("Bad bits per word value %d (only 8 or 16 are allowed).\n",
3fed8068 JH	88	size);
60cadec9 SA	89	return -EINVAL;
	90	}
	91
	92	return 0;
	93	}
	94
	95	static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
	96	{
	97	u32 tclk_hz;
	98	u32 rate;
	99	u32 prescale;
	100	u32 reg;
	101	struct orion_spi *orion_spi;
	102
	103	orion_spi = spi_master_get_devdata(spi->master);
	104
4574b886	105	tclk_hz = clk_get_rate(orion_spi->clk);
60cadec9 SA	106
	107	/*
	108	* the supported rates are: 4,6,8...30
	109	* round up as we look for equal or less speed
	110	*/
	111	rate = DIV_ROUND_UP(tclk_hz, speed);
	112	rate = roundup(rate, 2);
	113
	114	/* check if requested speed is too small */
	115	if (rate > 30)
	116	return -EINVAL;
	117
	118	if (rate < 4)
	119	rate = 4;
	120
	121	/* Convert the rate to SPI clock divisor value. */
	122	prescale = 0x10 + rate/2;
	123
	124	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	125	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) \| prescale);
	126	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	127
	128	return 0;
	129	}
	130
b15d5d70 JG	131	static void
	132	orion_spi_mode_set(struct spi_device *spi)
	133	{
	134	u32 reg;
	135	struct orion_spi *orion_spi;
	136
	137	orion_spi = spi_master_get_devdata(spi->master);
	138
	139	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	140	reg &= ~ORION_SPI_MODE_MASK;
	141	if (spi->mode & SPI_CPOL)
	142	reg \|= ORION_SPI_MODE_CPOL;
	143	if (spi->mode & SPI_CPHA)
	144	reg \|= ORION_SPI_MODE_CPHA;
	145	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	146	}
	147
60cadec9 SA	148	/*
	149	* called only when no transfer is active on the bus
	150	*/
	151	static int
	152	orion_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	153	{
	154	struct orion_spi *orion_spi;
	155	unsigned int speed = spi->max_speed_hz;
	156	unsigned int bits_per_word = spi->bits_per_word;
	157	int rc;
	158
	159	orion_spi = spi_master_get_devdata(spi->master);
	160
	161	if ((t != NULL) && t->speed_hz)
	162	speed = t->speed_hz;
	163
	164	if ((t != NULL) && t->bits_per_word)
	165	bits_per_word = t->bits_per_word;
	166
b15d5d70 JG	167	orion_spi_mode_set(spi);
b15d5d70 JG	168
60cadec9 SA	169	rc = orion_spi_baudrate_set(spi, speed);
	170	if (rc)
	171	return rc;
	172
	173	return orion_spi_set_transfer_size(orion_spi, bits_per_word);
	174	}
	175
	176	static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
	177	{
	178	if (enable)
	179	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	180	else
	181	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	182	}
	183
	184	static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
	185	{
	186	int i;
	187
	188	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
	189	if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
	190	return 1;
	191	else
	192	udelay(1);
	193	}
	194
	195	return -1;
	196	}
	197
	198	static inline int
	199	orion_spi_write_read_8bit(struct spi_device *spi,
	200	const u8 tx_buf, u8 rx_buf)
	201	{
	202	void __iomem tx_reg, rx_reg, *int_reg;
	203	struct orion_spi *orion_spi;
	204
	205	orion_spi = spi_master_get_devdata(spi->master);
	206	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	207	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	208	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
	209
	210	/* clear the interrupt cause register */
	211	writel(0x0, int_reg);
	212
	213	if (tx_buf && *tx_buf)
	214	writel((tx_buf)++, tx_reg);
	215	else
	216	writel(0, tx_reg);
	217
	218	if (orion_spi_wait_till_ready(orion_spi) < 0) {
	219	dev_err(&spi->dev, "TXS timed out\n");
	220	return -1;
	221	}
	222
	223	if (rx_buf && *rx_buf)
	224	(rx_buf)++ = readl(rx_reg);
	225
	226	return 1;
	227	}
	228
	229	static inline int
	230	orion_spi_write_read_16bit(struct spi_device *spi,
	231	const u16 tx_buf, u16 rx_buf)
	232	{
233	void __iomem tx_reg, rx_reg, *int_reg;
234	struct orion_spi *orion_spi;
235
236	orion_spi = spi_master_get_devdata(spi->master);
237	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
238	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
239	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
240
241	/* clear the interrupt cause register */
242	writel(0x0, int_reg);
243
244	if (tx_buf && *tx_buf)
245	writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
246	else
247	writel(0, tx_reg);
248
249	if (orion_spi_wait_till_ready(orion_spi) < 0) {
250	dev_err(&spi->dev, "TXS timed out\n");
251	return -1;
252	}
253
254	if (rx_buf && *rx_buf)
255	put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
256
257	return 1;
258	}
259
260	static unsigned int
261	orion_spi_write_read(struct spi_device spi, struct spi_transfer xfer)
262	{
263	struct orion_spi *orion_spi;
264	unsigned int count;
265	int word_len;
266
267	orion_spi = spi_master_get_devdata(spi->master);
268	word_len = spi->bits_per_word;
269	count = xfer->len;
270
271	if (word_len == 8) {
272	const u8 *tx = xfer->tx_buf;
273	u8 *rx = xfer->rx_buf;
274
275	do {
276	if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
277	goto out;
278	count--;
279	} while (count);
280	} else if (word_len == 16) {
281	const u16 *tx = xfer->tx_buf;
282	u16 *rx = xfer->rx_buf;
283
284	do {
285	if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
286	goto out;
287	count -= 2;
288	} while (count);
289	}
290
291	out:
292	return xfer->len - count;
293	}
294
295
ba59a807 AL	296	static int orion_spi_transfer_one_message(struct spi_master *master,
ba59a807 AL	297	struct spi_message *m)
60cadec9	298	{
ba59a807 AL	299	struct orion_spi *orion_spi = spi_master_get_devdata(master);
	300	struct spi_device *spi = m->spi;
	301	struct spi_transfer *t = NULL;
	302	int par_override = 0;
	303	int status = 0;
	304	int cs_active = 0;
60cadec9	305
ba59a807 AL	306	/* Load defaults */
ba59a807 AL	307	status = orion_spi_setup_transfer(spi, NULL);
60cadec9	308
ba59a807 AL	309	if (status < 0)
ba59a807 AL	310	goto msg_done;
60cadec9	311
ba59a807 AL	312	list_for_each_entry(t, &m->transfers, transfer_list) {
	313	/* make sure buffer length is even when working in 16
	314	* bit mode*/
	315	if ((t->bits_per_word == 16) && (t->len & 1)) {
	316	dev_err(&spi->dev,
	317	"message rejected : "
	318	"odd data length %d while in 16 bit mode\n",
	319	t->len);
	320	status = -EIO;
	321	goto msg_done;
	322	}
60cadec9	323
ba59a807 AL	324	if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
	325	dev_err(&spi->dev,
	326	"message rejected : "
	327	"device min speed (%d Hz) exceeds "
	328	"required transfer speed (%d Hz)\n",
	329	orion_spi->min_speed, t->speed_hz);
	330	status = -EIO;
60cadec9	331	goto msg_done;
ba59a807	332	}
60cadec9	333
ba59a807 AL	334	if (par_override \|\| t->speed_hz \|\| t->bits_per_word) {
	335	par_override = 1;
	336	status = orion_spi_setup_transfer(spi, t);
	337	if (status < 0)
	338	break;
	339	if (!t->speed_hz && !t->bits_per_word)
	340	par_override = 0;
60cadec9 SA	341	}
60cadec9 SA	342
ba59a807 AL	343	if (!cs_active) {
	344	orion_spi_set_cs(orion_spi, 1);
	345	cs_active = 1;
	346	}
60cadec9	347
ba59a807 AL	348	if (t->len)
ba59a807 AL	349	m->actual_length += orion_spi_write_read(spi, t);
60cadec9	350
ba59a807 AL	351	if (t->delay_usecs)
	352	udelay(t->delay_usecs);
	353
	354	if (t->cs_change) {
	355	orion_spi_set_cs(orion_spi, 0);
	356	cs_active = 0;
	357	}
60cadec9 SA	358	}
60cadec9 SA	359
ba59a807 AL	360	msg_done:
	361	if (cs_active)
	362	orion_spi_set_cs(orion_spi, 0);
	363
	364	m->status = status;
	365	spi_finalize_current_message(master);
	366
	367	return 0;
60cadec9 SA	368	}
60cadec9 SA	369
2deff8d6	370	static int orion_spi_reset(struct orion_spi *orion_spi)
60cadec9 SA	371	{
	372	/* Verify that the CS is deasserted */
	373	orion_spi_set_cs(orion_spi, 0);
	374
	375	return 0;
	376	}
	377
	378	static int orion_spi_setup(struct spi_device *spi)
	379	{
	380	struct orion_spi *orion_spi;
	381
	382	orion_spi = spi_master_get_devdata(spi->master);
	383
60cadec9 SA	384	if ((spi->max_speed_hz == 0)
	385	\|\| (spi->max_speed_hz > orion_spi->max_speed))
	386	spi->max_speed_hz = orion_spi->max_speed;
	387
	388	if (spi->max_speed_hz < orion_spi->min_speed) {
	389	dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
	390	spi->max_speed_hz);
	391	return -EINVAL;
	392	}
	393
	394	/*
	395	* baudrate & width will be set orion_spi_setup_transfer
	396	*/
	397	return 0;
	398	}
	399
2deff8d6	400	static int orion_spi_probe(struct platform_device *pdev)
60cadec9 SA	401	{
	402	struct spi_master *master;
	403	struct orion_spi *spi;
	404	struct resource *r;
4574b886	405	unsigned long tclk_hz;
60cadec9	406	int status = 0;
f814f9ac AL	407	const u32 *iprop;
f814f9ac AL	408	int size;
60cadec9	409
3fed8068	410	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
60cadec9 SA	411	if (master == NULL) {
	412	dev_dbg(&pdev->dev, "master allocation failed\n");
	413	return -ENOMEM;
	414	}
	415
	416	if (pdev->id != -1)
	417	master->bus_num = pdev->id;
f814f9ac AL	418	if (pdev->dev.of_node) {
	419	iprop = of_get_property(pdev->dev.of_node, "cell-index",
	420	&size);
	421	if (iprop && size == sizeof(*iprop))
	422	master->bus_num = *iprop;
	423	}
60cadec9	424
e7db06b5	425	/* we support only mode 0, and no options */
b15d5d70	426	master->mode_bits = SPI_CPHA \| SPI_CPOL;
e7db06b5	427
60cadec9	428	master->setup = orion_spi_setup;
ba59a807	429	master->transfer_one_message = orion_spi_transfer_one_message;
60cadec9 SA	430	master->num_chipselect = ORION_NUM_CHIPSELECTS;
60cadec9 SA	431
24b5a82c	432	platform_set_drvdata(pdev, master);
60cadec9 SA	433
	434	spi = spi_master_get_devdata(master);
	435	spi->master = master;
60cadec9	436
bb489841	437	spi->clk = devm_clk_get(&pdev->dev, NULL);
4574b886 AL	438	if (IS_ERR(spi->clk)) {
	439	status = PTR_ERR(spi->clk);
	440	goto out;
	441	}
	442
	443	clk_prepare(spi->clk);
	444	clk_enable(spi->clk);
	445	tclk_hz = clk_get_rate(spi->clk);
	446	spi->max_speed = DIV_ROUND_UP(tclk_hz, 4);
	447	spi->min_speed = DIV_ROUND_UP(tclk_hz, 30);
60cadec9 SA	448
60cadec9 SA	449	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1729ce34 MB	450	spi->base = devm_ioremap_resource(&pdev->dev, r);
	451	if (IS_ERR(spi->base)) {
	452	status = PTR_ERR(spi->base);
4574b886	453	goto out_rel_clk;
60cadec9 SA	454	}
60cadec9 SA	455
60cadec9	456	if (orion_spi_reset(spi) < 0)
1729ce34	457	goto out_rel_clk;
60cadec9	458
f814f9ac	459	master->dev.of_node = pdev->dev.of_node;
4bd3d8e3	460	status = devm_spi_register_master(&pdev->dev, master);
60cadec9	461	if (status < 0)
1729ce34	462	goto out_rel_clk;
60cadec9 SA	463
	464	return status;
	465
4574b886 AL	466	out_rel_clk:
4574b886 AL	467	clk_disable_unprepare(spi->clk);
60cadec9 SA	468	out:
	469	spi_master_put(master);
	470	return status;
	471	}
	472
	473
2deff8d6	474	static int orion_spi_remove(struct platform_device *pdev)
60cadec9 SA	475	{
60cadec9 SA	476	struct spi_master *master;
ba59a807	477	struct orion_spi *spi;
60cadec9	478
24b5a82c	479	master = platform_get_drvdata(pdev);
60cadec9 SA	480	spi = spi_master_get_devdata(master);
60cadec9 SA	481
4574b886	482	clk_disable_unprepare(spi->clk);
4574b886	483
60cadec9 SA	484	return 0;
	485	}
	486
	487	MODULE_ALIAS("platform:" DRIVER_NAME);
	488
fd4a319b	489	static const struct of_device_id orion_spi_of_match_table[] = {
f814f9ac AL	490	{ .compatible = "marvell,orion-spi", },
	491	{}
	492	};
	493	MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
	494
60cadec9 SA	495	static struct platform_driver orion_spi_driver = {
	496	.driver = {
	497	.name = DRIVER_NAME,
	498	.owner = THIS_MODULE,
f814f9ac	499	.of_match_table = of_match_ptr(orion_spi_of_match_table),
60cadec9	500	},
41ab724a	501	.probe = orion_spi_probe,
2deff8d6	502	.remove = orion_spi_remove,
60cadec9 SA	503	};
60cadec9 SA	504
41ab724a	505	module_platform_driver(orion_spi_driver);
60cadec9 SA	506
	507	MODULE_DESCRIPTION("Orion SPI driver");
	508	MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
	509	MODULE_LICENSE("GPL");