[deliverable/linux.git] / drivers / spi / spi-orion.c

/*
 * Marvell Orion SPI controller driver
 *
 * Author: Shadi Ammouri <shadi@marvell.com>
 * Copyright (C) 2007-2008 Marvell Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/sizes.h>
#include <asm/unaligned.h>

#define DRIVER_NAME			"orion_spi"

#define ORION_NUM_CHIPSELECTS		1 /* only one slave is supported*/
#define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */

#define ORION_SPI_IF_CTRL_REG		0x00
#define ORION_SPI_IF_CONFIG_REG		0x04
#define ORION_SPI_DATA_OUT_REG		0x08
#define ORION_SPI_DATA_IN_REG		0x0c
#define ORION_SPI_INT_CAUSE_REG		0x10

#define ORION_SPI_MODE_CPOL		(1 << 11)
#define ORION_SPI_MODE_CPHA		(1 << 12)
#define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
#define ORION_SPI_CLK_PRESCALE_MASK	0x1F
#define ORION_SPI_MODE_MASK		(ORION_SPI_MODE_CPOL | \
					 ORION_SPI_MODE_CPHA)

struct orion_spi {
	struct spi_master	*master;
	void __iomem		*base;
	struct clk              *clk;
};

static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
{
	return orion_spi->base + reg;
}

static inline void
orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val |= mask;
	writel(val, reg_addr);
}

static inline void
orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val &= ~mask;
	writel(val, reg_addr);
}

static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
{
	u32 tclk_hz;
	u32 rate;
	u32 prescale;
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	tclk_hz = clk_get_rate(orion_spi->clk);

	/*
	 * the supported rates are: 4,6,8...30
	 * round up as we look for equal or less speed
	 */
	rate = DIV_ROUND_UP(tclk_hz, speed);
	rate = roundup(rate, 2);

	/* check if requested speed is too small */
	if (rate > 30)
		return -EINVAL;

	if (rate < 4)
		rate = 4;

	/* Convert the rate to SPI clock divisor value.	*/
	prescale = 0x10 + rate/2;

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));

	return 0;
}

static void
orion_spi_mode_set(struct spi_device *spi)
{
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg &= ~ORION_SPI_MODE_MASK;
	if (spi->mode & SPI_CPOL)
		reg |= ORION_SPI_MODE_CPOL;
	if (spi->mode & SPI_CPHA)
		reg |= ORION_SPI_MODE_CPHA;
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
}

/*
 * called only when no transfer is active on the bus
 */
static int
orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct orion_spi *orion_spi;
	unsigned int speed = spi->max_speed_hz;
	unsigned int bits_per_word = spi->bits_per_word;
	int	rc;

	orion_spi = spi_master_get_devdata(spi->master);

	if ((t != NULL) && t->speed_hz)
		speed = t->speed_hz;

	if ((t != NULL) && t->bits_per_word)
		bits_per_word = t->bits_per_word;

	orion_spi_mode_set(spi);

	rc = orion_spi_baudrate_set(spi, speed);
	if (rc)
		return rc;

	if (bits_per_word == 16)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);

	return 0;
}

static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
{
	if (enable)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
}

static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
{
	int i;

	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
			return 1;
		else
			udelay(1);
	}

	return -1;
}

static inline int
orion_spi_write_read_8bit(struct spi_device *spi,
			  const u8 **tx_buf, u8 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(*(*tx_buf)++, tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		*(*rx_buf)++ = readl(rx_reg);

	return 1;
}

static inline int
orion_spi_write_read_16bit(struct spi_device *spi,
			   const u16 **tx_buf, u16 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);

	return 1;
}

static unsigned int
orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
{
	unsigned int count;
	int word_len;

	word_len = spi->bits_per_word;
	count = xfer->len;

	if (word_len == 8) {
		const u8 *tx = xfer->tx_buf;
		u8 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
				goto out;
			count--;
		} while (count);
	} else if (word_len == 16) {
		const u16 *tx = xfer->tx_buf;
		u16 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
				goto out;
			count -= 2;
		} while (count);
	}

out:
	return xfer->len - count;
}


static int orion_spi_transfer_one_message(struct spi_master *master,
					   struct spi_message *m)
{
	struct orion_spi *orion_spi = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	struct spi_transfer *t = NULL;
	int par_override = 0;
	int status = 0;
	int cs_active = 0;

	/* Load defaults */
	status = orion_spi_setup_transfer(spi, NULL);

	if (status < 0)
		goto msg_done;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (par_override || t->speed_hz || t->bits_per_word) {
			par_override = 1;
			status = orion_spi_setup_transfer(spi, t);
			if (status < 0)
				break;
			if (!t->speed_hz && !t->bits_per_word)
				par_override = 0;
		}

		if (!cs_active) {
			orion_spi_set_cs(orion_spi, 1);
			cs_active = 1;
		}

		if (t->len)
			m->actual_length += orion_spi_write_read(spi, t);

		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (t->cs_change) {
			orion_spi_set_cs(orion_spi, 0);
			cs_active = 0;
		}
	}

msg_done:
	if (cs_active)
		orion_spi_set_cs(orion_spi, 0);

	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static int orion_spi_reset(struct orion_spi *orion_spi)
{
	/* Verify that the CS is deasserted */
	orion_spi_set_cs(orion_spi, 0);

	return 0;
}

static int orion_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;
	struct resource *r;
	unsigned long tclk_hz;
	int status = 0;
	const u32 *iprop;
	int size;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (master == NULL) {
		dev_dbg(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	if (pdev->id != -1)
		master->bus_num = pdev->id;
	if (pdev->dev.of_node) {
		iprop = of_get_property(pdev->dev.of_node, "cell-index",
					&size);
		if (iprop && size == sizeof(*iprop))
			master->bus_num = *iprop;
	}

	/* we support only mode 0, and no options */
	master->mode_bits = SPI_CPHA | SPI_CPOL;

	master->transfer_one_message = orion_spi_transfer_one_message;
	master->num_chipselect = ORION_NUM_CHIPSELECTS;
	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);

	platform_set_drvdata(pdev, master);

	spi = spi_master_get_devdata(master);
	spi->master = master;

	spi->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(spi->clk)) {
		status = PTR_ERR(spi->clk);
		goto out;
	}

	clk_prepare(spi->clk);
	clk_enable(spi->clk);
	tclk_hz = clk_get_rate(spi->clk);
	master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	spi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(spi->base)) {
		status = PTR_ERR(spi->base);
		goto out_rel_clk;
	}

	if (orion_spi_reset(spi) < 0)
		goto out_rel_clk;

	master->dev.of_node = pdev->dev.of_node;
	status = devm_spi_register_master(&pdev->dev, master);
	if (status < 0)
		goto out_rel_clk;

	return status;

out_rel_clk:
	clk_disable_unprepare(spi->clk);
out:
	spi_master_put(master);
	return status;
}


static int orion_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;

	master = platform_get_drvdata(pdev);
	spi = spi_master_get_devdata(master);

	clk_disable_unprepare(spi->clk);

	return 0;
}

MODULE_ALIAS("platform:" DRIVER_NAME);

static const struct of_device_id orion_spi_of_match_table[] = {
	{ .compatible = "marvell,orion-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);

static struct platform_driver orion_spi_driver = {
	.driver = {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(orion_spi_of_match_table),
	},
	.probe		= orion_spi_probe,
	.remove		= orion_spi_remove,
};

module_platform_driver(orion_spi_driver);

MODULE_DESCRIPTION("Orion SPI driver");
MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
60cadec9	1	/*
ca632f55	2	* Marvell Orion SPI controller driver
60cadec9 SA	3	*
	4	* Author: Shadi Ammouri <shadi@marvell.com>
	5	* Copyright (C) 2007-2008 Marvell Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
60cadec9 SA	12	#include <linux/interrupt.h>
	13	#include <linux/delay.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/err.h>
	16	#include <linux/io.h>
	17	#include <linux/spi/spi.h>
d7614de4	18	#include <linux/module.h>
f814f9ac	19	#include <linux/of.h>
4574b886	20	#include <linux/clk.h>
895248f8	21	#include <linux/sizes.h>
60cadec9 SA	22	#include <asm/unaligned.h>
	23
	24	#define DRIVER_NAME "orion_spi"
	25
	26	#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
	27	#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
	28
	29	#define ORION_SPI_IF_CTRL_REG 0x00
	30	#define ORION_SPI_IF_CONFIG_REG 0x04
	31	#define ORION_SPI_DATA_OUT_REG 0x08
	32	#define ORION_SPI_DATA_IN_REG 0x0c
	33	#define ORION_SPI_INT_CAUSE_REG 0x10
	34
b15d5d70 JG	35	#define ORION_SPI_MODE_CPOL (1 << 11)
b15d5d70 JG	36	#define ORION_SPI_MODE_CPHA (1 << 12)
60cadec9 SA	37	#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
60cadec9 SA	38	#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
b15d5d70 JG	39	#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL \| \
b15d5d70 JG	40	ORION_SPI_MODE_CPHA)
60cadec9 SA	41
60cadec9 SA	42	struct orion_spi {
60cadec9 SA	43	struct spi_master *master;
60cadec9 SA	44	void __iomem *base;
4574b886	45	struct clk *clk;
60cadec9 SA	46	};
60cadec9 SA	47
60cadec9 SA	48	static inline void __iomem spi_reg(struct orion_spi orion_spi, u32 reg)
	49	{
	50	return orion_spi->base + reg;
	51	}
	52
	53	static inline void
	54	orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	55	{
	56	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	57	u32 val;
	58
	59	val = readl(reg_addr);
	60	val \|= mask;
	61	writel(val, reg_addr);
	62	}
	63
	64	static inline void
	65	orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	66	{
	67	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	68	u32 val;
	69
	70	val = readl(reg_addr);
	71	val &= ~mask;
	72	writel(val, reg_addr);
	73	}
	74
60cadec9 SA	75	static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
	76	{
	77	u32 tclk_hz;
	78	u32 rate;
	79	u32 prescale;
	80	u32 reg;
	81	struct orion_spi *orion_spi;
	82
	83	orion_spi = spi_master_get_devdata(spi->master);
	84
4574b886	85	tclk_hz = clk_get_rate(orion_spi->clk);
60cadec9 SA	86
	87	/*
	88	* the supported rates are: 4,6,8...30
	89	* round up as we look for equal or less speed
	90	*/
	91	rate = DIV_ROUND_UP(tclk_hz, speed);
	92	rate = roundup(rate, 2);
	93
	94	/* check if requested speed is too small */
	95	if (rate > 30)
	96	return -EINVAL;
	97
	98	if (rate < 4)
	99	rate = 4;
	100
	101	/* Convert the rate to SPI clock divisor value. */
	102	prescale = 0x10 + rate/2;
	103
	104	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	105	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) \| prescale);
	106	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	107
	108	return 0;
	109	}
	110
b15d5d70 JG	111	static void
	112	orion_spi_mode_set(struct spi_device *spi)
	113	{
	114	u32 reg;
	115	struct orion_spi *orion_spi;
	116
	117	orion_spi = spi_master_get_devdata(spi->master);
	118
	119	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	120	reg &= ~ORION_SPI_MODE_MASK;
	121	if (spi->mode & SPI_CPOL)
	122	reg \|= ORION_SPI_MODE_CPOL;
	123	if (spi->mode & SPI_CPHA)
	124	reg \|= ORION_SPI_MODE_CPHA;
	125	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	126	}
	127
60cadec9 SA	128	/*
	129	* called only when no transfer is active on the bus
	130	*/
	131	static int
	132	orion_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	133	{
	134	struct orion_spi *orion_spi;
	135	unsigned int speed = spi->max_speed_hz;
	136	unsigned int bits_per_word = spi->bits_per_word;
	137	int rc;
	138
	139	orion_spi = spi_master_get_devdata(spi->master);
	140
	141	if ((t != NULL) && t->speed_hz)
	142	speed = t->speed_hz;
	143
	144	if ((t != NULL) && t->bits_per_word)
	145	bits_per_word = t->bits_per_word;
	146
b15d5d70 JG	147	orion_spi_mode_set(spi);
b15d5d70 JG	148
60cadec9 SA	149	rc = orion_spi_baudrate_set(spi, speed);
	150	if (rc)
	151	return rc;
	152
495b3358 AL	153	if (bits_per_word == 16)
	154	orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	155	ORION_SPI_IF_8_16_BIT_MODE);
	156	else
	157	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	158	ORION_SPI_IF_8_16_BIT_MODE);
	159
	160	return 0;
60cadec9 SA	161	}
	162
	163	static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
	164	{
	165	if (enable)
	166	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	167	else
	168	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	169	}
	170
	171	static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
	172	{
	173	int i;
	174
	175	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
	176	if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
	177	return 1;
	178	else
	179	udelay(1);
	180	}
	181
	182	return -1;
	183	}
	184
	185	static inline int
	186	orion_spi_write_read_8bit(struct spi_device *spi,
	187	const u8 tx_buf, u8 rx_buf)
	188	{
	189	void __iomem tx_reg, rx_reg, *int_reg;
	190	struct orion_spi *orion_spi;
	191
	192	orion_spi = spi_master_get_devdata(spi->master);
	193	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	194	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	195	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
	196
	197	/* clear the interrupt cause register */
	198	writel(0x0, int_reg);
	199
	200	if (tx_buf && *tx_buf)
	201	writel((tx_buf)++, tx_reg);
	202	else
	203	writel(0, tx_reg);
	204
	205	if (orion_spi_wait_till_ready(orion_spi) < 0) {
	206	dev_err(&spi->dev, "TXS timed out\n");
	207	return -1;
	208	}
	209
	210	if (rx_buf && *rx_buf)
	211	(rx_buf)++ = readl(rx_reg);
	212
	213	return 1;
	214	}
	215
	216	static inline int
	217	orion_spi_write_read_16bit(struct spi_device *spi,
	218	const u16 tx_buf, u16 rx_buf)
	219	{
	220	void __iomem tx_reg, rx_reg, *int_reg;
	221	struct orion_spi *orion_spi;
	222
	223	orion_spi = spi_master_get_devdata(spi->master);
	224	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
225	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
226	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
227
228	/* clear the interrupt cause register */
229	writel(0x0, int_reg);
230
231	if (tx_buf && *tx_buf)
232	writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
233	else
234	writel(0, tx_reg);
235
236	if (orion_spi_wait_till_ready(orion_spi) < 0) {
237	dev_err(&spi->dev, "TXS timed out\n");
238	return -1;
239	}
240
241	if (rx_buf && *rx_buf)
242	put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
243
244	return 1;
245	}
246
247	static unsigned int
248	orion_spi_write_read(struct spi_device spi, struct spi_transfer xfer)
249	{
60cadec9 SA	250	unsigned int count;
	251	int word_len;
	252
60cadec9 SA	253	word_len = spi->bits_per_word;
	254	count = xfer->len;
	255
	256	if (word_len == 8) {
	257	const u8 *tx = xfer->tx_buf;
	258	u8 *rx = xfer->rx_buf;
	259
	260	do {
	261	if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
	262	goto out;
	263	count--;
	264	} while (count);
	265	} else if (word_len == 16) {
	266	const u16 *tx = xfer->tx_buf;
	267	u16 *rx = xfer->rx_buf;
	268
	269	do {
	270	if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
	271	goto out;
	272	count -= 2;
	273	} while (count);
	274	}
	275
	276	out:
	277	return xfer->len - count;
	278	}
	279
	280
ba59a807 AL	281	static int orion_spi_transfer_one_message(struct spi_master *master,
ba59a807 AL	282	struct spi_message *m)
60cadec9	283	{
ba59a807 AL	284	struct orion_spi *orion_spi = spi_master_get_devdata(master);
	285	struct spi_device *spi = m->spi;
	286	struct spi_transfer *t = NULL;
	287	int par_override = 0;
	288	int status = 0;
	289	int cs_active = 0;
60cadec9	290
ba59a807 AL	291	/* Load defaults */
ba59a807 AL	292	status = orion_spi_setup_transfer(spi, NULL);
60cadec9	293
ba59a807 AL	294	if (status < 0)
ba59a807 AL	295	goto msg_done;
60cadec9	296
ba59a807	297	list_for_each_entry(t, &m->transfers, transfer_list) {
ba59a807 AL	298	if (par_override \|\| t->speed_hz \|\| t->bits_per_word) {
	299	par_override = 1;
	300	status = orion_spi_setup_transfer(spi, t);
	301	if (status < 0)
	302	break;
	303	if (!t->speed_hz && !t->bits_per_word)
	304	par_override = 0;
60cadec9 SA	305	}
60cadec9 SA	306
ba59a807 AL	307	if (!cs_active) {
	308	orion_spi_set_cs(orion_spi, 1);
	309	cs_active = 1;
	310	}
60cadec9	311
ba59a807 AL	312	if (t->len)
ba59a807 AL	313	m->actual_length += orion_spi_write_read(spi, t);
60cadec9	314
ba59a807 AL	315	if (t->delay_usecs)
	316	udelay(t->delay_usecs);
	317
	318	if (t->cs_change) {
	319	orion_spi_set_cs(orion_spi, 0);
	320	cs_active = 0;
	321	}
60cadec9 SA	322	}
60cadec9 SA	323
ba59a807 AL	324	msg_done:
	325	if (cs_active)
	326	orion_spi_set_cs(orion_spi, 0);
	327
	328	m->status = status;
	329	spi_finalize_current_message(master);
	330
	331	return 0;
60cadec9 SA	332	}
60cadec9 SA	333
2deff8d6	334	static int orion_spi_reset(struct orion_spi *orion_spi)
60cadec9 SA	335	{
	336	/* Verify that the CS is deasserted */
	337	orion_spi_set_cs(orion_spi, 0);
	338
	339	return 0;
	340	}
	341
2deff8d6	342	static int orion_spi_probe(struct platform_device *pdev)
60cadec9 SA	343	{
	344	struct spi_master *master;
	345	struct orion_spi *spi;
	346	struct resource *r;
4574b886	347	unsigned long tclk_hz;
60cadec9	348	int status = 0;
f814f9ac AL	349	const u32 *iprop;
f814f9ac AL	350	int size;
60cadec9	351
3fed8068	352	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
60cadec9 SA	353	if (master == NULL) {
	354	dev_dbg(&pdev->dev, "master allocation failed\n");
	355	return -ENOMEM;
	356	}
	357
	358	if (pdev->id != -1)
	359	master->bus_num = pdev->id;
f814f9ac AL	360	if (pdev->dev.of_node) {
	361	iprop = of_get_property(pdev->dev.of_node, "cell-index",
	362	&size);
	363	if (iprop && size == sizeof(*iprop))
	364	master->bus_num = *iprop;
	365	}
60cadec9	366
e7db06b5	367	/* we support only mode 0, and no options */
b15d5d70	368	master->mode_bits = SPI_CPHA \| SPI_CPOL;
e7db06b5	369
ba59a807	370	master->transfer_one_message = orion_spi_transfer_one_message;
60cadec9	371	master->num_chipselect = ORION_NUM_CHIPSELECTS;
495b3358	372	master->bits_per_word_mask = SPI_BPW_MASK(8) \| SPI_BPW_MASK(16);
60cadec9	373
24b5a82c	374	platform_set_drvdata(pdev, master);
60cadec9 SA	375
	376	spi = spi_master_get_devdata(master);
	377	spi->master = master;
60cadec9	378
bb489841	379	spi->clk = devm_clk_get(&pdev->dev, NULL);
4574b886 AL	380	if (IS_ERR(spi->clk)) {
	381	status = PTR_ERR(spi->clk);
	382	goto out;
	383	}
	384
	385	clk_prepare(spi->clk);
	386	clk_enable(spi->clk);
	387	tclk_hz = clk_get_rate(spi->clk);
b52a37f5 AL	388	master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
b52a37f5 AL	389	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
60cadec9 SA	390
60cadec9 SA	391	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1729ce34 MB	392	spi->base = devm_ioremap_resource(&pdev->dev, r);
	393	if (IS_ERR(spi->base)) {
	394	status = PTR_ERR(spi->base);
4574b886	395	goto out_rel_clk;
60cadec9 SA	396	}
60cadec9 SA	397
60cadec9	398	if (orion_spi_reset(spi) < 0)
1729ce34	399	goto out_rel_clk;
60cadec9	400
f814f9ac	401	master->dev.of_node = pdev->dev.of_node;
4bd3d8e3	402	status = devm_spi_register_master(&pdev->dev, master);
60cadec9	403	if (status < 0)
1729ce34	404	goto out_rel_clk;
60cadec9 SA	405
	406	return status;
	407
4574b886 AL	408	out_rel_clk:
4574b886 AL	409	clk_disable_unprepare(spi->clk);
60cadec9 SA	410	out:
	411	spi_master_put(master);
	412	return status;
	413	}
	414
	415
2deff8d6	416	static int orion_spi_remove(struct platform_device *pdev)
60cadec9 SA	417	{
60cadec9 SA	418	struct spi_master *master;
ba59a807	419	struct orion_spi *spi;
60cadec9	420
24b5a82c	421	master = platform_get_drvdata(pdev);
60cadec9 SA	422	spi = spi_master_get_devdata(master);
60cadec9 SA	423
4574b886	424	clk_disable_unprepare(spi->clk);
4574b886	425
60cadec9 SA	426	return 0;
	427	}
	428
	429	MODULE_ALIAS("platform:" DRIVER_NAME);
	430
fd4a319b	431	static const struct of_device_id orion_spi_of_match_table[] = {
f814f9ac AL	432	{ .compatible = "marvell,orion-spi", },
	433	{}
	434	};
	435	MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
	436
60cadec9 SA	437	static struct platform_driver orion_spi_driver = {
	438	.driver = {
	439	.name = DRIVER_NAME,
	440	.owner = THIS_MODULE,
f814f9ac	441	.of_match_table = of_match_ptr(orion_spi_of_match_table),
60cadec9	442	},
41ab724a	443	.probe = orion_spi_probe,
2deff8d6	444	.remove = orion_spi_remove,
60cadec9 SA	445	};
60cadec9 SA	446
41ab724a	447	module_platform_driver(orion_spi_driver);
60cadec9 SA	448
	449	MODULE_DESCRIPTION("Orion SPI driver");
	450	MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
	451	MODULE_LICENSE("GPL");