[deliverable/linux.git] / drivers / spi / spi-orion.c

/*
 * Marvell Orion SPI controller driver
 *
 * Author: Shadi Ammouri <shadi@marvell.com>
 * Copyright (C) 2007-2008 Marvell Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/sizes.h>
#include <asm/unaligned.h>

#define DRIVER_NAME			"orion_spi"

/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
#define SPI_AUTOSUSPEND_TIMEOUT		200

#define ORION_NUM_CHIPSELECTS		1 /* only one slave is supported*/
#define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */

#define ORION_SPI_IF_CTRL_REG		0x00
#define ORION_SPI_IF_CONFIG_REG		0x04
#define ORION_SPI_DATA_OUT_REG		0x08
#define ORION_SPI_DATA_IN_REG		0x0c
#define ORION_SPI_INT_CAUSE_REG		0x10

#define ORION_SPI_MODE_CPOL		(1 << 11)
#define ORION_SPI_MODE_CPHA		(1 << 12)
#define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
#define ORION_SPI_CLK_PRESCALE_MASK	0x1F
#define ORION_SPI_MODE_MASK		(ORION_SPI_MODE_CPOL | \
					 ORION_SPI_MODE_CPHA)

struct orion_spi {
	struct spi_master	*master;
	void __iomem		*base;
	struct clk              *clk;
};

static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
{
	return orion_spi->base + reg;
}

static inline void
orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val |= mask;
	writel(val, reg_addr);
}

static inline void
orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
{
	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	u32 val;

	val = readl(reg_addr);
	val &= ~mask;
	writel(val, reg_addr);
}

static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
{
	u32 tclk_hz;
	u32 rate;
	u32 prescale;
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	tclk_hz = clk_get_rate(orion_spi->clk);

	/*
	 * the supported rates are: 4,6,8...30
	 * round up as we look for equal or less speed
	 */
	rate = DIV_ROUND_UP(tclk_hz, speed);
	rate = roundup(rate, 2);

	/* check if requested speed is too small */
	if (rate > 30)
		return -EINVAL;

	if (rate < 4)
		rate = 4;

	/* Convert the rate to SPI clock divisor value.	*/
	prescale = 0x10 + rate/2;

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));

	return 0;
}

static void
orion_spi_mode_set(struct spi_device *spi)
{
	u32 reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);

	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	reg &= ~ORION_SPI_MODE_MASK;
	if (spi->mode & SPI_CPOL)
		reg |= ORION_SPI_MODE_CPOL;
	if (spi->mode & SPI_CPHA)
		reg |= ORION_SPI_MODE_CPHA;
	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
}

/*
 * called only when no transfer is active on the bus
 */
static int
orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct orion_spi *orion_spi;
	unsigned int speed = spi->max_speed_hz;
	unsigned int bits_per_word = spi->bits_per_word;
	int	rc;

	orion_spi = spi_master_get_devdata(spi->master);

	if ((t != NULL) && t->speed_hz)
		speed = t->speed_hz;

	if ((t != NULL) && t->bits_per_word)
		bits_per_word = t->bits_per_word;

	orion_spi_mode_set(spi);

	rc = orion_spi_baudrate_set(spi, speed);
	if (rc)
		return rc;

	if (bits_per_word == 16)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
				  ORION_SPI_IF_8_16_BIT_MODE);

	return 0;
}

static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
{
	if (enable)
		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	else
		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
}

static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
{
	int i;

	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
			return 1;
		else
			udelay(1);
	}

	return -1;
}

static inline int
orion_spi_write_read_8bit(struct spi_device *spi,
			  const u8 **tx_buf, u8 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(*(*tx_buf)++, tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		*(*rx_buf)++ = readl(rx_reg);

	return 1;
}

static inline int
orion_spi_write_read_16bit(struct spi_device *spi,
			   const u16 **tx_buf, u16 **rx_buf)
{
	void __iomem *tx_reg, *rx_reg, *int_reg;
	struct orion_spi *orion_spi;

	orion_spi = spi_master_get_devdata(spi->master);
	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);

	/* clear the interrupt cause register */
	writel(0x0, int_reg);

	if (tx_buf && *tx_buf)
		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
	else
		writel(0, tx_reg);

	if (orion_spi_wait_till_ready(orion_spi) < 0) {
		dev_err(&spi->dev, "TXS timed out\n");
		return -1;
	}

	if (rx_buf && *rx_buf)
		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);

	return 1;
}

static unsigned int
orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
{
	unsigned int count;
	int word_len;

	word_len = spi->bits_per_word;
	count = xfer->len;

	if (word_len == 8) {
		const u8 *tx = xfer->tx_buf;
		u8 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
				goto out;
			count--;
		} while (count);
	} else if (word_len == 16) {
		const u16 *tx = xfer->tx_buf;
		u16 *rx = xfer->rx_buf;

		do {
			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
				goto out;
			count -= 2;
		} while (count);
	}

out:
	return xfer->len - count;
}

static int orion_spi_transfer_one_message(struct spi_master *master,
					   struct spi_message *m)
{
	struct orion_spi *orion_spi = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	struct spi_transfer *t = NULL;
	int par_override = 0;
	int status = 0;
	int cs_active = 0;

	/* Load defaults */
	status = orion_spi_setup_transfer(spi, NULL);

	if (status < 0)
		goto msg_done;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (par_override || t->speed_hz || t->bits_per_word) {
			par_override = 1;
			status = orion_spi_setup_transfer(spi, t);
			if (status < 0)
				break;
			if (!t->speed_hz && !t->bits_per_word)
				par_override = 0;
		}

		if (!cs_active) {
			orion_spi_set_cs(orion_spi, 1);
			cs_active = 1;
		}

		if (t->len)
			m->actual_length += orion_spi_write_read(spi, t);

		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (t->cs_change) {
			orion_spi_set_cs(orion_spi, 0);
			cs_active = 0;
		}
	}

msg_done:
	if (cs_active)
		orion_spi_set_cs(orion_spi, 0);

	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static int orion_spi_reset(struct orion_spi *orion_spi)
{
	/* Verify that the CS is deasserted */
	orion_spi_set_cs(orion_spi, 0);

	return 0;
}

static int orion_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct orion_spi *spi;
	struct resource *r;
	unsigned long tclk_hz;
	int status = 0;
	const u32 *iprop;
	int size;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (master == NULL) {
		dev_dbg(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	if (pdev->id != -1)
		master->bus_num = pdev->id;
	if (pdev->dev.of_node) {
		iprop = of_get_property(pdev->dev.of_node, "cell-index",
					&size);
		if (iprop && size == sizeof(*iprop))
			master->bus_num = *iprop;
	}

	/* we support only mode 0, and no options */
	master->mode_bits = SPI_CPHA | SPI_CPOL;

	master->transfer_one_message = orion_spi_transfer_one_message;
	master->num_chipselect = ORION_NUM_CHIPSELECTS;
	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
	master->auto_runtime_pm = true;

	platform_set_drvdata(pdev, master);

	spi = spi_master_get_devdata(master);
	spi->master = master;

	spi->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(spi->clk)) {
		status = PTR_ERR(spi->clk);
		goto out;
	}

	status = clk_prepare_enable(spi->clk);
	if (status)
		goto out;

	tclk_hz = clk_get_rate(spi->clk);
	master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	spi->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(spi->base)) {
		status = PTR_ERR(spi->base);
		goto out_rel_clk;
	}

	pm_runtime_set_active(&pdev->dev);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
	pm_runtime_enable(&pdev->dev);

	if (orion_spi_reset(spi) < 0)
		goto out_rel_pm;

	pm_runtime_mark_last_busy(&pdev->dev);
	pm_runtime_put_autosuspend(&pdev->dev);

	master->dev.of_node = pdev->dev.of_node;
	status = spi_register_master(master);
	if (status < 0)
		goto out_rel_pm;

	return status;

out_rel_pm:
	pm_runtime_disable(&pdev->dev);
out_rel_clk:
	clk_disable_unprepare(spi->clk);
out:
	spi_master_put(master);
	return status;
}


static int orion_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct orion_spi *spi = spi_master_get_devdata(master);

	pm_runtime_get_sync(&pdev->dev);
	clk_disable_unprepare(spi->clk);

	spi_unregister_master(master);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

MODULE_ALIAS("platform:" DRIVER_NAME);

#ifdef CONFIG_PM_RUNTIME
static int orion_spi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct orion_spi *spi = spi_master_get_devdata(master);

	clk_disable_unprepare(spi->clk);
	return 0;
}

static int orion_spi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct orion_spi *spi = spi_master_get_devdata(master);

	return clk_prepare_enable(spi->clk);
}
#endif

static const struct dev_pm_ops orion_spi_pm_ops = {
	SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
			   orion_spi_runtime_resume,
			   NULL)
};

static const struct of_device_id orion_spi_of_match_table[] = {
	{ .compatible = "marvell,orion-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);

static struct platform_driver orion_spi_driver = {
	.driver = {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.pm	= &orion_spi_pm_ops,
		.of_match_table = of_match_ptr(orion_spi_of_match_table),
	},
	.probe		= orion_spi_probe,
	.remove		= orion_spi_remove,
};

module_platform_driver(orion_spi_driver);

MODULE_DESCRIPTION("Orion SPI driver");
MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
60cadec9	1	/*
ca632f55	2	* Marvell Orion SPI controller driver
60cadec9 SA	3	*
	4	* Author: Shadi Ammouri <shadi@marvell.com>
	5	* Copyright (C) 2007-2008 Marvell Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
60cadec9 SA	12	#include <linux/interrupt.h>
	13	#include <linux/delay.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/err.h>
	16	#include <linux/io.h>
	17	#include <linux/spi/spi.h>
d7614de4	18	#include <linux/module.h>
5c678694	19	#include <linux/pm_runtime.h>
f814f9ac	20	#include <linux/of.h>
4574b886	21	#include <linux/clk.h>
895248f8	22	#include <linux/sizes.h>
60cadec9 SA	23	#include <asm/unaligned.h>
	24
	25	#define DRIVER_NAME "orion_spi"
	26
5c678694 RK	27	/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
	28	#define SPI_AUTOSUSPEND_TIMEOUT 200
	29
60cadec9 SA	30	#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
	31	#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
	32
	33	#define ORION_SPI_IF_CTRL_REG 0x00
	34	#define ORION_SPI_IF_CONFIG_REG 0x04
	35	#define ORION_SPI_DATA_OUT_REG 0x08
	36	#define ORION_SPI_DATA_IN_REG 0x0c
	37	#define ORION_SPI_INT_CAUSE_REG 0x10
	38
b15d5d70 JG	39	#define ORION_SPI_MODE_CPOL (1 << 11)
b15d5d70 JG	40	#define ORION_SPI_MODE_CPHA (1 << 12)
60cadec9 SA	41	#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
60cadec9 SA	42	#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
b15d5d70 JG	43	#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL \| \
b15d5d70 JG	44	ORION_SPI_MODE_CPHA)
60cadec9 SA	45
60cadec9 SA	46	struct orion_spi {
60cadec9 SA	47	struct spi_master *master;
60cadec9 SA	48	void __iomem *base;
4574b886	49	struct clk *clk;
60cadec9 SA	50	};
60cadec9 SA	51
60cadec9 SA	52	static inline void __iomem spi_reg(struct orion_spi orion_spi, u32 reg)
	53	{
	54	return orion_spi->base + reg;
	55	}
	56
	57	static inline void
	58	orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	59	{
	60	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	61	u32 val;
	62
	63	val = readl(reg_addr);
	64	val \|= mask;
	65	writel(val, reg_addr);
	66	}
	67
	68	static inline void
	69	orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
	70	{
	71	void __iomem *reg_addr = spi_reg(orion_spi, reg);
	72	u32 val;
	73
	74	val = readl(reg_addr);
	75	val &= ~mask;
	76	writel(val, reg_addr);
	77	}
	78
60cadec9 SA	79	static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
	80	{
	81	u32 tclk_hz;
	82	u32 rate;
	83	u32 prescale;
	84	u32 reg;
	85	struct orion_spi *orion_spi;
	86
	87	orion_spi = spi_master_get_devdata(spi->master);
	88
4574b886	89	tclk_hz = clk_get_rate(orion_spi->clk);
60cadec9 SA	90
	91	/*
	92	* the supported rates are: 4,6,8...30
	93	* round up as we look for equal or less speed
	94	*/
	95	rate = DIV_ROUND_UP(tclk_hz, speed);
	96	rate = roundup(rate, 2);
	97
	98	/* check if requested speed is too small */
	99	if (rate > 30)
	100	return -EINVAL;
	101
	102	if (rate < 4)
	103	rate = 4;
	104
	105	/* Convert the rate to SPI clock divisor value. */
	106	prescale = 0x10 + rate/2;
	107
	108	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	109	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) \| prescale);
	110	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	111
	112	return 0;
	113	}
	114
b15d5d70 JG	115	static void
	116	orion_spi_mode_set(struct spi_device *spi)
	117	{
	118	u32 reg;
	119	struct orion_spi *orion_spi;
	120
	121	orion_spi = spi_master_get_devdata(spi->master);
	122
	123	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	124	reg &= ~ORION_SPI_MODE_MASK;
	125	if (spi->mode & SPI_CPOL)
	126	reg \|= ORION_SPI_MODE_CPOL;
	127	if (spi->mode & SPI_CPHA)
	128	reg \|= ORION_SPI_MODE_CPHA;
	129	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
	130	}
	131
60cadec9 SA	132	/*
	133	* called only when no transfer is active on the bus
	134	*/
	135	static int
	136	orion_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	137	{
	138	struct orion_spi *orion_spi;
	139	unsigned int speed = spi->max_speed_hz;
	140	unsigned int bits_per_word = spi->bits_per_word;
	141	int rc;
	142
	143	orion_spi = spi_master_get_devdata(spi->master);
	144
	145	if ((t != NULL) && t->speed_hz)
	146	speed = t->speed_hz;
	147
	148	if ((t != NULL) && t->bits_per_word)
	149	bits_per_word = t->bits_per_word;
	150
b15d5d70 JG	151	orion_spi_mode_set(spi);
b15d5d70 JG	152
60cadec9 SA	153	rc = orion_spi_baudrate_set(spi, speed);
	154	if (rc)
	155	return rc;
	156
495b3358 AL	157	if (bits_per_word == 16)
	158	orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	159	ORION_SPI_IF_8_16_BIT_MODE);
	160	else
	161	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
	162	ORION_SPI_IF_8_16_BIT_MODE);
	163
	164	return 0;
60cadec9 SA	165	}
	166
	167	static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
	168	{
	169	if (enable)
	170	orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	171	else
	172	orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
	173	}
	174
	175	static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
	176	{
	177	int i;
	178
	179	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
	180	if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
	181	return 1;
	182	else
	183	udelay(1);
	184	}
	185
	186	return -1;
	187	}
	188
	189	static inline int
	190	orion_spi_write_read_8bit(struct spi_device *spi,
	191	const u8 tx_buf, u8 rx_buf)
	192	{
	193	void __iomem tx_reg, rx_reg, *int_reg;
	194	struct orion_spi *orion_spi;
	195
	196	orion_spi = spi_master_get_devdata(spi->master);
	197	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
	198	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
	199	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
	200
	201	/* clear the interrupt cause register */
	202	writel(0x0, int_reg);
	203
	204	if (tx_buf && *tx_buf)
	205	writel((tx_buf)++, tx_reg);
	206	else
	207	writel(0, tx_reg);
	208
	209	if (orion_spi_wait_till_ready(orion_spi) < 0) {
	210	dev_err(&spi->dev, "TXS timed out\n");
	211	return -1;
	212	}
	213
	214	if (rx_buf && *rx_buf)
	215	(rx_buf)++ = readl(rx_reg);
	216
	217	return 1;
	218	}
	219
	220	static inline int
	221	orion_spi_write_read_16bit(struct spi_device *spi,
	222	const u16 tx_buf, u16 rx_buf)
	223	{
	224	void __iomem tx_reg, rx_reg, *int_reg;
	225	struct orion_spi *orion_spi;
	226
	227	orion_spi = spi_master_get_devdata(spi->master);
	228	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
229	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
230	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
231
232	/* clear the interrupt cause register */
233	writel(0x0, int_reg);
234
235	if (tx_buf && *tx_buf)
236	writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
237	else
238	writel(0, tx_reg);
239
240	if (orion_spi_wait_till_ready(orion_spi) < 0) {
241	dev_err(&spi->dev, "TXS timed out\n");
242	return -1;
243	}
244
245	if (rx_buf && *rx_buf)
246	put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
247
248	return 1;
249	}
250
251	static unsigned int
252	orion_spi_write_read(struct spi_device spi, struct spi_transfer xfer)
253	{
60cadec9 SA	254	unsigned int count;
	255	int word_len;
	256
60cadec9 SA	257	word_len = spi->bits_per_word;
	258	count = xfer->len;
	259
	260	if (word_len == 8) {
	261	const u8 *tx = xfer->tx_buf;
	262	u8 *rx = xfer->rx_buf;
	263
	264	do {
	265	if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
	266	goto out;
	267	count--;
	268	} while (count);
	269	} else if (word_len == 16) {
	270	const u16 *tx = xfer->tx_buf;
	271	u16 *rx = xfer->rx_buf;
	272
	273	do {
	274	if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
	275	goto out;
	276	count -= 2;
	277	} while (count);
	278	}
	279
	280	out:
	281	return xfer->len - count;
	282	}
	283
ba59a807 AL	284	static int orion_spi_transfer_one_message(struct spi_master *master,
ba59a807 AL	285	struct spi_message *m)
60cadec9	286	{
ba59a807 AL	287	struct orion_spi *orion_spi = spi_master_get_devdata(master);
	288	struct spi_device *spi = m->spi;
	289	struct spi_transfer *t = NULL;
	290	int par_override = 0;
	291	int status = 0;
	292	int cs_active = 0;
60cadec9	293
ba59a807 AL	294	/* Load defaults */
ba59a807 AL	295	status = orion_spi_setup_transfer(spi, NULL);
60cadec9	296
ba59a807 AL	297	if (status < 0)
ba59a807 AL	298	goto msg_done;
60cadec9	299
ba59a807	300	list_for_each_entry(t, &m->transfers, transfer_list) {
ba59a807 AL	301	if (par_override \|\| t->speed_hz \|\| t->bits_per_word) {
	302	par_override = 1;
	303	status = orion_spi_setup_transfer(spi, t);
	304	if (status < 0)
	305	break;
	306	if (!t->speed_hz && !t->bits_per_word)
	307	par_override = 0;
60cadec9 SA	308	}
60cadec9 SA	309
ba59a807 AL	310	if (!cs_active) {
	311	orion_spi_set_cs(orion_spi, 1);
	312	cs_active = 1;
	313	}
60cadec9	314
ba59a807 AL	315	if (t->len)
ba59a807 AL	316	m->actual_length += orion_spi_write_read(spi, t);
60cadec9	317
ba59a807 AL	318	if (t->delay_usecs)
	319	udelay(t->delay_usecs);
	320
	321	if (t->cs_change) {
	322	orion_spi_set_cs(orion_spi, 0);
	323	cs_active = 0;
	324	}
60cadec9 SA	325	}
60cadec9 SA	326
ba59a807 AL	327	msg_done:
	328	if (cs_active)
	329	orion_spi_set_cs(orion_spi, 0);
	330
	331	m->status = status;
	332	spi_finalize_current_message(master);
	333
	334	return 0;
60cadec9 SA	335	}
60cadec9 SA	336
2deff8d6	337	static int orion_spi_reset(struct orion_spi *orion_spi)
60cadec9 SA	338	{
	339	/* Verify that the CS is deasserted */
	340	orion_spi_set_cs(orion_spi, 0);
	341
	342	return 0;
	343	}
	344
2deff8d6	345	static int orion_spi_probe(struct platform_device *pdev)
60cadec9 SA	346	{
	347	struct spi_master *master;
	348	struct orion_spi *spi;
	349	struct resource *r;
4574b886	350	unsigned long tclk_hz;
60cadec9	351	int status = 0;
f814f9ac AL	352	const u32 *iprop;
f814f9ac AL	353	int size;
60cadec9	354
3fed8068	355	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
60cadec9 SA	356	if (master == NULL) {
	357	dev_dbg(&pdev->dev, "master allocation failed\n");
	358	return -ENOMEM;
	359	}
	360
	361	if (pdev->id != -1)
	362	master->bus_num = pdev->id;
f814f9ac AL	363	if (pdev->dev.of_node) {
	364	iprop = of_get_property(pdev->dev.of_node, "cell-index",
	365	&size);
	366	if (iprop && size == sizeof(*iprop))
	367	master->bus_num = *iprop;
	368	}
60cadec9	369
e7db06b5	370	/* we support only mode 0, and no options */
b15d5d70	371	master->mode_bits = SPI_CPHA \| SPI_CPOL;
e7db06b5	372
ba59a807	373	master->transfer_one_message = orion_spi_transfer_one_message;
60cadec9	374	master->num_chipselect = ORION_NUM_CHIPSELECTS;
495b3358	375	master->bits_per_word_mask = SPI_BPW_MASK(8) \| SPI_BPW_MASK(16);
5c678694	376	master->auto_runtime_pm = true;
60cadec9	377
24b5a82c	378	platform_set_drvdata(pdev, master);
60cadec9 SA	379
	380	spi = spi_master_get_devdata(master);
	381	spi->master = master;
60cadec9	382
bb489841	383	spi->clk = devm_clk_get(&pdev->dev, NULL);
4574b886 AL	384	if (IS_ERR(spi->clk)) {
	385	status = PTR_ERR(spi->clk);
	386	goto out;
	387	}
	388
c85012ad RK	389	status = clk_prepare_enable(spi->clk);
	390	if (status)
	391	goto out;
	392
4574b886	393	tclk_hz = clk_get_rate(spi->clk);
b52a37f5 AL	394	master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4);
b52a37f5 AL	395	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30);
60cadec9 SA	396
60cadec9 SA	397	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1729ce34 MB	398	spi->base = devm_ioremap_resource(&pdev->dev, r);
	399	if (IS_ERR(spi->base)) {
	400	status = PTR_ERR(spi->base);
4574b886	401	goto out_rel_clk;
60cadec9 SA	402	}
60cadec9 SA	403
5c678694 RK	404	pm_runtime_set_active(&pdev->dev);
	405	pm_runtime_use_autosuspend(&pdev->dev);
	406	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
	407	pm_runtime_enable(&pdev->dev);
	408
60cadec9	409	if (orion_spi_reset(spi) < 0)
5c678694 RK	410	goto out_rel_pm;
	411
	412	pm_runtime_mark_last_busy(&pdev->dev);
	413	pm_runtime_put_autosuspend(&pdev->dev);
60cadec9	414
f814f9ac	415	master->dev.of_node = pdev->dev.of_node;
5c678694	416	status = spi_register_master(master);
60cadec9	417	if (status < 0)
5c678694	418	goto out_rel_pm;
60cadec9 SA	419
	420	return status;
	421
5c678694 RK	422	out_rel_pm:
5c678694 RK	423	pm_runtime_disable(&pdev->dev);
4574b886 AL	424	out_rel_clk:
4574b886 AL	425	clk_disable_unprepare(spi->clk);
60cadec9 SA	426	out:
	427	spi_master_put(master);
	428	return status;
	429	}
	430
	431
2deff8d6	432	static int orion_spi_remove(struct platform_device *pdev)
60cadec9	433	{
5c678694 RK	434	struct spi_master *master = platform_get_drvdata(pdev);
5c678694 RK	435	struct orion_spi *spi = spi_master_get_devdata(master);
60cadec9	436
5c678694	437	pm_runtime_get_sync(&pdev->dev);
4574b886	438	clk_disable_unprepare(spi->clk);
4574b886	439
5c678694 RK	440	spi_unregister_master(master);
	441	pm_runtime_disable(&pdev->dev);
	442
60cadec9 SA	443	return 0;
	444	}
	445
	446	MODULE_ALIAS("platform:" DRIVER_NAME);
	447
5c678694 RK	448	#ifdef CONFIG_PM_RUNTIME
	449	static int orion_spi_runtime_suspend(struct device *dev)
	450	{
	451	struct spi_master *master = dev_get_drvdata(dev);
	452	struct orion_spi *spi = spi_master_get_devdata(master);
	453
	454	clk_disable_unprepare(spi->clk);
	455	return 0;
	456	}
	457
	458	static int orion_spi_runtime_resume(struct device *dev)
	459	{
	460	struct spi_master *master = dev_get_drvdata(dev);
	461	struct orion_spi *spi = spi_master_get_devdata(master);
	462
	463	return clk_prepare_enable(spi->clk);
	464	}
	465	#endif
	466
	467	static const struct dev_pm_ops orion_spi_pm_ops = {
	468	SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
	469	orion_spi_runtime_resume,
	470	NULL)
	471	};
	472
fd4a319b	473	static const struct of_device_id orion_spi_of_match_table[] = {
f814f9ac AL	474	{ .compatible = "marvell,orion-spi", },
	475	{}
	476	};
	477	MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
	478
60cadec9 SA	479	static struct platform_driver orion_spi_driver = {
	480	.driver = {
	481	.name = DRIVER_NAME,
	482	.owner = THIS_MODULE,
5c678694	483	.pm = &orion_spi_pm_ops,
f814f9ac	484	.of_match_table = of_match_ptr(orion_spi_of_match_table),
60cadec9	485	},
41ab724a	486	.probe = orion_spi_probe,
2deff8d6	487	.remove = orion_spi_remove,
60cadec9 SA	488	};
60cadec9 SA	489
41ab724a	490	module_platform_driver(orion_spi_driver);
60cadec9 SA	491
	492	MODULE_DESCRIPTION("Orion SPI driver");
	493	MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
	494	MODULE_LICENSE("GPL");